From patchwork Thu Apr 17 12:59:19 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dominik Haller X-Patchwork-Id: 14055568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56615C369B2 for ; Thu, 17 Apr 2025 13:09:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=QfrzKJThfwHn1MDCSW4YI61kPcQvkhcraL8X4f356ys=; b=V3mQESU5ARMUM8U7MIak14JlEo ZqZPphkyOmKSfBJhHA3h4m8vqnkfyx7xFQojija3FD7cEhx8dzyBwxP5hOBoz3HH/ubC7IYlcJZhV KRLbsWvxhDZVUqSnZG4sTIl4Il9OikCMsTvh+tUwawKbovX+s0gH7iCkFCixmm9L1QWizKeGYN0eK mHs+HIjllkm4FkT+96Sta6+2c3ZURp4kDGo13vmJteLiwUgieeTaArHFLRpMyxVTkvTvJnFpoa3uA Rng8S5NZdkD7X262NdFb06mSc1q2ATZ+HkGLkBM/2XKz28mzGL9y0W6Mu14cLTEU9qEQ+Q2xMEp36 Wlvxc99A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Ozh-0000000D5Zq-23Vw; Thu, 17 Apr 2025 13:09:29 +0000 Received: from mail-db8eur05on2100.outbound.protection.outlook.com ([40.107.20.100] helo=EUR05-DB8-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Oqt-0000000D465-3Ckd for linux-arm-kernel@lists.infradead.org; Thu, 17 Apr 2025 13:00:25 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=qLQ0Qq2W781FXxtoxojaGbAb7OSVcPXyFcnN9Daos+o7KKQ4y89bj5ou+YZ9FraE7xhMnPQ4lGAxLeX/OLq+6ekh1LzvOL3cnof6fyWoAuiMVEUpj9t4kgTgjUSdJOUm8x+54XNtLVZ33or7YWj/kegTRME/QZvmwom0sQjyHaz5AmuYx/fQ2AWWoSvY7jWspzimUhB2FHW5Wjf0TDklyyc0YPz0W7W1CAwHjIORdXi8R5ilOdO7ksMk/7CzZQdJH6FGjLN8DikwMmyMaLxazCkPv8oxnydyXaYekWpaiCwqHgmiRWMjrQq0Asx4PV8C/xsdqnUsMOGEWmKgrDJXFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QfrzKJThfwHn1MDCSW4YI61kPcQvkhcraL8X4f356ys=; b=PO2bLbIKkk1Byv6ewvxdbaE50h4UVoP3Dfyz5ELZY0eqHwhEvgTdK4rD+CCGf95AO7nYFGXPkwyokYRt9bctGg9fV05CnLp3zI/ibIaFmHUK1D8d6h1BiQUcSyx5H+mlDm4HkCXZaH5n7F9E0OKiZQsdfW1kRpKiCJ+Dx0siw9+Ax/oPRqVoJ0VAOVZDfJ/eqpY4X5/QGyVtoYwTJExrvi26D60STtcdcqTGnWEfoKpDGos3y8p48ydbQZNnMzO895aUvIE8jz61MtH4LucgGoKCl5qV3BzADl0a9UoD6HVyZ+LeLIRs/RWQKeNf1MkdNZzwiys1lHfaSxpP8IX2AA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=softfail (sender ip is 91.26.50.189) smtp.rcpttodomain=kernel.org smtp.mailfrom=phytec.de; dmarc=fail (p=quarantine sp=quarantine pct=100) action=quarantine header.from=phytec.de; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=phytec.de; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QfrzKJThfwHn1MDCSW4YI61kPcQvkhcraL8X4f356ys=; b=aR2vTgLAE8+EI29U7yKIYsY9QNRrRClYDRTqEzpB4S9G8cBUUoOPofT/c7VZ3GYIlA8GfWqKq7zj6XuFhm0o7DRo7XRgOo7tkgf/Co5sq4QNRocFZBNZY/kGfecRXERS9mu+9PBT39U2/saHPPR/s2/TXsXhPSEoucHGQGHqlmZp7B10FK4eWYqDo4kEmnKEhlA5p8bkNiBb+tl0Z0q1esxmuOQHAPfPhjZZmJnje9zFVWxY07ZWSO7KVnHEntDOKXOFi8Cz5Gw5ElrbGlHB3Z3cG4+GWmUPxau1FWOBOlq4rIQZ5dcp6DRyhHEALu9rGN/VjuTUzYkBXFJGIBV1Mg== Received: from AS4PR10CA0009.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:5dc::12) by AS8P195MB2164.EURP195.PROD.OUTLOOK.COM (2603:10a6:20b:5c3::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.32; Thu, 17 Apr 2025 13:00:16 +0000 Received: from AMS0EPF00000197.eurprd05.prod.outlook.com (2603:10a6:20b:5dc:cafe::cd) by AS4PR10CA0009.outlook.office365.com (2603:10a6:20b:5dc::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.22 via Frontend Transport; Thu, 17 Apr 2025 13:00:16 +0000 X-MS-Exchange-Authentication-Results: spf=softfail (sender IP is 91.26.50.189) smtp.mailfrom=phytec.de; dkim=none (message not signed) header.d=none;dmarc=fail action=quarantine header.from=phytec.de; Received-SPF: SoftFail (protection.outlook.com: domain of transitioning phytec.de discourages use of 91.26.50.189 as permitted sender) Received: from Diagnostix.phytec.de (91.26.50.189) by AMS0EPF00000197.mail.protection.outlook.com (10.167.16.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Thu, 17 Apr 2025 13:00:15 +0000 Received: from Florix.phytec.de (172.25.0.13) by Diagnostix.phytec.de (172.25.0.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 Received: from lws-haller.phytec.de (172.25.32.139) by Florix.phytec.de (172.25.0.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 From: Dominik Haller To: , , , , , , CC: , , Subject: [PATCH v3 1/3] dt-bindings: arm: ti: Add bindings for PHYTEC AM68x based hardware Date: Thu, 17 Apr 2025 14:59:19 +0200 Message-ID: <20250417125921.100580-1-d.haller@phytec.de> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Originating-IP: [172.25.32.139] X-ClientProxiedBy: Diagnostix.phytec.de (172.25.0.14) To Florix.phytec.de (172.25.0.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF00000197:EE_|AS8P195MB2164:EE_ X-MS-Office365-Filtering-Correlation-Id: 2c666cb4-ea84-42d1-d752-08dd7dafcc81 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: t50E2vk5ZYqTBxaGU3gw854tJcKSsnFU3NqwWxoQUukZ3707ctxZ2sNv389ZaSY9DSTesYJQzEMBdN4p/6nq1u7VXv9k4QmDE9HFe9geNXmtphvEzYdxhDUfo9UbN/So7v+rSL5/kPvNUrcYSrkEjUQWVz7eLz1MIdfHBAjfFYRnGOnwQ2e1N9xZ99zCFneSNwj0zivt3Nj2UztTWbAtdYRWwJuI1z34Jt8/LUwUqcY70NfSrI8Obh8CTMrTK9hDRvvCeWSaCm/c3pqLY1IyJ8+J1JDtofnPiw5h0YOtzYKn3a/2/WRPE35Zhm0bsiYipPi0/e+4qq0uzV6R4ybo1SKGqRsVTYQt4CX3iyQkf4esu5HgLttOwqVSFkIxennHSAnFHH+KKmtN/hlLorvnHK4xgWtBy433QwElqE9JNaZ5agDOK667vDO8YFvo/+9udDDAik1IrAM1e21d5PUcAvmjt8GH19AkcDoLVPKuqrwmTtnXFaqeWHjiuTIeKUL+JgOvWhLodbiA4DtJd+V7DvSCZwiiJ6oarQ1KdD8Bw2pJE9mrcMCna8TmTVycZCpAu41lfoRSjdoLvXyFj4jGW3nmexG3kk0BI3iqYXBZ5+3Ek6JJb2plv7g0irrHoXKcX//vbQ/tLxgDPVZN2peuTRC83Rpsk4OudkGNVHLGz63zIDqaKqbomWObxukqkufyA093QB/xCB5NjxcNqffizuw62QvPOGmXPH4ZSZ1T7EfqOxrmsrjcVjJPL0cu7gRHJ9EBDH0VEfNQal8LFALdekT6mfMoteBgRMLh84eAjNZ09RfQT8jiVs9ngLX2niNykTIoY9ElniYTcCs+ZWjpuu9e+gMTeB3N+lTy0gKvajTac6c/2RSgOWRbBw9X5oNNPRS1b4MaxXSKtWjcRE0sZqGg27FiRN1LBsErw6RhZz5KziDZmWgOKOir8MR5dQqVXMksaeAj2J+AeMedje2FAIYWxdiDx9O1wHUFIZ92lb4p+LlCJNHBJ4IlZoUkpRpv25MadZbJMrFEiZHCmofnTy3Y+pAAh2oaY2ug3NwwUQOH9TZ9RAcdXe5zD4wlNRJ/qnRTonL0+O+3uKHV/pPPBXOEjiphVjOijV+R0FPvnzjrcHLzm0blfYEifhB7X4TjBPFxw3H5D9+n8/is4auaELO2Vtwyaxz2ZziWOiwyLdfMr8g5Jgdyb/upsq/tmNfrfda3oOkAUFABRe8SmWbCqZ3bLTOixMSU3TsikAVHla2Z5tYv6ApoUFC6avxK7GqIS7HeNLn/BZG2rhzMIfD5sQffLQWY4vo0n6X/zlGk0hCKTsNBRR8esXhAiLLmqhTvmlesVq0LmbjemV6MNDWpIB9iFVrNWUdgMrSAU38n8+oxnZKCd6Ok2kdrLj0MYwBB8T8zryKOz1p/UESRLwTlmC50IylPh0BErKnyPi9RwkO/gLWrup30BUiRP82GKCbQDtkoahJil0LPREgvDtr2k0iRl3HKjxYKyxCFY4JNBJCw6o7mVDdhqr2fcYprE019 X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:Diagnostix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2025 13:00:15.9976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2c666cb4-ea84-42d1-d752-08dd7dafcc81 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000197.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P195MB2164 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250417_060024_094905_8ED87395 X-CRM114-Status: UNSURE ( 7.42 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add devicetree bindings for the AM68x based phyCORE-AM68x/TDA4x SoM and the phyBOARD-Izar carrier board. Signed-off-by: Dominik Haller --- Notes: Changes in v3: - reorganized compatibles into their own entry Changes in v2: - no changes Documentation/devicetree/bindings/arm/ti/k3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 18f155cd06c8..30631daf9a84 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -139,6 +139,13 @@ properties: - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J721s2 SoC Phytec SoM based boards + items: + - enum: + - phytec,am68-phyboard-izar + - const: phytec,am68-phycore-som + - const: ti,j721s2 + - description: K3 J722S SoC and Boards items: - enum: From patchwork Thu Apr 17 12:59:20 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dominik Haller X-Patchwork-Id: 14055571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAB01C369B2 for ; Thu, 17 Apr 2025 13:13:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mFiWPIUQ30QhnpGawsUqJt0h5zUORw8VS6349RBsYU8=; b=u11av5XfLqt5rBs1qJ/rzEngT8 NSodR9yXVpSdIu5MONKca6HZ+jDd+kBPyRfzwLXdun3rI50lVqHaV45JUIxv/D+JcpMrySUPv3LRq c9CJ8z+frxlIi3bR/RqMf6iwG7S090oPzhJg1D5yDnsWjsVdzBA2nif/Hwv5MeXnv8kI0b+mSutAH cUKtboTTDQu69uVEf+VrGd4Oqp6La5ySgvUFbFMg6wU+iPHcpGBfZ13adbpNt2wanUfVgaFxbZNEb pj98ND6Sjp6CXZ4Z5gzfCwVlXPdIOKsur8v6oIadg+369jzdT6wLLdLevV1xtAnD8Q+IA9anPhBgy 7vcjnL6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5P3L-0000000D6B1-1rW9; Thu, 17 Apr 2025 13:13:15 +0000 Received: from mail-vi1eur05on20715.outbound.protection.outlook.com ([2a01:111:f403:2613::715] helo=EUR05-VI1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Oqv-0000000D46x-3ssK for linux-arm-kernel@lists.infradead.org; Thu, 17 Apr 2025 13:00:27 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BErbW+Ka0exJJcLiEu77XymyONAoDg9gR4km5xq6eCh9EPwnu326cRHF5C6wAQ1mLDNmjtUsLxf16O7z2wAyVS226eY7fO1AAtkgL78wM8jdkgUIunFFx8hL6FGawPeGWDnzlWhDfKZyrwBMPNYEIx6ZNy1HYgITdo/SwoAWvXUBciWyFBkBTFkhexzBLppeeM4SLxPI/ncNgB1VPFJPOtaWSIXfTQHErbCXlheXQWif0Hh3OK4kvRlmkWwCe4LZkL3kXTJB7LDw9MNjhq1bbyLdTAuKkfzYZ+4Pxi7hg+mikLmdmHLtsTNQWWm6tvejYSkWhAPkwyNqJNvufK0qHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mFiWPIUQ30QhnpGawsUqJt0h5zUORw8VS6349RBsYU8=; b=TtRxNTDD0u5FCnH9yu7Uets62mg9gP9Ns7hRqaVpUopYfsdv1M1bcWZwT8wBATmELGiXOzsZ6Gjkvszbxpw6XjyL+I907FwAQNx3ZzWOr0dD0AFjceIK6e//vqIH1ZEZ5XpSfib5UhBr7QSddHBmKwORGqpNk7oCs8sbI4rUeXTuVnNEeXXJbEbO+YmXz9Lmg5/Olw1MO338e8I+uxfj+P5udJLI//tegTYdWpNohDNEDDtWE8PAzjKK0R5LLeHARHglHKgN0X4yheDrWtt6E7F8lZikVYD8TWxsphluiYYwllujeltOqRBrDyip6ZT09YpX4HhNcBifyo6atgu3Zg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=softfail (sender ip is 91.26.50.189) smtp.rcpttodomain=kernel.org smtp.mailfrom=phytec.de; dmarc=fail (p=quarantine sp=quarantine pct=100) action=quarantine header.from=phytec.de; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=phytec.de; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mFiWPIUQ30QhnpGawsUqJt0h5zUORw8VS6349RBsYU8=; b=Yv3J9wTo9B3WQXOaA3NVA9Ykf9HOQqefZJ6J7FfQ9uEQ84Gf9eTBpe2evUZkpBwAM/JXQednPjOljt6ciRENNUCbaBGVNjrhSf02HBy2a10JgVJIrs4a7s6ekU0EFchGqJUm2dWuImwU2cAaCiTsQV9G9leOTEIdXCusphxjalIulSQgdceuUkw1bg1BDTy7eKKJZn94s2Z0uTh0sKzawEFjtnspcx76nxuH6nU65ZglSujT6CZ//Q+88708+nylEbgDp5K/9BNuPJeGwI6TuQ0UJDiLg0cFix8HzBT5OkZAfhDXdQz2TqwTBmiUE1xW0ou7ALjELGFTN2Wc0Nr3Hw== Received: from AS4PR10CA0006.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:5dc::6) by PA1P195MB2514.EURP195.PROD.OUTLOOK.COM (2603:10a6:102:461::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.34; Thu, 17 Apr 2025 13:00:16 +0000 Received: from AMS0EPF00000197.eurprd05.prod.outlook.com (2603:10a6:20b:5dc:cafe::27) by AS4PR10CA0006.outlook.office365.com (2603:10a6:20b:5dc::6) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.18 via Frontend Transport; Thu, 17 Apr 2025 13:00:16 +0000 X-MS-Exchange-Authentication-Results: spf=softfail (sender IP is 91.26.50.189) smtp.mailfrom=phytec.de; dkim=none (message not signed) header.d=none;dmarc=fail action=quarantine header.from=phytec.de; Received-SPF: SoftFail (protection.outlook.com: domain of transitioning phytec.de discourages use of 91.26.50.189 as permitted sender) Received: from Diagnostix.phytec.de (91.26.50.189) by AMS0EPF00000197.mail.protection.outlook.com (10.167.16.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Thu, 17 Apr 2025 13:00:16 +0000 Received: from Florix.phytec.de (172.25.0.13) by Diagnostix.phytec.de (172.25.0.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 Received: from lws-haller.phytec.de (172.25.32.139) by Florix.phytec.de (172.25.0.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 From: Dominik Haller To: , , , , , , CC: , , Subject: [PATCH v3 2/3] arm64: dts: ti: Add basic support for phyBOARD-Izar-AM68x Date: Thu, 17 Apr 2025 14:59:20 +0200 Message-ID: <20250417125921.100580-2-d.haller@phytec.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250417125921.100580-1-d.haller@phytec.de> References: <20250417125921.100580-1-d.haller@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.32.139] X-ClientProxiedBy: Diagnostix.phytec.de (172.25.0.14) To Florix.phytec.de (172.25.0.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF00000197:EE_|PA1P195MB2514:EE_ X-MS-Office365-Filtering-Correlation-Id: d2be3590-7731-4f3e-853f-08dd7dafccd0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026|13003099007; X-Microsoft-Antispam-Message-Info: 4faLy18A7RxWuawi/vfdDzqB2DFLIB2y5iKw2G4nn8DIJH4ZE8tNF6U4YRISaQyDWSfVMUM5Etv6CuqvvlIXffUR5OxTcPAp9KKxEGmzx0pRbk1fnRaa/KbYogXtcOvodxeQfeCLFfOSQavy73TS3RLvgS3foM8QlDZHc1a1agWvEmpHL5I2KSHuU4/HT2waToJrpchNxHp0ZhAKqiLBlzOPHQrD3h/hv2oUUex6s6obc3Kak5o3AH/A0oiwt5lWcQsgm8h5Yhzhpw41FNeE2vajpz9fzGFkJswBgn3JW/Sz6UfBGCiGDFylVU262sKBaanFtf+pMdHB1Fehii2YDTly+r4AcyftAVGCuic3imfL3zRn7f7Ctiro/xyrroekOvX9ypcgB4KgTDD9QL0J/7JXKb2jWABW6WkD8H2GnOLes42zy9IH5f4S/No7tI+OPTmaZhvEnQ/nYXKcEGdH4zaa2DDCP+BuIdAz+frVwAUd3ZTfIpDZk3bOZXsG35OuiffL3LHwMrbfH8KB6/Itrux/d5WmjT/ZxlSFyWs4CtAAXIEzOx+YWqGMgv2k/3cHaGV3aHW6MPVYJeiSVHaK3RYZxfJadS17YDHb6pTATLQuG4hrC0COrfuhhp0ecHMlKbsQ0AJKMnT/b3SjOOszVKpr4WkvIGUh4YBMqfN1NG39f36KfGG7MXMMNAEI5X9+Jy2xo4Ztr3G6WDERutmAfzGBlo+LjpcHnkLn82LSoCRMHlPjvg/52+TrdElnWl3pqRfbDKFpthwEwnMeE+qFviJC6iicc2S9PTKuj9k0I4S+Mey6I0zrlrcQE3m8yMUCyNdgcwkc9jC6UH5cI75TBft8eW6qmnqRe7uKVnCuGhdnJoWIpS5TG23i+RsP1u+4daIn8ngPCrpCmb5ZkWHPbhGHut2RUF1xFudebrEGudp1yO1h+geMxAXHEf0byySJw0m2OGfDamqo58cIKjUZxUaV+HmnZ8jMrQRoymUDBnRYPmHPAWeuDMIH2ubL2WolZo6Mw/7xiEwRZKM9gw8YgSpgVxn90BV9KW4egUeyTCf+p4hr9p5raJbDeAShymwLXML/y69msDuProM7J4XWxCxQy7q8lX0rI0ZshRESM6r1QtxM5Ep1St2a1rYu7DqSk/PUBBx+hiODtvCes4JS0odW41q2/eyHNJYu7QQ3ZkyXf98MKEzTRpGpFLF/Cg0gyXtQYBZJd6Aonylw6sDvipuIs4UdAU2Hc6rpnmBtXQNFo1ijM3dZWMrtLcewFpxsHniS7N2n35cABl+VHmjbD9T2lgrGiQF/b849t5NPij0ncBKS6Y5+DeN9z/pIqJpcP5s2RkMET2Vlc8R0At6A0XCzZ1vijdOd6XOUm1UTW6z7eTgCF+TODtqej+Q7NvZt3VD+/u0TiRJk8HBiOmudKPPCYLpQISd4v59DlCTG1318+H8Np7WBIR0p8H6KuYQ31Wv+Qq/brMg5fJSWa0kVDQ== X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:Diagnostix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026)(13003099007);DIR:OUT;SFP:1102; X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2025 13:00:16.4976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2be3590-7731-4f3e-853f-08dd7dafccd0 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000197.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA1P195MB2514 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250417_060026_150299_3A5CC1D1 X-CRM114-Status: GOOD ( 15.91 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The phyCORE-AM68x/TDA4x [1] is a SoM (System on Module) featuring TI's AM68x/TDA4x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM68x/TDA4x (J721S2) family. A reference carrier board design, called phyBOARD-Izar is used for the phyCORE-AM68x/TDA4x development kit [2]. Supported features: * Debug UART * 2x SPI NOR Flash * eMMC * 2x Ethernet * Micro SD card * I2C EEPROM * I2C RTC * 2x I2C GPIO Expander * LEDs * USB 5 Gbit/s * PCIe For more details see the product pages for the SoM and the development kit: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ [2] https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ Signed-off-by: Dominik Haller Acked-by: Moteen Shah --- Notes: Bootlog: https://gist.github.com/dominiknh90/644e753c752b232117e12092e3691124 Link to v2: https://lore.kernel.org/linux-arm-kernel/20250415130458.33714-1-d.haller@phytec.de/ Link to v1: https://lore.kernel.org/linux-arm-kernel/20250411101004.13276-1-d.haller@phytec.de/ Changes in v3: - added phytec,am68-phycore-som compatible - pickup up Acked-by: Moteen Shah Changes in v2: - aliases reordered - stdout-path set to &main_uart8 - fixed coding style in serdes0 node - dropped whitespaces in commit message arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am68-phyboard-izar.dts | 579 +++++++++++++++++ .../boot/dts/ti/k3-am68-phycore-som.dtsi | 594 ++++++++++++++++++ 3 files changed, 1174 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 03d4cecfc001..3f18ca4029c3 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -109,6 +109,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC +dtb-$(CONFIG_ARCH_K3) += k3-am68-phyboard-izar.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts new file mode 100644 index 000000000000..842952e13ea3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + * + * https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ + */ + +/dts-v1/; + +#include +#include +#include +#include +#include "k3-am68-phycore-som.dtsi" + +#include "k3-serdes.h" + +/ { + compatible = "phytec,am68-phyboard-izar", + "phytec,am68-phycore-som", "ti,j721s2"; + model = "PHYTEC phyBOARD-Izar-AM68x"; + + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart8; + serial3 = &main_uart1; + serial4 = &main_uart2; + mmc1 = &main_sdhci1; + ethernet0 = &cpsw_port1; + }; + + chosen { + stdout-path = &main_uart8; + }; + + transceiver1: can-phy1 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver2: can-phy2 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <8000000>; + }; + + vcc_12v0: regulator-12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "VCC_IN"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_1v8: regulator-vcc-1v8 { + /* Output of TLV7158P */ + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-vcc-3v3 { + /* Output of SiC431 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + }; + + vcc_5v0: regulator-vcc-5v0 { + /* Output of LM5116 */ + compatible = "regulator-fixed"; + regulator-name = "VCC_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_12v0>; + }; +}; + +&main_pmx0 { + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (V27) MCASP1_AXR1.I2C2_SCL */ + J721S2_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (W27) MCASP1_AXR2.I2C2_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ + J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ + >; + }; + + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + + main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ + >; + }; + + main_mcan1_pins_default: main-mcan1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c8, PIN_INPUT, 4) /* (AD28) EXT_REFCLK1.MCAN1_RX */ + J721S2_IOPAD(0x06c, PIN_OUTPUT, 0) /* (V26) MCAN1_TX */ + >; + }; + + main_mcan13_pins_default: main-mcan13-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ec, PIN_INPUT, 9) /* (AG25) TIMER_IO1.MCAN13_RX */ + J721S2_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AE28) MCAN13_TX */ + >; + }; + + main_mcan16_pins_default: main-mcan16-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + bootph-all; + }; + + main_spi6_pins_default: main-spi6-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x030, PIN_INPUT, 8) /* (T26) GPIO0_12.SPI6_CLK */ + J721S2_IOPAD(0x080, PIN_INPUT, 8) /* (U26) MCASP0_AXR4.SPI6_CS2 */ + J721S2_IOPAD(0x0c4, PIN_OUTPUT, 8) /* (AB26) ECAP0_IN_APWM_OUT.SPI6_D0 */ + J721S2_IOPAD(0x074, PIN_INPUT, 8) /* (R28) MCAN2_TX.SPI6_D1 */ + J721S2_IOPAD(0x0dc, PIN_OUTPUT, 7) /* (AH26) SPI0_D1.GPIO0_55 */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x05c, PIN_INPUT, 11) /* (AA26) MCASP2_AXR0.UART1_CTSn */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 11) /* (AC27) MCASP2_AXR1.UART1_RTSn */ + J721S2_IOPAD(0x054, PIN_INPUT, 11) /* (Y27) MCASP2_ACLKX.UART1_RXD */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 11) /* (AA27) MCASP2_AFSX.UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d8, PIN_INPUT, 11) /* (AG26) SPI0_D0.UART2_RXD */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 11) /* (U28) MCAN0_RX.UART2_TXD */ + >; + }; + + main_uart8_pins_default: main-uart8-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + bootph-all; + }; +}; + +&wkup_pmx1 { + mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + >; + }; +}; + +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_i2c1_pins_default: mcu-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ + J721S2_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x038, PIN_INPUT, 0) /* (B27) MCU_SPI0_CLK */ + J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B26) MCU_SPI0_CS0 */ + J721S2_WKUP_IOPAD(0x068, PIN_INPUT, 2) /* (C23) WKUP_GPIO0_4.MCU_SPI0_CS3 */ + J721S2_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (D24) MCU_SPI0_D0 */ + J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 0) /* (B25) MCU_SPI0_D1 */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (E25) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (F28) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ + >; + bootph-all; + }; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&phy0>; +}; + +&davinci_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mdio_pins_default>; + + phy0: ethernet-phy@0 { + reg = <0>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + }; +}; + +&i2c_som_rtc { + trickle-resistor-ohms = <3000>; +}; + +&main_i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + status = "okay"; + + exp1: gpio@20 { + compatible = "nxp,pca9672"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HALF/nFULL_EN", "RS485/nRS232_EN", "MCU_ETH_nRESET", "", + "PCIe_nRESET", "USB2.0-Hub_nRESET", "USB3.0-Hub_nRESET", "PEB_AV_BL_EN"; + interrupt-parent = <&main_gpio0>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + exp2: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "RPI_GPIO4", "RPI_GPIO5", "RPI_GPIO6", "RPI_GPIO19", + "RPI_GPIO20", "RPI_GPIO21", "RPI_GPIO22", "RPI_GPIO23", + "RPI_GPIO24", "RPI_GPIO25", "RPI_GPIO26", "RPI_GPIO20", + "LVDS_BL_nEN", "LVDS_REG_nEN", "CSI_CAM0_nRESET", "CSI_CAM1_nRESET", + "CSI0_CTRL1", "CSI0_CTRL2", "CSI0_CTRL3", "CSI0_CTRL4", + "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3", "CSI1_CTRL4"; + interrupt-parent = <&main_gpio0>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; + }; +}; + +/* CSI0 + RPI */ +&main_i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c4_pins_default>; +}; + +/* CSI1 + PCIe */ +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins_default>; + phys = <&transceiver1>; + status = "okay"; +}; + +&main_mcan13 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan13_pins_default>; + phys = <&transceiver2>; + status = "okay"; +}; + +&main_mcan16 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan16_pins_default>; + phys = <&transceiver3>; + status = "okay"; +}; + +/* SD-Card */ +&main_sdhci1 { + pinctrl-0 = <&main_mmc1_pins_default>; + pinctrl-names = "default"; + disable-wp; + vmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&main_spi6 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi6_pins_default>; + cs-gpios = <&main_gpio0 55 GPIO_ACTIVE_LOW>; + ti,spi-num-cs = <1>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + uart-has-rtscts; + status = "okay"; +}; + +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; + status = "okay"; +}; + +&main_uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; + bootph-all; + status = "okay"; +}; + +&mcu_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>; +}; + +&mcu_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + status = "okay"; +}; + +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver4>; + status = "okay"; +}; + +/* RPI-Header */ +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins_default>; +}; + +/* RPI-Header */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; + uart-has-rtscts; + status = "okay"; +}; + +&ospi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <40000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + }; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = , , + , ; +}; + +&serdes_refclk { + clock-frequency = <100000000>; +}; + +&serdes0 { + status = "okay"; + + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,phy-type = ; + }; + + serdes0_usb_link: phy@1 { + reg = <1>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + resets = <&serdes_wiz0 2>; + cdns,phy-type = ; + }; +}; + +&tscadc0 { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&tscadc1 { + status = "okay"; + + adc { + ti,adc-channels = <3 4 5 6 7>; + }; +}; + +&usbss0 { + ti,vbus-divider; + status = "okay"; +}; + +&usb0 { + dr_mode = "host"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&usb_serdes_mux { + idle-states = <1>; /* USB0 to SERDES lane 1 */ +}; + +&wkup_i2c0 { + eeprom@57 { + compatible = "atmel,24c32"; + reg = <0x57>; + pagesize = <32>; + }; + + led-controller@62 { + compatible = "nxp,pca9533"; + reg = <0x62>; + + led-1 { + label = "user-led1"; + type = ; + }; + + led-2 { + label = "user-led2"; + type = ; + }; + + led-3 { + label = "user-led3"; + type = ; + }; + }; +}; + +/* Shared with TIFS */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + uart-has-rtscts; + bootph-all; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi new file mode 100644 index 000000000000..f9fb0c78ccde --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + * + * https://www.phytec.eu/en/produkte/system-on-modules/phycore-am68x-tda4x/ + */ + +/dts-v1/; + +#include +#include +#include "k3-j721s2.dtsi" + +/ { + compatible = "phytec,am68-phycore-som", "ti,j721s2"; + model = "PHYTEC phyCORE-AM68x"; + + aliases { + ethernet1 = &main_cpsw_port1; + mmc0 = &main_sdhci0; + rtc0 = &i2c_som_rtc; + }; + + memory@80000000 { + device_type = "memory"; + /* 4GB RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x20000000>; + linux,cma-default; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a5100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa5100000 0x00 0xf00000>; + no-map; + }; + + c71_0_dma_memory_region: c71-dma-memory@a6000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6000000 0x00 0x100000>; + no-map; + }; + + c71_0_memory_region: c71-memory@a6100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa6100000 0x00 0xf00000>; + no-map; + }; + + c71_1_dma_memory_region: c71-dma-memory@a7000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7000000 0x00 0x100000>; + no-map; + }; + + c71_1_memory_region: c71-memory@a7100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa7100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a8000000 { + reg = <0x00 0xa8000000 0x00 0x01c00000>; + alignment = <0x1000>; + no-map; + }; + }; + + vdd_sd_dv: regulator-sd { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "VDD_SD_DV"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + gpios = <&main_gpio0 1 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0>, + <1800000 0x1>; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_pins_default: main-cpsw-mdio-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24) I2C0_SDA */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x004, PIN_OUTPUT, 7) /* (W25) MCAN12_TX.GPIO0_1 */ + >; + }; +}; + +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ + J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (F18) MCU_OSPI0_D3 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (E19) MCU_OSPI0_D4 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D5 */ + J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (F19) MCU_OSPI0_D6 */ + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D7 */ + J721S2_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (E18) MCU_OSPI0_DQS */ + >; + bootph-all; + }; +}; + +&wkup_pmx1 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 7) /* (C21) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ + >; + }; +}; + +&wkup_pmx2 { + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x098, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x09c, PIN_INPUT_PULLUP, 0) /* (H27) WKUP_I2C0_SDA */ + >; + bootph-all; + }; +}; + +&c71_0 { + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; + status = "okay"; +}; + +&c71_1 { + mboxes = <&mailbox0_cluster4 &mbox_c71_1>; + memory-region = <&c71_1_dma_memory_region>, + <&c71_1_memory_region>; + status = "okay"; +}; + +&mailbox0_cluster0 { + interrupts = <436>; + status = "okay"; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster1 { + interrupts = <432>; + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster2 { + interrupts = <428>; + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&mailbox0_cluster4 { + interrupts = <420>; + status = "okay"; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c71_1: mbox-c71-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; +}; + +&main_cpsw { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins_default>; + status = "okay"; +}; + +&main_cpsw_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_pins_default>; + status = "okay"; + + phy1: ethernet-phy@0 { + reg = <0>; + ti,clk-output-sel = ; + ti,fifo-depth = ; + ti,min-output-impedance; + ti,rx-internal-delay = ; + }; +}; + +&main_cpsw_port1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + + temperature-sensor@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + }; + + i2c_som_rtc: rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + }; +}; + +&main_gpio0 { + status = "okay"; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +/* eMMC */ +&main_sdhci0 { + disable-wp; + non-removable; + ti,driver-strength-ohm = <50>; + bootph-all; + status = "okay"; +}; + +/* SD card */ +&main_sdhci1 { + vqmmc-supply = <&vdd_sd_dv>; + bootph-all; +}; + +&main_r5fss0 { + ti,cluster-mode = <0>; +}; + +&main_r5fss1 { + ti,cluster-mode = <0>; +}; + +/* Timers are used by Remoteproc firmware */ +&main_timer0 { + status = "reserved"; +}; + +&main_timer1 { + status = "reserved"; +}; + +&main_timer2 { + status = "reserved"; +}; + +&main_timer3 { + status = "reserved"; +}; + +&main_timer4 { + status = "reserved"; +}; + +&main_timer5 { + status = "reserved"; +}; + +&mcu_r5fss0_core0 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + memory-region = <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0_core1 { + mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; + memory-region = <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; +}; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + status = "okay"; + + serial_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + bootph-all; + }; +}; + +&wkup_gpio0 { + status = "okay"; +}; + +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu_avs: regulator@40 { + compatible = "ti,tps62873"; + reg = <0x40>; + regulator-name = "VDD_CPU_AVS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + bootph-pre-ram; + }; + + pmic@48 { + compatible = "ti,tps6594-q1"; + reg = <0x48>; + system-power-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_irq_pins_default>; + interrupt-parent = <&wkup_gpio0>; + interrupts = <39 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + buck12-supply = <&vcc_3v3>; + buck3-supply = <&vcc_3v3>; + buck4-supply = <&vcc_3v3>; + buck5-supply = <&vcc_3v3>; + ldo1-supply = <&vcc_3v3>; + ldo2-supply = <&vcc_3v3>; + ldo3-supply = <&vcc_3v3>; + ldo4-supply = <&vcc_3v3>; + ti,primary-pmic; + + regulators { + bucka12: buck12 { + regulator-name = "VDD_DDR_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka3: buck3 { + regulator-name = "VDD_RAM_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name = "VDD_IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name = "VDD_MCU_0V85"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name = "VDD_MCUIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name = "VDD_MCUIO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name = "VDDA_DLL_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name = "VDDA_MCU_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + bootph-all; + }; + + som_eeprom_opt: eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; From patchwork Thu Apr 17 12:59:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dominik Haller X-Patchwork-Id: 14055670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B635FC369B2 for ; Thu, 17 Apr 2025 14:13:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SARyRxrKg3qek/4+8wUuOEhGgsOEF3Uaa//5s3TbaH0=; b=KfrszF4C/7FUqGCTZFiFaoRZSF 3LN66RKRoCIjb0V28VsL7/Y8XDjtrHPidPOVPAtUgkADP6dWbDQBu06DzsKchh+Bf24U+5UuncWwk WjvOhht8jCx3SYVLZv7hnQ9kapzbsa7IV/6EF6FiL8VuVz/dMvHyGqz9OYfhPlAOjitW5LnnzDZp1 FP4H8L/wIVGU277dY0XZpiVJzchENn/Q6Dkc0lmdGZ2KGP5p/UMvDLp7YTOtf9Pq+BNr0RHTVuUjY 7AjxwQXuASfgva/nRt9MiuuYavBlle7PMMzKDtSyinbE0e1L8P0mD+mRnBRLCIjMR23NTx5ePGvjg m7Hj/m2Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Pzi-0000000DGgw-41Fs; Thu, 17 Apr 2025 14:13:35 +0000 Received: from mail-vi1eur03on2071a.outbound.protection.outlook.com ([2a01:111:f403:260c::71a] helo=EUR03-VI1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5Oqv-0000000D46D-2F7G for linux-arm-kernel@lists.infradead.org; Thu, 17 Apr 2025 13:00:26 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uXxnCeDKXFYRmEu2l5vNlOYKc9wbRHPogxU0pdw0M6Du78t2Cad+DOAdR/cxXQ0VDG5j3NdM9o6QFe6jCSX590JQq3P7B5ldvKZW4SNS4Zug+uUPi9ZfNc+BwTlcUgQKqYfaME/X7UOrR7fdU3hiccmc5OHKflt6/5Do3lOcLL4b8xWTllWffDAQ1d1fF+oVZjVJEX6dOociopX+LF/BKGiPgZSvV1HKhs3be8QdP3Xm+vFy2F5o8d8bDjpgOhtTmQ4nL85qRUJ0vUQCo1AJE5KAGrvl4dA7KEwgLDIl9YKQATuivkxw2JK1WUOttDXwN18jQmHAocYzrkhcRJy5eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SARyRxrKg3qek/4+8wUuOEhGgsOEF3Uaa//5s3TbaH0=; b=XVmmBr62jJbpQEOFJX9SjpVpQLUgZHo4pB2MI4Sgh9Bt6mNetoRV3BXCutwK8P5IDNucgsPhBBMFQBhR0cIfu9PU1xBQUJ+cJob9Kfi3+epXbJF6K944H5w9WcgZuiUwUUekdGM/u7ZgcJ5J2HkG0TY8EpQk5bl2Fj12ROo6CpbfB5+PfggOzrUy4LGoj6uvu6ZLBzd+Aa5CoGF0AUM/EzQvbQxjEuR2Bda+m+2NPukjQsDMsgp0DMOxqN7z3dDc2NWtgXM3RYRM5LJCeEcz5drz6yVnnH5nwKzCeSd93XaedWSwO8ZsUzgdI0SlwFZWjF2Z9RtQtrvoZcfAVYyz6A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=softfail (sender ip is 91.26.50.189) smtp.rcpttodomain=kernel.org smtp.mailfrom=phytec.de; dmarc=fail (p=quarantine sp=quarantine pct=100) action=quarantine header.from=phytec.de; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=phytec.de; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SARyRxrKg3qek/4+8wUuOEhGgsOEF3Uaa//5s3TbaH0=; b=uLQQOK0iTuW/Dt7D5IxqLKInpw+1ZXzwz2sdu9GEoQPgaiQuw1YfEWIliX2i0M+lWgoaCIfx4biaWfLE4j2PAp9Z2KU5XFLYONcn7haeY/HIP5jOurvYyVlaJF07mTHUjEFYjRl55LOH9QMbaDEtXsgJFlxmnXSk9jPlD9aURkm44Y3hSprIk/9zHGbDG2x4m5gx9xxP7C3wqDzg1IYMunpzrIPbHenxucneMrn8uorZDG/YRr6ZJ3weCbjJOFkJon3HnL38HqSUIqcjjuATbiQHs/f12xZ0VFk/PA6R5+N3jYLew7tOR8Lfy3B5tzxZdNF3M3BRr30WiYsqsHfWKw== Received: from AS4PR10CA0003.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:5dc::16) by DB9P195MB1354.EURP195.PROD.OUTLOOK.COM (2603:10a6:10:295::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8655.22; Thu, 17 Apr 2025 13:00:17 +0000 Received: from AMS0EPF00000197.eurprd05.prod.outlook.com (2603:10a6:20b:5dc:cafe::62) by AS4PR10CA0003.outlook.office365.com (2603:10a6:20b:5dc::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8655.18 via Frontend Transport; Thu, 17 Apr 2025 13:00:17 +0000 X-MS-Exchange-Authentication-Results: spf=softfail (sender IP is 91.26.50.189) smtp.mailfrom=phytec.de; dkim=none (message not signed) header.d=none;dmarc=fail action=quarantine header.from=phytec.de; Received-SPF: SoftFail (protection.outlook.com: domain of transitioning phytec.de discourages use of 91.26.50.189 as permitted sender) Received: from Diagnostix.phytec.de (91.26.50.189) by AMS0EPF00000197.mail.protection.outlook.com (10.167.16.219) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Thu, 17 Apr 2025 13:00:17 +0000 Received: from Florix.phytec.de (172.25.0.13) by Diagnostix.phytec.de (172.25.0.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 Received: from lws-haller.phytec.de (172.25.32.139) by Florix.phytec.de (172.25.0.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 17 Apr 2025 15:00:15 +0200 From: Dominik Haller To: , , , , , , CC: , , Subject: [PATCH v3 3/3] arm64: defconfig: Enable TMP102 as module Date: Thu, 17 Apr 2025 14:59:21 +0200 Message-ID: <20250417125921.100580-3-d.haller@phytec.de> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250417125921.100580-1-d.haller@phytec.de> References: <20250417125921.100580-1-d.haller@phytec.de> MIME-Version: 1.0 X-Originating-IP: [172.25.32.139] X-ClientProxiedBy: Diagnostix.phytec.de (172.25.0.14) To Florix.phytec.de (172.25.0.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AMS0EPF00000197:EE_|DB9P195MB1354:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c6be577-f9e7-4716-f7f8-08dd7dafcd23 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: OGCFZdTCgLuZaviXHbX0Cx1F47zGLTvZzErdgTEdo78gU6ijRoOnbv1JNEWYrxpOZo1nZfS3yb2x0yVlxEv9j0wUG/BKm/Q06Om19QV7xoOMKVlsFO9NzjVhXI136tFBvYbYJRzETf4aSUroAed9FYX7eokU+jpw9o/4dJBeE+LJ8uAd2W2n9PvlMVy3fvY6h/ZKN8zyJclQsxIIbu4DDQzNDUab24BUB9Sl9ypeM4U2SM0Y3/ZSVxjjwYNtr29G3LBYdLsSGx7JTEbmUgG9JSc3/drj0gHfBPaIDrryFKEFNR9tYSas3j8//Q3kLF6UvMJw7YJU9fKoE7QQjHMZOQAHXomKpQAoiQyf/KWU2VTjgKSxWPPoMOL4yho6PWmc7hodkHOdEkXutvjGbOI2YUSk6kMEZ2pVjqnIJRHVyoOxWWhbYiGSFWzmhKzryOfTKpAbDRbcYCoE2T9IzlG1gxBH6p/Opc8FHx8jpEnbiDca7MEC+FUdMkm1oY6V997ky90CeEutd0BjDyUX0UINLoQSZNmM789C9vXb4ugxJQoppluQrOP+65zj1ath6+DI4Ah67DdpXJ84fg5jzR4BDiSZ0JJOuinImmUvYhckLXg6RW1BLYEMSRIHTD4UHk+IFa4wRKuzKjph1lTrHCXcQ/KyOhNvli6M3t3CIyFT32iFe4XI9POyID9V2NKeHrL7JmcizJz7vrW++nt4oNRILqhy/3KOipioY+kGJu/L3XobgDrAO4MmEyfDAKet/q61U1EezD8iPGVGH8LQD4t4YJlFIPKLCe29EBTYTyrEjHSDSc1q5RMUFohPmE54s1YG+zBEcov3pS2gZMr5pb7J2yq8sPAAFtms9Bkqg1mDIjOzX5eaTpOPP3ckdGDiCzQqbXrRM7+GJQfWgZuAtsMS6x+9BS+4cPPduuI3MJ3n8BrvPD6cVGEStrJWPfxOBm9lLJwZLpapoRaRAN8OiaNIupuZCp6xBb/yVMUBniXWL1DAIVaO960CtG+K4Tc4C4LMwQ/6OYM2BQ9VlzI+NRiDU8U3mcZl6dDoia4XJpdcfEL6Pc13AolLb2VC8LaxaNY1lGQ3Q4Z8u7QK7DchIJbsiPgpBYgLGu1eSp8BBYfacOKDIZ5WRoNdWdr5aes4GkOUevD51cPrCalaxKFwiorebmBuayjvBfpcrHtuK0f8JTumTXJtu0mg3UmGS3q25MTC38PCA8AlDJlAnxe7eH/M5d1bg+FdSASsU63AZb7bBZS9zTZuBvnXN5ML7TtJjJdFdSnTcor7Bmy3TDrVcqrTxzFI4Jw6Ya/Nc25uI1TKG/QDV293lhOZ7+1Os97kx9jEIm/aC6DjU2sp8mltiPxQOlAII6iO8GLgnuTrqn8sA6fwDKWPSNHcnO4/cJttNrE/HL7fHlcQEQtwNZBcxqHX2C6kAZlrfMYORpcvGL8ZLPJUckMkQErULqhyi7u3WTZfpA62gY/8TqmoontPIPgKnVCuDmK10QeweSVwEcorVQlqJFfNZESX3pypXqyqYmnQ X-Forefront-Antispam-Report: CIP:91.26.50.189;CTRY:DE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:Diagnostix.phytec.de;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2025 13:00:17.0601 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c6be577-f9e7-4716-f7f8-08dd7dafcd23 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF00000197.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9P195MB1354 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250417_060025_577389_AF914097 X-CRM114-Status: UNSURE ( 8.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the driver for the TI TMP102 temperature sensors used on the Phytec phyCORE-AM68x/TDA4x and the phyGATE-Tauri-L-iMX8MM. Signed-off-by: Dominik Haller --- Notes: Changes in v3: - no changes Changes in v2: - new patch in series arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..54e6705f9752 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -702,6 +702,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TMP102=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y