From patchwork Fri Apr 18 14:53:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B21ADC369CA for ; Fri, 18 Apr 2025 14:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lW9HadnW3ISct7FxJQCIq92tdRch392jIK2A7igLrA8=; b=0qu/N0/cRRi0ST u25dy3DdhhYQolZ2vwWQGrwzuyWylOV/J2WbjP9nhvu5dfXJ7mXfj5UIBUgn1PBUq6T0MySp8DI2D hC603pYmRluTWz9BlucMhHfNAvq4+OESR4a4yi08er0A4eSpsGvIARNVVZTY1NeiGzEm4OKXnF1TK Ncqxf2iMl0lnmhjh1OlvXSZLlOnBTcXq/cWXH5MhnvmWi+mDt7x6bwEEFOuEfqnNHl4hWw0O7sHro tCKIXo854Ah/OmoeiDsvrNXPNunP/xIsNrEBnZ2n2Jf7XNLTBwfQ1Si3CRaltEvne9RmEmxDEjMBH 2W6WFtmGvhDdVvnU2Rmg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8C-0000000GWyd-1W6m; Fri, 18 Apr 2025 14:55:52 +0000 Received: from mail-qt1-x829.google.com ([2607:f8b0:4864:20::829]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6W-0000000GWOV-3Vjf for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:09 +0000 Received: by mail-qt1-x829.google.com with SMTP id d75a77b69052e-477296dce8dso18122701cf.3 for ; Fri, 18 Apr 2025 07:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988048; x=1745592848; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=81a1v+nMC7nJeIGTMZQ54emwTNg/YN8dMbbTK1LgyT8=; b=jo6M19YK0E5+enjaSe+Pay3MgVpmQWvmvkeb9jRYhDQxzGOyhXCVC3dwZEc39h6kPO toVyci3lbj02dj2jfJyt2g9XL/e14SQewcbMHf9/92+x9Z6kbktL8Qx2vRVZhYP/67/t EwkpCwuKV7mody6XLmmHDiQQGjcNjgC21gbmMOsyLxaiJNwBYW1sAHU1IIIyZeQJ0hOg Q59h552YM+8DJJAuw7KlCRTIISTEl7QXMguD94RbyAgO/jM1Kqumr5KZud+kLSNty5LF VXk7QMUtGIh5E/iHt+t3xfiuhOs8pv9hEhCJaZtYlNQROazWnijsb4aAkDvdUR6ZkT0Y fSRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988048; x=1745592848; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=81a1v+nMC7nJeIGTMZQ54emwTNg/YN8dMbbTK1LgyT8=; b=squgNazlRTyvqmPZJkGvT8RSPVS6QLavEejY6qXHQSueVsd9bhqXDbENGmUbIGinqW zWt1CGdIIRAbF+qNoT2e0RuoRa5egES1Sxi4serEpPSkW89HbJlZMTQjGLg+6ZLfZgPr FfoA95e2PkxXPNsnGn0vlgOE2ICJRIgvIk2qcS4g7NMNmzL/iprcbgv7MT/LKVCzpv6L Woc7diOGuo7xHJGHSjCU86C6E/dxOUorSlEVo12AVGZaLaR/2gMLkvy91NcK+6k239lO fLeLI326folzgPxJ5Nr7LH3D1o6JD3aR02zvvVffxwJmu3LDNeidH8Yiq0W3pdt5qW6a wyzg== X-Forwarded-Encrypted: i=1; AJvYcCVEVgV+qHT/IsKHihsv4kdApbimnlUvTDzbjzlZ89cEZhnb6t1hFxbf/9Lnrj+jOhXwby4iid48WHvzWA==@lists.infradead.org X-Gm-Message-State: AOJu0Yx4BIkwAGF1hxOwAcVp6iWLUnk8BZsEdvKoZUlU4vJrwV/ZEXhC ALe/LYYn6SQXVk7wxTKGX74f2TDGFPXhM+7Y391LinIIxLMAW0rYoiUIcPKT64Y= X-Gm-Gg: ASbGncsyXPAvVixoofJuj5hrk8Ko259CYqpNIeMZYjRVK4bdeNxhOybfSaI8WTJGlKP gHl8bWU//kgzUUlRY1yRUOo7UHTsN/P/IDE2OZ7m00UQvIELRBE1LQQQm//W6jdUCIMNAF4DVP3 nWNQK7svSNCu/Oemge+430okKAV388DLdyTfrtFzXArR7pMv/XbhTwUNBSlsrh0EC12FHm6a+Yg Bra5OGRBLgGE862F2lmH1M4lwySlJTpt5xcKbN5cyOiPyCrIeYoSSX9VtpctmJQcDgJAxuwbTzP DrTooIRruXnv0N8VCPBs4ZZ0LeiNEtFQhhvjlA/7Gad9MwPINaQP6dMKynTZZi83mUFjdzwRFgF AsXwtm59nXqCCKw== X-Google-Smtp-Source: AGHT+IGnwYLPi26HcaYRuJb1HCtQR40oX+awr6yWA9tTAcIKCeZh7T5uLErh0fblqbjjE1+0Wh4r/Q== X-Received: by 2002:ac8:7d8f:0:b0:475:287:12fb with SMTP id d75a77b69052e-47aec4b6843mr45320001cf.36.1744988047731; Fri, 18 Apr 2025 07:54:07 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:07 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v5 1/7] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets Date: Fri, 18 Apr 2025 09:53:53 -0500 Message-ID: <20250418145401.2603648-2-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075408_874756_4AD0AFDE X-CRM114-Status: GOOD ( 10.36 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will (initially) support only resets. They do not incorporate power domain functionality. Previously the clock properties were required for all compatible nodes. Make that requirement only apply to the three existing CCUs (APBC, APMU, and MPMU), so that the new reset-only CCUs can go without specifying them. Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks). Signed-off-by: Alex Elder Reviewed-by: Krzysztof Kozlowski --- .../soc/spacemit/spacemit,k1-syscon.yaml | 29 +++- .../dt-bindings/clock/spacemit,k1-syscon.h | 128 ++++++++++++++++++ 2 files changed, 150 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml index 30aaf49da03d3..133a391ee68cd 100644 --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml @@ -19,6 +19,9 @@ properties: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 reg: maxItems: 1 @@ -47,9 +50,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - - "#clock-cells" - "#reset-cells" allOf: @@ -57,13 +57,28 @@ allOf: properties: compatible: contains: - const: spacemit,k1-syscon-apbc + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu then: - properties: - "#power-domain-cells": false - else: required: - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu + then: + required: + - clocks + - clock-names + - "#clock-cells" additionalProperties: false diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h index 35968ae982466..f5965dda3b905 100644 --- a/include/dt-bindings/clock/spacemit,k1-syscon.h +++ b/include/dt-bindings/clock/spacemit,k1-syscon.h @@ -78,6 +78,9 @@ #define CLK_APB 31 #define CLK_WDT_BUS 32 +/* MPMU resets */ +#define RESET_WDT 0 + /* APBC clocks */ #define CLK_UART0 0 #define CLK_UART2 1 @@ -180,6 +183,59 @@ #define CLK_TSEN_BUS 98 #define CLK_IPC_AP2AUD_BUS 99 +/* APBC resets */ +#define RESET_UART0 0 +#define RESET_UART2 1 +#define RESET_UART3 2 +#define RESET_UART4 3 +#define RESET_UART5 4 +#define RESET_UART6 5 +#define RESET_UART7 6 +#define RESET_UART8 7 +#define RESET_UART9 8 +#define RESET_GPIO 9 +#define RESET_PWM0 10 +#define RESET_PWM1 11 +#define RESET_PWM2 12 +#define RESET_PWM3 13 +#define RESET_PWM4 14 +#define RESET_PWM5 15 +#define RESET_PWM6 16 +#define RESET_PWM7 17 +#define RESET_PWM8 18 +#define RESET_PWM9 19 +#define RESET_PWM10 20 +#define RESET_PWM11 21 +#define RESET_PWM12 22 +#define RESET_PWM13 23 +#define RESET_PWM14 24 +#define RESET_PWM15 25 +#define RESET_PWM16 26 +#define RESET_PWM17 27 +#define RESET_PWM18 28 +#define RESET_PWM19 29 +#define RESET_SSP3 30 +#define RESET_RTC 31 +#define RESET_TWSI0 32 +#define RESET_TWSI1 33 +#define RESET_TWSI2 34 +#define RESET_TWSI4 35 +#define RESET_TWSI5 36 +#define RESET_TWSI6 37 +#define RESET_TWSI7 38 +#define RESET_TWSI8 39 +#define RESET_TIMERS1 40 +#define RESET_TIMERS2 41 +#define RESET_AIB 42 +#define RESET_ONEWIRE 43 +#define RESET_SSPA0 44 +#define RESET_SSPA1 45 +#define RESET_DRO 46 +#define RESET_IR 47 +#define RESET_TSEN 48 +#define RESET_IPC_AP2AUD 49 +#define RESET_CAN0 50 + /* APMU clocks */ #define CLK_CCI550 0 #define CLK_CPU_C0_HI 1 @@ -244,4 +300,76 @@ #define CLK_V2D 60 #define CLK_EMMC_BUS 61 +/* APMU resets */ +#define RESET_CCIC_4X 0 +#define RESET_CCIC1_PHY 1 +#define RESET_SDH_AXI 2 +#define RESET_SDH0 3 +#define RESET_SDH1 4 +#define RESET_SDH2 5 +#define RESET_USBP1_AXI 6 +#define RESET_USB_AXI 7 +#define RESET_USB3_0 8 +#define RESET_QSPI 9 +#define RESET_QSPI_BUS 10 +#define RESET_DMA 11 +#define RESET_AES 12 +#define RESET_VPU 13 +#define RESET_GPU 14 +#define RESET_EMMC 15 +#define RESET_EMMC_X 16 +#define RESET_AUDIO 17 +#define RESET_HDMI 18 +#define RESET_PCIE0 19 +#define RESET_PCIE1 20 +#define RESET_PCIE2 21 +#define RESET_EMAC0 22 +#define RESET_EMAC1 23 +#define RESET_JPG 24 +#define RESET_CCIC2PHY 25 +#define RESET_CCIC3PHY 26 +#define RESET_CSI 27 +#define RESET_ISP_CPP 28 +#define RESET_ISP_BUS 29 +#define RESET_ISP 30 +#define RESET_ISP_CI 31 +#define RESET_DPU_MCLK 32 +#define RESET_DPU_ESC 33 +#define RESET_DPU_HCLK 34 +#define RESET_DPU_SPIBUS 35 +#define RESET_DPU_SPI_HBUS 36 +#define RESET_V2D 37 +#define RESET_MIPI 38 +#define RESET_MC 39 + +/* RCPU resets */ +#define RESET_RCPU_SSP0 0 +#define RESET_RCPU_I2C0 1 +#define RESET_RCPU_UART1 2 +#define RESET_RCPU_IR 3 +#define RESET_RCPU_CAN 4 +#define RESET_RCPU_UART0 5 +#define RESET_RCPU_HDMI_AUDIO 6 + +/* RCPU2 resets */ +#define RESET_RCPU2_PWM0 0 +#define RESET_RCPU2_PWM1 1 +#define RESET_RCPU2_PWM2 2 +#define RESET_RCPU2_PWM3 3 +#define RESET_RCPU2_PWM4 4 +#define RESET_RCPU2_PWM5 5 +#define RESET_RCPU2_PWM6 6 +#define RESET_RCPU2_PWM7 7 +#define RESET_RCPU2_PWM8 8 +#define RESET_RCPU2_PWM9 9 + +/* APBC2 resets */ +#define RESET_APBC2_UART1 0 +#define RESET_APBC2_SSP2 1 +#define RESET_APBC2_TWSI3 2 +#define RESET_APBC2_RTC 3 +#define RESET_APBC2_TIMERS0 4 +#define RESET_APBC2_KPC 5 +#define RESET_APBC2_GPIO 6 + #endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */ From patchwork Fri Apr 18 14:53:54 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22EB6C369D0 for ; Fri, 18 Apr 2025 14:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=upCjtaMgViBdIDR4N9waia3oMvTzmvzh460KJWwp3Bo=; b=1qKZyxnlgGffil 7j1vrcRxuIAdCeySBM1V85O/NTvjKztVaFeTtqtgwFEFoJOX9HBmFT2YVVcQW7c5RIj2/uXah3fgA pgl7DLFJ0GS3y1xO2d7qofNI1TLurz/TRSN+dWw1U8iU7YdUXl7iGNBNvAd6zBVveKqOHPANThzBu ewOyCNIM9eGvfkWyyI3T6CvJzI3hK4N7nO1pIfKIIHQWsQmAewC/Tl8qfGiRAUBJKeGOwyhH6fp6H 0bxGpqGz1Kb39LiYGMn1322zCkfBb/9tT/42sDu/AnjFTHEAxof69pkLEsm8jf0xwlLxZTTaw2SUM //LJ0LOFaFNl69r3DNAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8D-0000000GWz8-07Do; Fri, 18 Apr 2025 14:55:53 +0000 Received: from mail-qt1-x832.google.com ([2607:f8b0:4864:20::832]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6Y-0000000GWPE-0dHJ for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:11 +0000 Received: by mail-qt1-x832.google.com with SMTP id d75a77b69052e-476a720e806so16510491cf.0 for ; Fri, 18 Apr 2025 07:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988049; x=1745592849; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DGLQrJG9/WVjMRDCZD5X9MgDJzulV+jWlnrfByD2cXU=; b=ckgX7QVwKMOOxByoNOtoRrNSelw65KIh/VJVT+bSeVdkLvTsWG5GoYEEX0FgGB6fQ1 1b8tcNZ31cHjhh1bkkDHFwUfan2pBC8lhL48YLhg+9oOeEYshWkZI10CF3N8WjLCznZv LDYzbhRUnP4hQE+HV/t92g6WazYwvwjNbrDJiBtPB0D0+AtKZwxuy4qFj6XRIfSU5cgf cA5riP90hiseCeH4fKgKjbiNscCMyCrjQuJIozDuoVvzQDLRVCHgvdp/mRR/uqfCTsyy tUQNDmEP0Ysh7IDT/3NsvcBjtvx/pvT46hJothxG2YMUAmsfZ3tZdEkVKcXxMCeGnWQf Li0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988049; x=1745592849; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DGLQrJG9/WVjMRDCZD5X9MgDJzulV+jWlnrfByD2cXU=; b=KybzExJQVIk2CyHcgfW5LnejmDzO4EqIOzZTlvA7yAqTCMIrbpFS6dVYaRyBl+EG7k nMWQI3IAYwd2WdBt4nV3qRfSfDj1yJ/PGgfz7D6m+QjeBDDs6x9McrO5MFw2F2SMRXy3 aR0wVHhuAu/aa/qcVJUp9qbR7/IXZDqR7unS5qmKxBEBkGGPOcjltfAnbpcthIkpQwmp ryBBkAIS3lU9R2T07OLWmz16VeB61oO0EUrbeBvfU1cYN7op1A2r7o90ExiaQvIS5Oj3 FxTes41M5wIWasbgGJpBRDK8QRN7an79e9BOa85dKj3A21lQTI9WLfivKzkVPGVBYe92 0ThQ== X-Forwarded-Encrypted: i=1; AJvYcCV0ObBiwtRuvFBvMkjwXcZvMP/Bhv4ynC3p00dmfSl9pSbYwZ2D0SObfmkBbTw2LhZS5ObQCsXSDmlfGg==@lists.infradead.org X-Gm-Message-State: AOJu0Yyl3LNEqUWNv1Aq2F5mKBEM0GDJ+Ggqi1VkD75Y16n3Xd+2Uxcq q6yPOkH/GOpyL7XOxoNRiNppDDUxjVm8qEjxgPXxY8lJ2vgKp/03wD2eGaED9GU= X-Gm-Gg: ASbGnctnckV26EMdUJ0stu6eQDh5Iq1CPE5eWHRVb2L9Ab3v7Pz0i2kFM86yzMQX41Z 6gqhv/uYrJhcK099RYqru31cr3AyIF1ybcCkp3/WaMSxQBRaNERpYJIoOAi/X45PhRvKlxxyQBA sbTx3p1O+7yGJvJUFmngcHOJe8aDq7JVBPpPganm9h2F04iCBX6pEmdAtu0oMtUDbbrLvEfpXiL 3QLz37bYfYtBQuk3RKx4mOEiezaAYdaV34HDPMinukyZWJV9GuBWn9NTBnbKzGBVlDkl5uXIDuw R+7lHLxdvNvtGtSMMvXuSqBbvZnQ828yTMhCcdKhnolKJX4T532SJAqK/NsZnPz9WQjE7KTH8rO ES7Atac7xWaSJXA== X-Google-Smtp-Source: AGHT+IHEqzlEJZsM9ibzpxY3pVimq3gvrY9lGtxVp45evTuL1ehJDJBIbt283Y62JHB4YPt3Xe3sXw== X-Received: by 2002:a05:622a:1987:b0:472:133f:93ae with SMTP id d75a77b69052e-47aec4cf703mr39891641cf.48.1744988049055; Fri, 18 Apr 2025 07:54:09 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:08 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/7] clk: spacemit: rename spacemit_ccu_data fields Date: Fri, 18 Apr 2025 09:53:54 -0500 Message-ID: <20250418145401.2603648-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075410_192592_50985482 X-CRM114-Status: GOOD ( 11.96 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add "clk_" to the names of the fields in the spacemit_ccu_data structure type. This prepares it for the addition of two similar fields dedicated to resets. Signed-off-by: Alex Elder Reviewed-by: Haylen Chu --- drivers/clk/spacemit/ccu-k1.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index cdde37a052353..a7712d1681a11 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,8 +130,8 @@ #define APMU_EMAC1_CLK_RES_CTRL 0x3ec struct spacemit_ccu_data { - struct clk_hw **hws; - size_t num; + struct clk_hw **clk_hws; + size_t clk_num; }; /* APBS clocks start, APBS region contains and only contains all PLL clocks */ @@ -819,8 +819,8 @@ static struct clk_hw *k1_ccu_pll_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_pll_data = { - .hws = k1_ccu_pll_hws, - .num = ARRAY_SIZE(k1_ccu_pll_hws), + .clk_hws = k1_ccu_pll_hws, + .clk_num = ARRAY_SIZE(k1_ccu_pll_hws), }; static struct clk_hw *k1_ccu_mpmu_hws[] = { @@ -860,8 +860,8 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_mpmu_data = { - .hws = k1_ccu_mpmu_hws, - .num = ARRAY_SIZE(k1_ccu_mpmu_hws), + .clk_hws = k1_ccu_mpmu_hws, + .clk_num = ARRAY_SIZE(k1_ccu_mpmu_hws), }; static struct clk_hw *k1_ccu_apbc_hws[] = { @@ -968,8 +968,8 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_apbc_data = { - .hws = k1_ccu_apbc_hws, - .num = ARRAY_SIZE(k1_ccu_apbc_hws), + .clk_hws = k1_ccu_apbc_hws, + .clk_num = ARRAY_SIZE(k1_ccu_apbc_hws), }; static struct clk_hw *k1_ccu_apmu_hws[] = { @@ -1038,8 +1038,8 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { }; static const struct spacemit_ccu_data k1_ccu_apmu_data = { - .hws = k1_ccu_apmu_hws, - .num = ARRAY_SIZE(k1_ccu_apmu_hws), + .clk_hws = k1_ccu_apmu_hws, + .clk_num = ARRAY_SIZE(k1_ccu_apmu_hws), }; static int spacemit_ccu_register(struct device *dev, @@ -1050,13 +1050,13 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; int i, ret; - clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->num), + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->clk_num), GFP_KERNEL); if (!clk_data) return -ENOMEM; - for (i = 0; i < data->num; i++) { - struct clk_hw *hw = data->hws[i]; + for (i = 0; i < data->clk_num; i++) { + struct clk_hw *hw = data->clk_hws[i]; struct ccu_common *common; const char *name; @@ -1081,7 +1081,7 @@ static int spacemit_ccu_register(struct device *dev, clk_data->hws[i] = hw; } - clk_data->num = data->num; + clk_data->num = data->clk_num; ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); if (ret) From patchwork Fri Apr 18 14:53:55 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18F97C369CF for ; Fri, 18 Apr 2025 14:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3SJX0hjxD/anW3aaTkLosHQAFPjzTOn9mxhDZATVQ18=; b=BxC4d3LsjHnr/+ iFSZ9kPmNcbP6U9Mmu+9iVwzAWQCod1lZ2J4rnWPFzYzeM77gr3xFmialmd0PMIvyqzKv86mS1PPB P630SI0w+ZnUTL4Lzqakbk3Q2xpdx1dA2pc3Q54R9JMXmoRN7cW9VOtFrQbVtZIWYjf5lPRZMuTc5 DqWVu1KCOnX/tXB+yZEhog0DGB+I82El5Pk4QBr52AHsVc0XxTO2tose9sgzeUV7YvTWFAwn9bVGb V2YEkU1EdiNnxpY/iSuNka+SJN0Kvk5C4+5PzAjBh1LueFuW0Bq5qx/+e+mfeIM6HNzGXremU2rX8 sKZLeG8JXuLd+qrL4Fmw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8D-0000000GX06-3MMz; Fri, 18 Apr 2025 14:55:53 +0000 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6Z-0000000GWQ6-22V9 for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:12 +0000 Received: by mail-qt1-x834.google.com with SMTP id d75a77b69052e-4768f90bf36so17979841cf.0 for ; Fri, 18 Apr 2025 07:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988050; x=1745592850; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yaw5lt81qT1qo0WLXCCCbUzvwZO95HiGQh1l0h3tFD4=; b=IQIIoC00NROiSt75N3VN9ciRtbCwdMWoLGSpIX6D/Aam7H0ucvbfRvGWIx74zH4EDV pIGS6ZLVtH9OW/51PHmXqdMdFujezAO05oK57lV+qlIYICo/S0gLv+8NWRqORdQiIPYs TupByMlK5JzieJyB16exC0vT/WbDxDZNKikRLeuZnciUSaY0GLvi3uL6w+eklC0dMvCT bU0fYzF3yitlzHFzNzB557pjtoRpfQ7oPQDF/OWhcifIqCz2/gU5hJR7b8CGDS8ccq/F 8KXcv0u/oiZqfHSguuvB6C46JEcf5InMjR9pmn83azgMtVfoiNDgZN51++reOpsadcmR Y5ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988050; x=1745592850; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yaw5lt81qT1qo0WLXCCCbUzvwZO95HiGQh1l0h3tFD4=; b=YgBFgrC3niu0u7n/KUZVVLS+JLijZ8m6L3b+yaEYTnDRwRWiNhv3mvEZrBB5Uuuulw ADR6bjK7dWnZNZPNExABXvS0w+mcuA57PFS7+Ezjx+2cUQ66BUwonr3IHIO6o/ytCMBh /xJpXdQ4PXuQ62L1FDfZYKKZ0F+ow3cjtyXjvb+Hc69fJJpmhLsTIS7H2evtmKtb26lr 08HGiah/kS2MX6E19A4gzj3QJlNm5lPQsvBG0d1ZYYPri4Ua9AQANxKOrf7io/nyP1Jf sbaKy0G1qrjPuBTxSCrwxaETclgZrOS+BJswe6EngwmRYElEgmHB66/oOYZgqSHNyqhB 9eWA== X-Forwarded-Encrypted: i=1; AJvYcCUvfDfPsi+26yq5ldMEhkOvhBhQREPO9fdMrlcvg7uEhHjaXds6daQ7azSEoMn1eCjX+Q2YYN2+e3fcYQ==@lists.infradead.org X-Gm-Message-State: AOJu0YxB65cl6XfIeBMZ84UxDzm3lSWhPHwa3My2+Cql3D+W4y7J2Ean twbfpufdqOWDtmiPo/1LQlV17YblcaqVTf9FJFWz0C6Kb7cDJJM2OHsIm5I2dDs= X-Gm-Gg: ASbGncuuBeJLF6jokt5fdyNAh5ScBy5w9n0wXiV2PYrw8mJPFiOMcU7A6wPBZ18pr1g O5+oMYfqjtLJgcqbayC4kTT8qdJ7DNUja0AUnX+P4rVwL/FS/G0fYxdRHac09YOPbgLRpwg7nJK RLzvmv/88OT+bBAmV7Y7xjMphAje1nmxoCJUdAtgi3dNq6z59IuX1UlatlECLmruBxdvQUzEmKS Cmm+dDsnG+g07vrEf6tEys3rdosywb8whzMjRZypk8I7Yxlj/8pSJ+iJcKvb4vi8bqfM+2eVWLb tKMlGrHaP7aBdocOGd4zR1D6wJeFWtcNkqaN3HTtgLoiKbdVQNUrNtE2JjWg2FH2O33jqZBkV5E VbO+5sAhmUAcYFg== X-Google-Smtp-Source: AGHT+IFvYy7PkzuSyv6/DahcPqSuURSVxow9I8GZ9PMmiSUagXcMHnpfEu6YrBdLJKJ9ltUJ181r5g== X-Received: by 2002:ac8:57cf:0:b0:47a:e70c:e1ad with SMTP id d75a77b69052e-47aec399e28mr54297341cf.1.1744988050449; Fri, 18 Apr 2025 07:54:10 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:10 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/7] clk: spacemit: add reset controller support Date: Fri, 18 Apr 2025 09:53:55 -0500 Message-ID: <20250418145401.2603648-4-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075411_527764_CF36CCEC X-CRM114-Status: GOOD ( 22.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define ccu_reset_data as a structure that contains the constant register offset and bitmasks used to assert and deassert a reset control on a SpacemiT K1 CCU. Add a pointer to an array of those structures to the spacemit_ccu_data structure, along with a field indicating how many elements are in that array. Resets will be optional, and if none are defined the reset array pointer will be null. Define a new ccu_reset_controller structure, which (for a CCU with resets) contains a pointer to the constant reset data, the regmap to be used for the controller, and an embedded a reset controller structure. Each reset control is asserted or deasserted by updating bits in a register. The bits used are defined by an assert mask and a deassert mask. In some cases, one (non-zero) mask asserts reset and a different (non-zero) mask deasserts it. Otherwise one mask is nonzero, and the other is zero. Either way, the bits in both masks are cleared, then either the assert mask or the deassert mask is set in a register to affect the state of a reset control. Signed-off-by: Alex Elder Reviewed-by: Philipp Zabel --- drivers/clk/spacemit/ccu-k1.c | 86 +++++++++++++++++++++++++++++++++-- 1 file changed, 83 insertions(+), 3 deletions(-) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index a7712d1681a11..9152cce00ce90 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_pll.h" @@ -129,9 +130,23 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec +struct ccu_reset_data { + u32 offset; + u32 assert_mask; + u32 deassert_mask; +}; + struct spacemit_ccu_data { - struct clk_hw **clk_hws; + struct clk_hw **clk_hws; /* array */ size_t clk_num; + const struct ccu_reset_data *reset_data; /* array */ + size_t reset_num; +}; + +struct ccu_reset_controller { + struct regmap *regmap; + const struct spacemit_ccu_data *data; + struct reset_controller_dev rcdev; }; /* APBS clocks start, APBS region contains and only contains all PLL clocks */ @@ -1042,6 +1057,39 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data = { .clk_num = ARRAY_SIZE(k1_ccu_apmu_hws), }; +static int spacemit_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct ccu_reset_controller *controller; + const struct ccu_reset_data *data; + u32 mask; + u32 val; + + controller = container_of(rcdev, struct ccu_reset_controller, rcdev); + data = &controller->data->reset_data[id]; + mask = data->assert_mask | data->deassert_mask; + val = assert ? data->assert_mask : data->deassert_mask; + + return regmap_update_bits(controller->regmap, data->offset, mask, val); +} + +static int spacemit_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, true); +} + +static int spacemit_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return spacemit_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops spacemit_reset_control_ops = { + .assert = spacemit_reset_assert, + .deassert = spacemit_reset_deassert, +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap, @@ -1090,9 +1138,37 @@ static int spacemit_ccu_register(struct device *dev, return ret; } +static int spacemit_reset_controller_register(struct device *dev, + struct regmap *regmap, + const struct spacemit_ccu_data *data) +{ + struct ccu_reset_controller *controller; + struct reset_controller_dev *rcdev; + + /* Resets are optional */ + if (!data->reset_data) + return 0; + + controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + + controller->regmap = regmap; + controller->data = data; + + rcdev = &controller->rcdev; + rcdev->ops = &spacemit_reset_control_ops; + rcdev->owner = THIS_MODULE; + rcdev->of_node = dev->of_node; + rcdev->nr_resets = data->reset_num; + + return devm_reset_controller_register(dev, rcdev); +} + static int k1_ccu_probe(struct platform_device *pdev) { struct regmap *base_regmap, *lock_regmap = NULL; + const struct spacemit_ccu_data *data; struct device *dev = &pdev->dev; int ret; @@ -1121,11 +1197,15 @@ static int k1_ccu_probe(struct platform_device *pdev) "failed to get lock regmap\n"); } - ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, - of_device_get_match_data(dev)); + data = of_device_get_match_data(dev); + ret = spacemit_ccu_register(dev, base_regmap, lock_regmap, data); if (ret) return dev_err_probe(dev, ret, "failed to register clocks\n"); + ret = spacemit_reset_controller_register(dev, base_regmap, data); + if (ret) + return dev_err_probe(dev, ret, "failed to register reset controller\n"); + return 0; } From patchwork Fri Apr 18 14:53:56 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3477C369D2 for ; Fri, 18 Apr 2025 14:55:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=2lEgHU5RNU0Hfxzbl0ZVlsN1Py92ZVWNeYJnCNkt+t4=; b=aSokBNW9yubYT2 kKRxSYsZzNFFN/pDzaiT0cG/TxfusLcCsLEqCRSrYKaqNbssrhwcvvH4DMGAapZ/R0sboMkOstIf5 czClEXNLjYC04HJzbE/vzepV7CDTgoGKUddqoZDkoV0yWgYCH1Xc8HMvHkpS5xFHQQwwcGknXu+W9 3aPELsCO/S6CUsQfvdLxHQhYmM3rfYOH85J7LNZkYsXbIe3eMeEDaYwGLzASVr7qzb9l4yOGJqqnz jW8xcwd9b9n+OwSIn/EIvJOLlC8haKcvBE5r5YXuQ9KTMwy/PWOKO3FBsvaxFoUzKLcqf9FoXab4v Ikxxzja/SivBxmHNQeJQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8E-0000000GX0y-2lTf; Fri, 18 Apr 2025 14:55:54 +0000 Received: from mail-qt1-x834.google.com ([2607:f8b0:4864:20::834]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6a-0000000GWQe-2yUH for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:13 +0000 Received: by mail-qt1-x834.google.com with SMTP id d75a77b69052e-476b89782c3so21804591cf.1 for ; Fri, 18 Apr 2025 07:54:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988052; x=1745592852; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J/LZIDJ92Tz7awYomEWjt5hmUFJrb1ca7bM/MgIo4+s=; b=KLyzgm8eNFkhuHCtKb6GfcyDuM84HQGKKIxQ1s41Ha1K/JTcirjivQT6O1pwrZUrJ1 hGFRI3yqbjAsyWfZeOfqEHlUdHzxV4s+wu6JQYeiEw/ajqhi8dbZ41d2HxnkUm7KV/7O O0rM3kKzLA7xZ+veqH24qPwfLkGCFv7gzIPiZDyj+UiT2Ym4MSlh5XKA676Gd9inpb/E +pUdaOxesq7mb1JNLKX0C/y3teBDyc8UoxB0n65IaWLH7UTOggZwYm77Vc/VncNjgDne RtCDw/GvxlJvvptUA2K3MERJxPf9b0SMPM0+NYNZqJSFz2TMa/NlX4qt6bB1tMv+vcCx Rj2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988052; x=1745592852; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J/LZIDJ92Tz7awYomEWjt5hmUFJrb1ca7bM/MgIo4+s=; b=AZPX29nMfX5RzUKaPCMlofZkDvJe+DUCoOwLThd8b9l1l/8HrmLsxY7NPR/rabxFjr PmKrRRDAkrVShU/FpsaX4vOqLis7fas34rmj/LexlQOwrFLwXgktpVmh/Oil6xgqZZp6 Hk/ND8VkmO9BXXGTkUXo+DuY/NMUec4lAmhJes1XumnuNhOkusWDqdGCXxhnwQljstl1 JKk6/uI6h6PIfv13lZoPZhNPnjeJc12xmmDDfadY91wTEzvUk9ZEYzm8bO1ip5AV5x8w 1YHn6eL30/ZcEnqyGR6SaByPqlvWapaPQjyIuWuQodYhrPoEU4bAIKJlwaNqqBD8Xluk NpSw== X-Forwarded-Encrypted: i=1; AJvYcCVXtEtNhudxvhyta+cDokVyJprAlyWm6olgXkHMdN/uWkJzyHqfvHjQ2gmKY1erpC3sH6GJxH6N9l7FVQ==@lists.infradead.org X-Gm-Message-State: AOJu0YwX0ZkpCpIflG8Ss89Lf09kAH3DvkBITDpuOpyvb/yVgyMtd+/D cUIGplUB2vnCXOEyZs5KL5TheK5CcWvW9TNXCl7/F9gJnfup5eALuBgwXJEN7ls= X-Gm-Gg: ASbGncvd5knkMM1aQxSezeEiNcW2H5s1t3LtjdVmXLvAUxgegvcA+pWmDRegZa+6p+h Jjp42K6GMTXhvWv3Ns2h8Q2y2qHVyzHItq5ej0RdQi2DDzy6k4hgjTTv7ZzEUxxceOZ49/wBLsK bASH3ARkXf1vK2v9qwfR68ZmCG+CTmVkZZPATvBqMsdbnzRN6+HFw0xQvSsdXs6DHVkYUKkQtWu fscp4xRHfS0ehQqT5zB05yl0W4clOi7peo3fZp/G1XyV2a4aA1ezHEBuxlhlHftgDp5zABkJgLQ Vud1ooZjhN6l8X3HLXsy/wlpAO6WIGNrfsPzXxhyi0YYr2GyLFFpCTjWSvGGeRkrwYhq6/KM8YS Hkfwa7RixMWUs7Q== X-Google-Smtp-Source: AGHT+IGPcEqgJbzZ93z5saI9RMTu0Jw8MVo7LvC1jCgugrgygiGJsDA3Rj1DL7+viV5SSM/phg0jGQ== X-Received: by 2002:a05:622a:1a12:b0:475:16db:b911 with SMTP id d75a77b69052e-47aec4d072cmr54371041cf.52.1744988051878; Fri, 18 Apr 2025 07:54:11 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:11 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 4/7] clk: spacemit: define existing syscon resets Date: Fri, 18 Apr 2025 09:53:56 -0500 Message-ID: <20250418145401.2603648-5-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075412_758254_E812B9E2 X-CRM114-Status: GOOD ( 11.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define reset controls associated with the MPMU, APBC, and APMU SpacemiT K1 CCUs. These already have clocks associated with them. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 120 ++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index 9152cce00ce90..ad5f41695f8db 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -136,6 +136,13 @@ struct ccu_reset_data { u32 deassert_mask; }; +#define RESET_DATA(_offset, _assert_mask, _deassert_mask) \ + { \ + .offset = (_offset), \ + .assert_mask = (_assert_mask), \ + .deassert_mask = (_deassert_mask), \ + } + struct spacemit_ccu_data { struct clk_hw **clk_hws; /* array */ size_t clk_num; @@ -836,6 +843,7 @@ static struct clk_hw *k1_ccu_pll_hws[] = { static const struct spacemit_ccu_data k1_ccu_pll_data = { .clk_hws = k1_ccu_pll_hws, .clk_num = ARRAY_SIZE(k1_ccu_pll_hws), + /* No resets in the PLL CCU */ }; static struct clk_hw *k1_ccu_mpmu_hws[] = { @@ -874,9 +882,15 @@ static struct clk_hw *k1_ccu_mpmu_hws[] = { [CLK_WDT_BUS] = &wdt_bus_clk.common.hw, }; +static const struct ccu_reset_data mpmu_reset_data[] = { + [RESET_WDT] = RESET_DATA(MPMU_WDTPCR, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_mpmu_data = { .clk_hws = k1_ccu_mpmu_hws, .clk_num = ARRAY_SIZE(k1_ccu_mpmu_hws), + .reset_data = mpmu_reset_data, + .reset_num = ARRAY_SIZE(mpmu_reset_data), }; static struct clk_hw *k1_ccu_apbc_hws[] = { @@ -982,9 +996,65 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { [CLK_IPC_AP2AUD_BUS] = &ipc_ap2aud_bus_clk.common.hw, }; +static const struct ccu_reset_data apbc_reset_data[] = { + [RESET_UART0] = RESET_DATA(APBC_UART1_CLK_RST, BIT(2), 0), + [RESET_UART2] = RESET_DATA(APBC_UART2_CLK_RST, BIT(2), 0), + [RESET_GPIO] = RESET_DATA(APBC_GPIO_CLK_RST, BIT(2), 0), + [RESET_PWM0] = RESET_DATA(APBC_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM1] = RESET_DATA(APBC_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM2] = RESET_DATA(APBC_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM3] = RESET_DATA(APBC_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM4] = RESET_DATA(APBC_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM5] = RESET_DATA(APBC_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM6] = RESET_DATA(APBC_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM7] = RESET_DATA(APBC_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM8] = RESET_DATA(APBC_PWM8_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM9] = RESET_DATA(APBC_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM10] = RESET_DATA(APBC_PWM10_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM11] = RESET_DATA(APBC_PWM11_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM12] = RESET_DATA(APBC_PWM12_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM13] = RESET_DATA(APBC_PWM13_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM14] = RESET_DATA(APBC_PWM14_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM15] = RESET_DATA(APBC_PWM15_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM16] = RESET_DATA(APBC_PWM16_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM17] = RESET_DATA(APBC_PWM17_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM18] = RESET_DATA(APBC_PWM18_CLK_RST, BIT(2), BIT(0)), + [RESET_PWM19] = RESET_DATA(APBC_PWM19_CLK_RST, BIT(2), BIT(0)), + [RESET_SSP3] = RESET_DATA(APBC_SSP3_CLK_RST, BIT(2), 0), + [RESET_UART3] = RESET_DATA(APBC_UART3_CLK_RST, BIT(2), 0), + [RESET_RTC] = RESET_DATA(APBC_RTC_CLK_RST, BIT(2), 0), + [RESET_TWSI0] = RESET_DATA(APBC_TWSI0_CLK_RST, BIT(2), 0), + [RESET_TIMERS1] = RESET_DATA(APBC_TIMERS1_CLK_RST, BIT(2), 0), + [RESET_AIB] = RESET_DATA(APBC_AIB_CLK_RST, BIT(2), 0), + [RESET_TIMERS2] = RESET_DATA(APBC_TIMERS2_CLK_RST, BIT(2), 0), + [RESET_ONEWIRE] = RESET_DATA(APBC_ONEWIRE_CLK_RST, BIT(2), 0), + [RESET_SSPA0] = RESET_DATA(APBC_SSPA0_CLK_RST, BIT(2), 0), + [RESET_SSPA1] = RESET_DATA(APBC_SSPA1_CLK_RST, BIT(2), 0), + [RESET_DRO] = RESET_DATA(APBC_DRO_CLK_RST, BIT(2), 0), + [RESET_IR] = RESET_DATA(APBC_IR_CLK_RST, BIT(2), 0), + [RESET_TWSI1] = RESET_DATA(APBC_TWSI1_CLK_RST, BIT(2), 0), + [RESET_TSEN] = RESET_DATA(APBC_TSEN_CLK_RST, BIT(2), 0), + [RESET_TWSI2] = RESET_DATA(APBC_TWSI2_CLK_RST, BIT(2), 0), + [RESET_TWSI4] = RESET_DATA(APBC_TWSI4_CLK_RST, BIT(2), 0), + [RESET_TWSI5] = RESET_DATA(APBC_TWSI5_CLK_RST, BIT(2), 0), + [RESET_TWSI6] = RESET_DATA(APBC_TWSI6_CLK_RST, BIT(2), 0), + [RESET_TWSI7] = RESET_DATA(APBC_TWSI7_CLK_RST, BIT(2), 0), + [RESET_TWSI8] = RESET_DATA(APBC_TWSI8_CLK_RST, BIT(2), 0), + [RESET_IPC_AP2AUD] = RESET_DATA(APBC_IPC_AP2AUD_CLK_RST, BIT(2), 0), + [RESET_UART4] = RESET_DATA(APBC_UART4_CLK_RST, BIT(2), 0), + [RESET_UART5] = RESET_DATA(APBC_UART5_CLK_RST, BIT(2), 0), + [RESET_UART6] = RESET_DATA(APBC_UART6_CLK_RST, BIT(2), 0), + [RESET_UART7] = RESET_DATA(APBC_UART7_CLK_RST, BIT(2), 0), + [RESET_UART8] = RESET_DATA(APBC_UART8_CLK_RST, BIT(2), 0), + [RESET_UART9] = RESET_DATA(APBC_UART9_CLK_RST, BIT(2), 0), + [RESET_CAN0] = RESET_DATA(APBC_CAN0_CLK_RST, BIT(2), 0), +}; + static const struct spacemit_ccu_data k1_ccu_apbc_data = { .clk_hws = k1_ccu_apbc_hws, .clk_num = ARRAY_SIZE(k1_ccu_apbc_hws), + .reset_data = apbc_reset_data, + .reset_num = ARRAY_SIZE(apbc_reset_data), }; static struct clk_hw *k1_ccu_apmu_hws[] = { @@ -1052,9 +1122,59 @@ static struct clk_hw *k1_ccu_apmu_hws[] = { [CLK_EMMC_BUS] = &emmc_bus_clk.common.hw, }; +static const struct ccu_reset_data apmu_reset_data[] = { + [RESET_CCIC_4X] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(1)), + [RESET_CCIC1_PHY] = RESET_DATA(APMU_CCIC_CLK_RES_CTRL, 0, BIT(2)), + [RESET_SDH_AXI] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(0)), + [RESET_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_USBP1_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(4)), + [RESET_USB_AXI] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)), + [RESET_USB3_0] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, + BIT(11) | BIT(10) | BIT(9)), + [RESET_QSPI] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(1)), + [RESET_QSPI_BUS] = RESET_DATA(APMU_QSPI_CLK_RES_CTRL, 0, BIT(0)), + [RESET_DMA] = RESET_DATA(APMU_DMA_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AES] = RESET_DATA(APMU_AES_CLK_RES_CTRL, 0, BIT(4)), + [RESET_VPU] = RESET_DATA(APMU_VPU_CLK_RES_CTRL, 0, BIT(0)), + [RESET_GPU] = RESET_DATA(APMU_GPU_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMMC_X] = RESET_DATA(APMU_PMUA_EM_CLK_RES_CTRL, 0, BIT(0)), + [RESET_AUDIO] = RESET_DATA(APMU_AUDIO_CLK_RES_CTRL, 0, + BIT(3) | BIT(2) | BIT(0)), + [RESET_HDMI] = RESET_DATA(APMU_HDMI_CLK_RES_CTRL, 0, BIT(9)), + [RESET_PCIE0] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_0, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE1] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_1, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_PCIE2] = RESET_DATA(APMU_PCIE_CLK_RES_CTRL_2, BIT(8), + BIT(5) | BIT(4) | BIT(3)), + [RESET_EMAC0] = RESET_DATA(APMU_EMAC0_CLK_RES_CTRL, 0, BIT(1)), + [RESET_EMAC1] = RESET_DATA(APMU_EMAC1_CLK_RES_CTRL, 0, BIT(1)), + [RESET_JPG] = RESET_DATA(APMU_JPG_CLK_RES_CTRL, 0, BIT(0)), + [RESET_CCIC2PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(2)), + [RESET_CCIC3PHY] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(29)), + [RESET_CSI] = RESET_DATA(APMU_CSI_CCIC2_CLK_RES_CTRL, 0, BIT(1)), + [RESET_ISP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(0)), + [RESET_ISP_CPP] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(27)), + [RESET_ISP_BUS] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(3)), + [RESET_ISP_CI] = RESET_DATA(APMU_ISP_CLK_RES_CTRL, 0, BIT(16)), + [RESET_DPU_MCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL2, 0, BIT(9)), + [RESET_DPU_ESC] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(3)), + [RESET_DPU_HCLK] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(4)), + [RESET_DPU_SPIBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(4)), + [RESET_DPU_SPI_HBUS] = RESET_DATA(APMU_LCD_SPI_CLK_RES_CTRL, 0, BIT(2)), + [RESET_V2D] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(27)), + [RESET_MIPI] = RESET_DATA(APMU_LCD_CLK_RES_CTRL1, 0, BIT(15)), + [RESET_MC] = RESET_DATA(APMU_PMUA_MC_CTRL, 0, BIT(0)), +}; + static const struct spacemit_ccu_data k1_ccu_apmu_data = { .clk_hws = k1_ccu_apmu_hws, .clk_num = ARRAY_SIZE(k1_ccu_apmu_hws), + .reset_data = apmu_reset_data, + .reset_num = ARRAY_SIZE(apmu_reset_data), }; static int spacemit_reset_update(struct reset_controller_dev *rcdev, From patchwork Fri Apr 18 14:53:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5578C369D1 for ; Fri, 18 Apr 2025 14:55:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=h4LZQf4FiY3eW42LZiWFylGRc4yDzWgryW5L4NRV/FM=; b=Q8924VVjr5o+Kn QkYAcWMGO/0o/Jl0HFhz5NM535zeYnmItPkY8oDL7O3M1ZJAIj5zKwMy3Gf/VhPq1mNfIuTr/ZjZJ nHhN8LoyNWx+n4F40IAjKWjBR/GrC/xZ/7pvzXqmww/qfJ7TF/1PKUhx3Ltq3dvg9LAGT8FsltR/n ySCwafZiPXsx4gRKGE1lLY1+WjzryHZ7l5Ml4YToczv5Ls7GsaElDnOW4KPNs4mZyZq64ZxqGA3c6 CvLbtOAh91fHwnAa5mQu27QbpIb+EGfnkvJsB6YHLbBUEoNtwhRspngZlKxJ9ikK0W0CAlO9pcRok Aiw9GLPFi0CMasxq/+4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8F-0000000GX1m-1zho; Fri, 18 Apr 2025 14:55:55 +0000 Received: from mail-qt1-x82e.google.com ([2607:f8b0:4864:20::82e]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6c-0000000GWRA-1aSV for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:15 +0000 Received: by mail-qt1-x82e.google.com with SMTP id d75a77b69052e-476a1acf61eso18432291cf.1 for ; Fri, 18 Apr 2025 07:54:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988053; x=1745592853; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q0cRJZr/QLbnC//i+6RCLRRi6tJxaoAhZJAaalWswhg=; b=CFRr02JEUvA5+ENc1LzndbnfvM2EXVcoLiFceqR1Dc96U3idV1OCB+BH1p0z9So449 mGiwokzmxqUlv4UUSVoMxWfz9pL1j0iV15g4CCWZKji+8CEICIaJKjC57ww8gB9Iu8lP DdENCJjuIS9W2BxXztTiVMoi30jXlpQTp4zVip6KWQLzA6+mlzkgUBYjL1dcVZRT7l27 LGY+0/oJYKjzCya1ibhT5VxXIYMOJC4SMbF8UqNiMQHI0nZqiG47M9RXGx5heJega8A5 EyYj79VEgX7549VpmEQHHnpmJcsswgi9f3RUf7KRuI4OqNm/MHyDJw9APYmB2WTyoObs FAig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988053; x=1745592853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q0cRJZr/QLbnC//i+6RCLRRi6tJxaoAhZJAaalWswhg=; b=XkEYSCN7CYjZdE2p8QvbRx/PenDPMTpJlB8cUDUJuuF0GZiz74w7AKKIp+KG8iBFmV YCoJCaqG3ypi6gEZzTMBFR84RZYf9a020GqmMyi00r8yQ/VY8WsVIYky+hOfufjxvDED ww41bQnoIDqInVatbiLqDVkitk4g8zAWiqsFpjvBEiS4Iy86tUjp5yn7ggqWG5oi+5Iv pbh4qHp80TSNkUsYK5eecEaFJhVfLXub/UtHPcz5yjKyolBAj9RDVmnQoM6ju69phb14 wSefXiZUenMK3qGxRTuUDYk/OqE4lXUpWFrkZbH0P9L0pB8sD3jQyN5Xu1a94y2WkC5q 9E5A== X-Forwarded-Encrypted: i=1; AJvYcCXjpm70utTGnaURMtlRetercx+XPgbBqWpECoUN2gshzfUJMAJbe/XSR8S+Jcb/ZX9kj5VvLWKkoMoWwQ==@lists.infradead.org X-Gm-Message-State: AOJu0YzKVBpyCbtuJ443mTGIjGecGnpxUiYcKtz+MpYc5GD5jaRLvMhb tjoltK8GqyZRGtUHrMDXSqcYtqyT5gvkWXk02CuQozv1dRZn7rQeJH3nvX07BI8= X-Gm-Gg: ASbGnct2R02QvGVsH18rMHghDdU69pX55cZdsn3QfcA+5q4wtEb1fTvTXhRj363IP71 hl/oKAi4byHGPGpiRzbSbN2tYSoyoTcUbyuefxZiQCy3oGp1nCK5pURK9HS62By4A7B/yXqvtoO 4j0gQis9EXb5Ga8mIgNM2Jax6v1uESEVyInF0cDFCfX89nGDM8eSDJjgJEsOsx4aCNpyKgquOE6 zK1Vv5CZuQWwMhaW6vb521+JDVf4nK74qKtrHz3CGG4T7zihORMMW1hEatU4PG5Wp5xLePvDKkl oFGPaVgzYHlDjgCtLCMGvRaQrXug/vpfRphFuxKihN9MeouWABFXefJFa1tY9g7+EMI3HgINSfb RkazFVTjTV36KBg== X-Google-Smtp-Source: AGHT+IFZ0pFYNx2snWn3YpkMMZYSR9nF5fcb5GLtk7fhZ50PwkaLo1+AOy6UlMO++lE568O7vJ+T8g== X-Received: by 2002:ac8:5f89:0:b0:477:4224:9607 with SMTP id d75a77b69052e-47aec3a6358mr42212621cf.12.1744988053257; Fri, 18 Apr 2025 07:54:13 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:12 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 5/7] clk: spacemit: make clocks optional Date: Fri, 18 Apr 2025 09:53:57 -0500 Message-ID: <20250418145401.2603648-6-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075414_420908_9C083EA1 X-CRM114-Status: GOOD ( 11.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org There are some syscon devices that support both clocks and resets, but for now only their reset functionality is required. Make defining clocks optional for a SpacemiT CCU, though at least one clock or at least one reset controller must be defined. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index ad5f41695f8db..dfc8aa60d4345 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -1218,6 +1218,10 @@ static int spacemit_ccu_register(struct device *dev, struct clk_hw_onecell_data *clk_data; int i, ret; + /* Clocks are optional */ + if (!data->clk_hws) + return 0; + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, data->clk_num), GFP_KERNEL); if (!clk_data) @@ -1329,6 +1333,7 @@ static int k1_ccu_probe(struct platform_device *pdev) return 0; } +/* Match data is required; its clk_hws or reset_data field must be non-null */ static const struct of_device_id of_k1_ccu_match[] = { { .compatible = "spacemit,k1-pll", From patchwork Fri Apr 18 14:53:58 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D496C369D3 for ; Fri, 18 Apr 2025 14:56:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Mc7bUy6oXcrHcYfzgtM9FNbI7LNCdRY+mC2AwcVSTBo=; b=uJQSU5U97Qj/sD bXo9J5I/9EqMPdZN4o/0SbpdpDIlXbXkfdEEY70Ka1+s/bwqxMRgnjXMG81YjVfyiq0LoK3t8bFh+ BQMy7a28QVLGJeVwGBFbYR3XqUvajYVV08Yozj1korUEqBglT7P+y4QNovgr6u8JIm0e28zh61vQX /zP5KMq/g7SXtvo0A8TyTlkl6HJIjMp3iov83smMNfADEQw7pVwKARz67wAtXxLIbA3eMxZmL3org IqBqh6a+X6d84gMCnK6u0Wn3fYepyjMYW1RBZZYv0vYMAltXxigcKRjYSFVXFdT4dn1hDG+XCiB0o /qasfONJqwWvnnEVQD/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8G-0000000GX2g-1KVZ; Fri, 18 Apr 2025 14:55:56 +0000 Received: from mail-qt1-x82e.google.com ([2607:f8b0:4864:20::82e]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6d-0000000GWRk-1GgU for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:16 +0000 Received: by mail-qt1-x82e.google.com with SMTP id d75a77b69052e-4775ce8a4b0so31594711cf.1 for ; Fri, 18 Apr 2025 07:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988054; x=1745592854; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XkMtzn7N02RmrS0PJQFbrGZioeU0O7QBuxxi4LcB8Zs=; b=pPntKyQwKxNHISz/013DnJMmXYg2Vn8uaR3Pl7sfd+mW5Ih7ZVIT1/zkM5f360ilRk NIUqUPY2RX7P9DPJOjdrmDgIDBgj0uYeIIb7GT3+qFwHPesWsr8zdpRVfb5u1OfMAtWb K01SZTVK1P4mzqrJvKwyLowN1vn5cEk5MlIAQybWjn1tjcVMBdj/rqZeQ58NLyKXNCox 5P+cPEs71RyLIHlZun14oqDB2dXyq9Gp1mkTR2HY40lzJr5hzhhfalwvEUqWe1Bkgoxa ++oAhz4UQI8IrVTgUjUO+iDG1sOBaufEW1LYkdbJ4tk/YC4h5FvcGMwhka6JHSTpuPxp RqZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988054; x=1745592854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XkMtzn7N02RmrS0PJQFbrGZioeU0O7QBuxxi4LcB8Zs=; b=m53aC0L0IfAtOhHDWKl+z5QzT9e4hZ0dnnzXbsGGvn6vsJGY1DYVMwAT5SaO0rtB0v QPeOMrilDdsUP/8DRoz6+L1xWe4JnwiRkLQqFRpDbRftnDcCZknLimXSm23JCsQoQeDE PH5jmg+ZLuveuRzZZvoLQZ6Yt5/mbqBxom5uLlECU0KJNWD/H0CfaZzzUoI0wtpT7nxI 5nfqIwrBRjQmCF1D/JQ/hUMihWLt6mm4soezHaPtq5r3OxTadIzwgmnnLjmyHesh4K7T QOJTjZVNH/XPy0eXmAIgtlcqLni1Z3goean4MuDzmUnZ+sSe3eROWCJ9t/DaXA0Rb2Do 83xg== X-Forwarded-Encrypted: i=1; AJvYcCXyk2xLMlqmyUiDcnXxrIIzWb4HlG1bDBx3y++auomU8dIxKX0aWYpwIJGxFeTJwMg2WJzTNOtt5B1+vA==@lists.infradead.org X-Gm-Message-State: AOJu0Yxx5lajoibBBvjWIopkp8tY1AQvImrWzdGxIQwl10QgCAKL5ly0 y9uKgHlH91V2ZVjfe47RgZ8aQ4jiPbxJpyvIj7Gv8lutAAM08XXD6/jUXQ5IOKU= X-Gm-Gg: ASbGncthneqq9wkVcfZ1ZTcvYMTEyJDhy5CO13ktQ3SVRFNZnIzagy+Z1i9M5UZbZXs n8CdHi2Ie1CIojJbACYClANbDXTjMeU4MK7NqpxSHcMEOY7OkN068XGbdEP4TPypdWVRK5s4i4w Yxap+MFfTkt/YQp/iFAxi4lt0dzZywiq/9YPcjh0TVteYoq4D59TgyOBuIV1a9EIyhMGhOWmYNa LNHCKLSsSe3xQe5BwGSlUIRQYZZRSSoxPsz6bKCSpakcShgaUw6TMdiOZstFUEBLi6/dTkfvJh0 CMERWQRZSw7YNo+RQTxtgtB9jABYuMV+dsBYK1UoX1bSCP/Oq5uS6Zz9ldIkoixjLOa1jKEzXhN iB3LChKxQ19XH3Q== X-Google-Smtp-Source: AGHT+IExljy5N60XbU6MXOLtCevb/N4vBZAyZbbO0mx88RZ5LF09j7uagInSYJoa9ykOQI9BYFdHuw== X-Received: by 2002:ac8:7d0d:0:b0:476:7199:4da1 with SMTP id d75a77b69052e-47aec4c378cmr46007231cf.46.1744988054558; Fri, 18 Apr 2025 07:54:14 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:14 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 6/7] clk: spacemit: define new syscons with only resets Date: Fri, 18 Apr 2025 09:53:58 -0500 Message-ID: <20250418145401.2603648-7-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075415_344852_4CB7D4DF X-CRM114-Status: GOOD ( 11.18 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Enable support for three additional syscon CCUs which support reset controls but no clocks: ARCPU, RCPU2, and APBC2. Signed-off-by: Alex Elder --- drivers/clk/spacemit/ccu-k1.c | 93 +++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/drivers/clk/spacemit/ccu-k1.c b/drivers/clk/spacemit/ccu-k1.c index dfc8aa60d4345..c2f057aecb705 100644 --- a/drivers/clk/spacemit/ccu-k1.c +++ b/drivers/clk/spacemit/ccu-k1.c @@ -130,6 +130,36 @@ #define APMU_EMAC0_CLK_RES_CTRL 0x3e4 #define APMU_EMAC1_CLK_RES_CTRL 0x3ec +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c + struct ccu_reset_data { u32 offset; u32 assert_mask; @@ -1177,6 +1207,57 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data = { .reset_num = ARRAY_SIZE(apmu_reset_data), }; +static const struct ccu_reset_data rcpu_reset_data[] = { + [RESET_RCPU_SSP0] = RESET_DATA(RCPU_SSP0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_I2C0] = RESET_DATA(RCPU_I2C0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART1] = RESET_DATA(RCPU_UART1_CLK_RST, 0, BIT(0)), + [RESET_RCPU_IR] = RESET_DATA(RCPU_CAN_CLK_RST, 0, BIT(0)), + [RESET_RCPU_CAN] = RESET_DATA(RCPU_IR_CLK_RST, 0, BIT(0)), + [RESET_RCPU_UART0] = RESET_DATA(RCPU_UART0_CLK_RST, 0, BIT(0)), + [RESET_RCPU_HDMI_AUDIO] = RESET_DATA(AUDIO_HDMI_CLK_CTRL, 0, BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu_data = { + /* No clocks in the RCPU CCU */ + .reset_data = rcpu_reset_data, + .reset_num = ARRAY_SIZE(rcpu_reset_data), +}; + +static const struct ccu_reset_data rcpu2_reset_data[] = { + [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { + /* No clocks in the RCPU2 CCU */ + .reset_data = rcpu2_reset_data, + .reset_num = ARRAY_SIZE(rcpu2_reset_data), +}; + +static const struct ccu_reset_data apbc2_reset_data[] = { + [RESET_APBC2_UART1] = RESET_DATA(APBC2_UART1_CLK_RST, BIT(2), 0), + [RESET_APBC2_SSP2] = RESET_DATA(APBC2_SSP2_CLK_RST, BIT(2), 0), + [RESET_APBC2_TWSI3] = RESET_DATA(APBC2_TWSI3_CLK_RST, BIT(2), 0), + [RESET_APBC2_RTC] = RESET_DATA(APBC2_RTC_CLK_RST, BIT(2), 0), + [RESET_APBC2_TIMERS0] = RESET_DATA(APBC2_TIMERS0_CLK_RST, BIT(2), 0), + [RESET_APBC2_KPC] = RESET_DATA(APBC2_KPC_CLK_RST, BIT(2), 0), + [RESET_APBC2_GPIO] = RESET_DATA(APBC2_GPIO_CLK_RST, BIT(2), 0), +}; + +static const struct spacemit_ccu_data k1_ccu_apbc2_data = { + /* No clocks in the APBC2 CCU */ + .reset_data = apbc2_reset_data, + .reset_num = ARRAY_SIZE(apbc2_reset_data), +}; + static int spacemit_reset_update(struct reset_controller_dev *rcdev, unsigned long id, bool assert) { @@ -1351,6 +1432,18 @@ static const struct of_device_id of_k1_ccu_match[] = { .compatible = "spacemit,k1-syscon-apmu", .data = &k1_ccu_apmu_data, }, + { + .compatible = "spacemit,k1-syscon-rcpu", + .data = &k1_ccu_rcpu_data, + }, + { + .compatible = "spacemit,k1-syscon-rcpu2", + .data = &k1_ccu_rcpu2_data, + }, + { + .compatible = "spacemit,k1-syscon-apbc2", + .data = &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match); From patchwork Fri Apr 18 14:53:59 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Elder X-Patchwork-Id: 14057276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2DCBDC369AB for ; Fri, 18 Apr 2025 14:56:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LG3slYx6eIb6mSZEGcawHjFcIRNEM2L5xjTR1TYQYdY=; b=W0XvII41n4rDLf PIawVYnZees8TWlQ7d+Vxs8aZXsfPC4OCN9oAyd5b2WavWBg7d9mP3zb/yGGbH8OCnlzmQ+EoPHn+ voDbB4nxU8oCWftYZSY6NEBunxE0LNdGkgvHjeM+JASteP28vTgrs0EmBjGW+e3AU6GxyPE2Ex0+d zwWMTWTJ/2V8ROZ9tTkw0hzNZPltPSdW1jfiAt3AXb4k+KzZcaM826NVYClztnnvH+8zNYzOzsldT lDqtL013Uf46840i8zgVGPCDW9ki4j2VQ6j+R/oPICrDNJS/rv6+iw04Dp5+EZpMKzSk7Cbxw1pGW 34yvFQIKp/LVsXQejSfw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n8H-0000000GX41-14H2; Fri, 18 Apr 2025 14:55:57 +0000 Received: from mail-qt1-x833.google.com ([2607:f8b0:4864:20::833]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1u5n6e-0000000GWSM-3QZv for linux-riscv@lists.infradead.org; Fri, 18 Apr 2025 14:54:17 +0000 Received: by mail-qt1-x833.google.com with SMTP id d75a77b69052e-476b89782c3so21805261cf.1 for ; Fri, 18 Apr 2025 07:54:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20230601.gappssmtp.com; s=20230601; t=1744988056; x=1745592856; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eoPF+bCrpMBavT+34w02cPZ0ktfHw7A1w/wlErW18/c=; b=L10/sx7YaziQd0ybGhunO296SZmGjpKTW4FGZCP7kw1YQ+XmQ2+HF6HpxQmiN7buBv XqDyVIGEnjrW0o2bERvKdkl/QJKRu8K3vxyAk6lnYOINCrqRYtQvHqNkdoYjUhtNtMQJ wnBFUwL3c08lqtqVVgFSuyNuNm7vLfOUR6fL6dQLeLSeHCShA5gZjqHXFg8aF3WesxES NkkO++ivBZhB04HL5Xd/pJiM/oXJKTb7x7nftzue7OAczfzP9N7vT+vFnKWftmaeo/ow +I8pMYdm+2yZxPDAMjQ1iddHjvBW5Kc3fA3fzBTsar1aeJ+6u3rzOtcMLFoOfeUxaJSS YcXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744988056; x=1745592856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eoPF+bCrpMBavT+34w02cPZ0ktfHw7A1w/wlErW18/c=; b=VWNyc18hbLGoEf/jfguDA22OIeMCJYzvTPMFKwkq++bbgfb3ARCLTHNSUIwPRvuNC3 WzO1Q2VxJ5yi95aKIR3PWiKdXoEMOZut3epb2MPoZ1+8g62JNcwWj674j0hBTrQ5eSzX BXKqxEkHos8XYUVYTC4wx0Vh1b4DFnhLR/U2eT+jug29XkNHVQE85fmbSKMEmrFfN4lM FAN3FPXuIwuHHa2aPkK9g5UwpE8vaOHeO7y3aqRkqovnHwRqzlLSHU9T7/qh1TnvU0LG aIV1+xJqhHvwYPK8/LwHIlPQ6Alcxz748apExw+GUUnVIWzgpqxi+OOHdhrzTaqhcIv5 BBNw== X-Forwarded-Encrypted: i=1; AJvYcCXGwq3hSBfuWAxcQfRO2n6HFAB5meT7uXico8B8Upp2it7pFrFnP9jN+u24HwA6YEZivp7IVGZZTEs3jg==@lists.infradead.org X-Gm-Message-State: AOJu0Yy1Tiy8SO5RG16LTrHrlbDzUZk05AA3yLXyyZyJQ5cJ6WBpEm8o UlGjQx7XxDfdJ/L1qgCsHhOqyq7dmDSvjnpV/MFO05PxGX2YOAv1TtI11RCyJVI= X-Gm-Gg: ASbGncuPCJ833+EbbKLSOTVyj5h8j7xiOItIgIuaWVj6ZJosMNqWXbSN1kDcvUcuier +Pvkholn3kGqPRpsgpsa+7d3QlfAtUGyfjwPeGobGmuDIpF06pT7e9KoonELl7evfUOvNBbMafJ MHmGnrJltiB8O4+AFGq34OmW7WL+Bl1DRuDqRlPzmXMYqAMGrj4jQK5KtKbJZW5hwol0peBZSmg OflXPAP9+r0pa9FmVAoVYAXROfiSKmfJ/Voj9jVJ1GDoCql6Csh5s9bg51JHEGoNt1FNfDBFUta n3NXQsfHNZwcvuw39x2ZnrKzpUllLWo0R7t4C37VCklwLkO36LLHUNWAn12GGlTqi/w2/MgGxe0 PRvv/UpQC60zjug== X-Google-Smtp-Source: AGHT+IHNVbMfjIlfo9PHEWLdLnnlwobHS10wrAnQS7/2BfmnC2z46vdeRRFOkin5pnaA1y6blfUwPA== X-Received: by 2002:ac8:5fc6:0:b0:479:be67:3bd2 with SMTP id d75a77b69052e-47aec3cb8f4mr50692481cf.23.1744988055824; Fri, 18 Apr 2025 07:54:15 -0700 (PDT) Received: from localhost.localdomain (c-73-228-159-35.hsd1.mn.comcast.net. [73.228.159.35]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-47ae9c16ddesm11329201cf.3.2025.04.18.07.54.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 07:54:15 -0700 (PDT) From: Alex Elder To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: p.zabel@pengutronix.de, dlan@gentoo.org, heylenay@4d2.org, guodong@riscstar.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, spacemit@lists.linux.dev, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 7/7] riscv: dts: spacemit: add reset support for the K1 SoC Date: Fri, 18 Apr 2025 09:53:59 -0500 Message-ID: <20250418145401.2603648-8-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250418145401.2603648-1-elder@riscstar.com> References: <20250418145401.2603648-1-elder@riscstar.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250418_075416_854225_A4DE7DEC X-CRM114-Status: UNSURE ( 8.81 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Define syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1. Signed-off-by: Alex Elder --- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi index 584f0dbc60f5b..491ab891788b8 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -346,6 +346,18 @@ soc { dma-noncoherent; ranges; + syscon_rcpu: system-controller@c0880000 { + compatible = "spacemit,k1-syscon-rcpu"; + reg = <0x0 0xc0880000 0x0 0x2048>; + #reset-cells = <1>; + }; + + syscon_rcpu2: system-controller@c0888000 { + compatible = "spacemit,k1-syscon-rcpu2"; + reg = <0x0 0xc0888000 0x0 0x28>; + #reset-cells = <1>; + }; + syscon_apbc: system-control@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>; @@ -514,6 +526,12 @@ clint: timer@e4000000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; + syscon_apbc2: system-controller@f0610000 { + compatible = "spacemit,k1-syscon-apbc2"; + reg = <0x0 0xf0610000 0x0 0x20>; + #reset-cells = <1>; + }; + sec_uart1: serial@f0612000 { compatible = "spacemit,k1-uart", "intel,xscale-uart"; reg = <0x0 0xf0612000 0x0 0x100>;