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Fri, 18 Apr 2025 11:47:07 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:06 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks Date: Fri, 18 Apr 2025 19:46:44 +0100 Message-ID: <20250418184658.456398-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add support for PLLDSI and PLLDSI divider clocks. Introduce the `renesas-rzv2h-dsi.h` header to centralize and share PLLDSI-related data structures, limits, and algorithms between the RZ/V2H CPG and DSI drivers. The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly different parameter limits and omits the programmable divider present in CPG. To ensure precise frequency calculations-especially for milliHz-level accuracy needed by the DSI driver-the shared algorithm allows both drivers to compute PLL parameters consistently using the same logic and input clock. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Update the commit message to clarify the purpose of `renesas-rzv2h-dsi.h` header - Used mul_u32_u32() in rzv2h_cpg_plldsi_div_determine_rate() - Replaced *_mhz to *_millihz for clarity - Updated u64->u32 for fvco limits - Initialized the members in declaration order for RZV2H_CPG_PLL_DSI_LIMITS() macro - Used clk_div_mask() in rzv2h_cpg_plldsi_div_recalc_rate() - Replaced `unsigned long long` with u64 - Dropped rzv2h_cpg_plldsi_clk_recalc_rate() and reused rzv2h_cpg_pll_clk_recalc_rate() instead - In rzv2h_cpg_plldsi_div_set_rate() followed the same style of RMW-operation as done in the other functions - Renamed rzv2h_cpg_plldsi_set_rate() to rzv2h_cpg_pll_set_rate() - Dropped rzv2h_cpg_plldsi_clk_register() and reused rzv2h_cpg_pll_clk_register() instead - Added a gaurd in renesas-rzv2h-dsi.h header v1->v2: - No changes --- drivers/clk/renesas/rzv2h-cpg.c | 237 +++++++++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 14 ++ include/linux/clk/renesas-rzv2h-dsi.h | 211 +++++++++++++++++++++++ 3 files changed, 460 insertions(+), 2 deletions(-) create mode 100644 include/linux/clk/renesas-rzv2h-dsi.h diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index 60f8a585ae8b..ce14f527d88e 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -14,9 +14,13 @@ #include #include #include +#include #include #include #include +#include +#include +#include #include #include #include @@ -26,6 +30,7 @@ #include #include #include +#include #include @@ -48,6 +53,7 @@ #define CPG_PLL_STBY(x) ((x)) #define CPG_PLL_STBY_RESETB BIT(0) #define CPG_PLL_STBY_RESETB_WEN BIT(16) +#define CPG_PLL_STBY_SSCGEN_WEN BIT(18) #define CPG_PLL_CLK1(x) ((x) + 0x004) #define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x))) #define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x)) @@ -79,6 +85,8 @@ * @last_dt_core_clk: ID of the last Core Clock exported to DT * @mstop_count: Array of mstop values * @rcdev: Reset controller entity + * @dsi_limits: PLL DSI parameters limits + * @plldsi_div_parameters: PLL DSI and divider parameters configuration */ struct rzv2h_cpg_priv { struct device *dev; @@ -95,6 +103,9 @@ struct rzv2h_cpg_priv { atomic_t *mstop_count; struct reset_controller_dev rcdev; + + const struct rzv2h_pll_div_limits *dsi_limits; + struct rzv2h_plldsi_parameters plldsi_div_parameters; }; #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) @@ -148,6 +159,24 @@ struct ddiv_clk { #define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div) +/** + * struct rzv2h_plldsi_div_clk - PLL DSI DDIV clock + * + * @dtable: divider table + * @priv: CPG private data + * @hw: divider clk + * @ddiv: divider configuration + */ +struct rzv2h_plldsi_div_clk { + const struct clk_div_table *dtable; + struct rzv2h_cpg_priv *priv; + struct clk_hw hw; + struct ddiv ddiv; +}; + +#define to_plldsi_div_clk(_hw) \ + container_of(_hw, struct rzv2h_plldsi_div_clk, hw) + static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw) { struct pll_clk *pll_clk = to_pll(hw); @@ -196,6 +225,188 @@ static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw) return ret; } +static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv = dsi_div->priv; + struct ddiv ddiv = dsi_div->ddiv; + u32 div; + + div = readl(priv->base + ddiv.offset); + div >>= ddiv.shift; + div &= clk_div_mask(ddiv.width); + div = dsi_div->dtable[div].div; + + return DIV_ROUND_CLOSEST_ULL(parent_rate, div); +} + +static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv = dsi_div->priv; + struct rzv2h_plldsi_parameters *dsi_dividers = &priv->plldsi_div_parameters; + u64 rate_millihz; + + /* + * Adjust the requested clock rate (`req->rate`) to ensure it falls within + * the supported range of 5.44 MHz to 187.5 MHz. + */ + req->rate = clamp(req->rate, 5440000UL, 187500000UL); + + rate_millihz = mul_u32_u32(req->rate, MILLI); + if (rate_millihz == dsi_dividers->error_millihz + dsi_dividers->freq_millihz) + goto exit_determine_rate; + + if (!rzv2h_dsi_get_pll_parameters_values(priv->dsi_limits, + dsi_dividers, rate_millihz)) { + dev_err(priv->dev, + "failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + +exit_determine_rate: + req->best_parent_rate = req->rate * dsi_dividers->csdiv; + + return 0; +}; + +static int rzv2h_cpg_plldsi_div_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rzv2h_plldsi_div_clk *dsi_div = to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv = dsi_div->priv; + struct rzv2h_plldsi_parameters *dsi_dividers = &priv->plldsi_div_parameters; + struct ddiv ddiv = dsi_div->ddiv; + const struct clk_div_table *clkt; + bool div_found = false; + u32 val, shift, div; + + div = dsi_dividers->csdiv; + for (clkt = dsi_div->dtable; clkt->div; clkt++) { + if (clkt->div == div) { + div_found = true; + break; + } + } + + if (!div_found) + return -EINVAL; + + shift = ddiv.shift; + val = readl(priv->base + ddiv.offset) | DDIV_DIVCTL_WEN(shift); + val &= ~(clk_div_mask(ddiv.width) << shift); + val |= (u32)clkt->val << shift; + writel(val, priv->base + ddiv.offset); + + return 0; +}; + +static const struct clk_ops rzv2h_cpg_plldsi_div_ops = { + .recalc_rate = rzv2h_cpg_plldsi_div_recalc_rate, + .determine_rate = rzv2h_cpg_plldsi_div_determine_rate, + .set_rate = rzv2h_cpg_plldsi_div_set_rate, +}; + +static struct clk * __init +rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core_clk *core, + struct rzv2h_cpg_priv *priv) +{ + struct rzv2h_plldsi_div_clk *clk_hw_data; + struct clk **clks = priv->clks; + struct clk_init_data init; + const struct clk *parent; + const char *parent_name; + struct clk_hw *clk_hw; + int ret; + + parent = clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv = priv; + clk_hw_data->ddiv = core->cfg.ddiv; + clk_hw_data->dtable = core->dtable; + + parent_name = __clk_get_name(parent); + init.name = core->name; + init.ops = &rzv2h_cpg_plldsi_div_ops; + init.flags = core->flag; + init.parent_names = &parent_name; + init.num_parents = 1; + + clk_hw = &clk_hw_data->hw; + clk_hw->init = &init; + + ret = devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw->clk; +} + +static long rzv2h_cpg_plldsi_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return clamp(rate, 25000000UL, 375000000UL); +} + +static int rzv2h_cpg_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk = to_pll(hw); + struct rzv2h_cpg_priv *priv = pll_clk->priv; + struct rzv2h_plldsi_parameters *dsi_dividers; + struct pll pll = pll_clk->pll; + u16 offset = pll.offset; + u32 val; + int ret; + + /* Put PLL into standby mode */ + writel(CPG_PLL_STBY_RESETB_WEN, priv->base + CPG_PLL_STBY(offset)); + ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), + val, !(val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(priv->dev, "Failed to put PLLDSI into standby mode"); + return ret; + } + + dsi_dividers = &priv->plldsi_div_parameters; + /* Output clock setting 1 */ + writel((dsi_dividers->k << 16) | (dsi_dividers->m << 6) | (dsi_dividers->p), + priv->base + CPG_PLL_CLK1(offset)); + + /* Output clock setting 2 */ + val = readl(priv->base + CPG_PLL_CLK2(offset)); + writel((val & ~GENMASK(2, 0)) | dsi_dividers->s, + priv->base + CPG_PLL_CLK2(offset)); + + /* Put PLL to normal mode */ + writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB, + priv->base + CPG_PLL_STBY(offset)); + + /* PLL normal mode transition, output clock stability check */ + ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), + val, (val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(priv->dev, "Failed to put PLLDSI into normal mode"); + return ret; + } + + return 0; +}; + static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -217,6 +428,12 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1)); } +static const struct clk_ops rzv2h_cpg_plldsi_ops = { + .recalc_rate = rzv2h_cpg_pll_clk_recalc_rate, + .round_rate = rzv2h_cpg_plldsi_round_rate, + .set_rate = rzv2h_cpg_pll_set_rate, +}; + static const struct clk_ops rzv2h_cpg_pll_ops = { .is_enabled = rzv2h_cpg_pll_clk_is_enabled, .enable = rzv2h_cpg_pll_clk_enable, @@ -226,7 +443,8 @@ static const struct clk_ops rzv2h_cpg_pll_ops = { static struct clk * __init rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv, - const struct clk_ops *ops) + const struct clk_ops *ops, + bool turn_on) { void __iomem *base = priv->base; struct device *dev = priv->dev; @@ -256,6 +474,13 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, pll_clk->base = base; pll_clk->priv = priv; + if (turn_on) { + /* Disable SSC and turn on PLL clock when init */ + writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB | + CPG_PLL_STBY_SSCGEN_WEN, + base + CPG_PLL_STBY(pll_clk->pll.offset)); + } + ret = devm_clk_hw_register(dev, &pll_clk->hw); if (ret) return ERR_PTR(ret); @@ -497,7 +722,7 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, clk = clk_hw->clk; break; case CLK_TYPE_PLL: - clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); + clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops, false); break; case CLK_TYPE_DDIV: clk = rzv2h_cpg_ddiv_clk_register(core, priv); @@ -505,6 +730,12 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core, case CLK_TYPE_SMUX: clk = rzv2h_cpg_mux_clk_register(core, priv); break; + case CLK_TYPE_PLLDSI: + clk = rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_plldsi_ops, true); + break; + case CLK_TYPE_PLLDSI_DIV: + clk = rzv2h_cpg_plldsi_div_clk_register(core, priv); + break; default: goto fail; } @@ -1040,6 +1271,8 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) priv->last_dt_core_clk = info->last_dt_core_clk; priv->num_resets = info->num_resets; + priv->dsi_limits = info->plldsi_limits; + for (i = 0; i < nclks; i++) clks[i] = ERR_PTR(-ENOENT); diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index fbfd411c7ca8..5cdb0f67852e 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -100,6 +100,7 @@ struct smuxed { #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) #define CPG_CSDIV0 (0x500) +#define CPG_CSDIV1 (0x504) #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) @@ -163,6 +164,8 @@ enum clk_types { CLK_TYPE_PLL, CLK_TYPE_DDIV, /* Dynamic Switching Divider */ CLK_TYPE_SMUX, /* Static Mux */ + CLK_TYPE_PLLDSI, /* PLLDSI */ + CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */ }; #define DEF_TYPE(_name, _id, _type...) \ @@ -190,6 +193,14 @@ enum clk_types { .num_parents = ARRAY_SIZE(_parent_names), \ .flag = CLK_SET_RATE_PARENT, \ .mux_flags = CLK_MUX_HIWORD_MASK) +#define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent = _parent, .cfg.pll = _pll_packed) +#define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \ + .cfg.ddiv = _ddiv_packed, \ + .dtable = _dtable, \ + .parent = _parent, \ + .flag = CLK_SET_RATE_PARENT) /** * struct rzv2h_mod_clk - Module Clocks definitions @@ -301,6 +312,7 @@ struct rzv2h_reset { * * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to the * number of CPG_BUS_m_MSTOP registers multiplied by 16. + * @plldsi_limits: PLL DSI parameters limits */ struct rzv2h_cpg_info { /* Core Clocks */ @@ -319,6 +331,8 @@ struct rzv2h_cpg_info { unsigned int num_resets; unsigned int num_mstop_bits; + + const struct rzv2h_pll_div_limits *plldsi_limits; }; extern const struct rzv2h_cpg_info r9a09g047_cpg_info; diff --git a/include/linux/clk/renesas-rzv2h-dsi.h b/include/linux/clk/renesas-rzv2h-dsi.h new file mode 100644 index 000000000000..41fdcf0c3d31 --- /dev/null +++ b/include/linux/clk/renesas-rzv2h-dsi.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/V2H(P) DSI CPG helper + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __RENESAS_RZV2H_DSI_H__ +#define __RENESAS_RZV2H_DSI_H__ + +#include +#include +#include +#include + +#define OSC_CLK_IN_MEGA (24 * MEGA) + +struct rzv2h_pll_div_limits { + struct { + u32 min; + u32 max; + } fvco; + + struct { + u16 min; + u16 max; + } m; + + struct { + u8 min; + u8 max; + } p; + + struct { + u8 min; + u8 max; + } s; + + struct { + s16 min; + s16 max; + } k; + + struct { + u8 min; + u8 max; + } csdiv; +}; + +struct rzv2h_plldsi_parameters { + u64 freq_millihz; + s64 error_millihz; + u16 m; + s16 k; + u8 csdiv; + u8 p; + u8 s; +}; + +#define RZV2H_CPG_PLL_DSI_LIMITS(name) \ + static const struct rzv2h_pll_div_limits (name) = { \ + .fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \ + .m = { .min = 64, .max = 533 }, \ + .p = { .min = 1, .max = 4 }, \ + .s = { .min = 0, .max = 6 }, \ + .k = { .min = -32768, .max = 32767 }, \ + .csdiv = { .min = 2, .max = 32 }, \ + } \ + +/** + * rzv2h_dsi_get_pll_parameters_values - Finds the best combination of PLL parameters + * and divider value for a given frequency. + * + * @limits: Pointer to the structure containing the limits for the PLL parameters and + * divider values + * @pars: Pointer to the structure where the best calculated PLL parameters and divider + * values will be stored + * @freq: Target output frequency (in mHz) + * + * This function calculates the best set of PLL parameters (M, K, P, S) and divider + * value (CSDIV) to achieve the desired frequency. + * There is no direct formula to calculate the PLL parameters and the divider value, + * as it's an open system of equations, therefore this function uses an iterative + * approach to determine the best solution. The best solution is one that minimizes + * the error (desired frequency - actual frequency). + * + * Return: true if a valid set of divider values is found, false otherwise. + */ +static __maybe_unused bool +rzv2h_dsi_get_pll_parameters_values(const struct rzv2h_pll_div_limits *limits, + struct rzv2h_plldsi_parameters *pars, + u64 freq_millihz) +{ + struct rzv2h_plldsi_parameters p, best; + + /* Initialize best error to maximum possible value */ + best.error_millihz = S64_MAX; + + for (p.csdiv = limits->csdiv.min; p.csdiv <= limits->csdiv.max; p.csdiv += 2) { + for (p.p = limits->p.min; p.p <= limits->p.max; p.p++) { + u32 fref = OSC_CLK_IN_MEGA / p.p; + + for (p.s = limits->s.min; p.s <= limits->s.max; p.s++) { + u16 two_pow_s = 1 << p.s; + u16 divider = two_pow_s * p.csdiv; + + for (p.m = limits->m.min; p.m <= limits->m.max; p.m++) { + u64 output_m, output_k_range; + s64 pll_k, output_k; + u64 fvco, output; + + /* + * The frequency generated by the combination of the + * PLL + divider is calculated as follows: + * + * Freq = Ffout / csdiv + * + * With: + * Ffout = Ffvco / 2^(pll_s) + * Ffvco = (pll_m + (pll_k / 65536)) * Ffref + * Ffref = 24MHz / pll_p + * + * Freq can also be rewritten as: + * Freq = Ffvco / (2^(pll_s) * csdiv)) + * = Ffvco / divider + * = (pll_m * Ffref) / divider + ((pll_k / 65536) * Ffref) / divider + * = output_m + output_k + * + * Every parameter has been determined at this point, but pll_k. + * Considering that: + * -32768 <= pll_k <= 32767 + * Then: + * -0.5 <= (pll_k / 65536) < 0.5 + * Therefore: + * -Ffref / (2 * divider) <= output_k < Ffref / (2 * divider) + */ + + /* Compute output M component (in mHz) */ + output_m = DIV_ROUND_CLOSEST_ULL(p.m * fref * 1000ULL, + divider); + /* Compute range for output K (in mHz) */ + output_k_range = DIV_ROUND_CLOSEST_ULL(fref * 1000ULL, + divider * 2); + /* + * No point in continuing if we can't achieve the + * desired frequency + */ + if (freq_millihz < (output_m - output_k_range) || + freq_millihz >= (output_m + output_k_range)) + continue; + + /* + * Compute the K component + * + * Since: + * Freq = output_m + output_k + * Then: + * output_k = Freq - output_m + * = ((pll_k / 65536) * Ffref) / divider + * Therefore: + * pll_k = (output_k * 65536 * divider) / Ffref + */ + output_k = freq_millihz - output_m; + pll_k = div64_s64(output_k * 65536ULL * divider, fref); + pll_k = DIV_S64_ROUND_CLOSEST(pll_k, 1000); + + /* Validate K value within allowed limits */ + if (pll_k < limits->k.min || pll_k > limits->k.max) + continue; + + p.k = pll_k; + + /* Compute (Ffvco * 65536) */ + fvco = ((p.m * 65536ULL) + p.k) * fref; + if ((fvco < (limits->fvco.min * 65536ULL)) || + (fvco > (limits->fvco.max * 65536ULL))) + continue; + + /* PLL_M component of (output * 65536 * PLL_P) */ + output = p.m * 65536ULL * OSC_CLK_IN_MEGA; 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Fri, 18 Apr 2025 11:47:09 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:08 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 02/15] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC Date: Fri, 18 Apr 2025 19:46:45 +0100 Message-ID: <20250418184658.456398-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK() - Renamed plleth_lpclk_div4 -> cdiv4_plleth_lpclk - Renamed plleth_lpclk -> plleth_lpclk_gear v1->v2: - Changed CSDIV0_DIVCTL2 to the NO_RMW --- drivers/clk/renesas/r9a09g057-cpg.c | 63 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 3 ++ 2 files changed, 66 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c index 057bfa0e2a57..dcd84cda4aff 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -30,6 +31,7 @@ enum clk_ids { CLK_PLLCA55, CLK_PLLVDO, CLK_PLLETH, + CLK_PLLDSI, CLK_PLLGPU, /* Internal Core Clocks */ @@ -58,6 +60,9 @@ enum clk_ids { CLK_SMUX2_GBE0_RXCLK, CLK_SMUX2_GBE1_TXCLK, CLK_SMUX2_GBE1_RXCLK, + CLK_DIV_PLLETH_LPCLK, + CLK_CSDIV_PLLETH_LPCLK, + CLK_PLLDSI_SDIV2, CLK_PLLGPU_GEAR, /* Module Clocks */ @@ -78,6 +83,26 @@ static const struct clk_div_table dtable_2_4[] = { {0, 0}, }; +static const struct clk_div_table dtable_2_32[] = { + {0, 2}, + {1, 4}, + {2, 6}, + {3, 8}, + {4, 10}, + {5, 12}, + {6, 14}, + {7, 16}, + {8, 18}, + {9, 20}, + {10, 22}, + {11, 24}, + {12, 26}, + {13, 28}, + {14, 30}, + {15, 32}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] = { {0, 2}, {1, 4}, @@ -94,6 +119,14 @@ static const struct clk_div_table dtable_2_100[] = { {0, 0}, }; +static const struct clk_div_table dtable_16_128[] = { + {0, 16}, + {1, 32}, + {2, 64}, + {3, 128}, + {0, 0}, +}; + /* Mux clock tables */ static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0-rxc-rxclk" }; static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0-txc-txclk" }; @@ -113,6 +146,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), + DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI), DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), /* Internal Core Clocks */ @@ -148,6 +182,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), + DEF_FIXED(".cdiv4_plleth_lpclk", CLK_DIV_PLLETH_LPCLK, CLK_PLLETH, 1, 4), + DEF_CSDIV(".plleth_lpclk_gear", CLK_CSDIV_PLLETH_LPCLK, CLK_DIV_PLLETH_LPCLK, + CSDIV0_DIVCTL2, dtable_16_128), + + DEF_PLLDSI_DIV(".plldsi_sdiv2", CLK_PLLDSI_SDIV2, CLK_PLLDSI, + CSDIV1_DIVCTL2, dtable_2_32), DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), @@ -327,6 +367,22 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { BUS_MSTOP(9, BIT(7))), DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, BUS_MSTOP(9, BIT(7))), + DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_SDIV2, 14, 10, 7, 10, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_lpclk", CLK_CSDIV_PLLETH_LPCLK, 14, 11, 7, 11, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), + DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), + DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_SDIV2, 14, 15, 7, 15, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, @@ -388,11 +444,16 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ + DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */ + DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */ + DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */ DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ }; +RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits); + const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { /* Core Clocks */ .core_clks = r9a09g057_core_clks, @@ -410,4 +471,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { .num_resets = ARRAY_SIZE(r9a09g057_resets), .num_mstop_bits = 192, + + .plldsi_limits = &rzv2h_cpg_pll_dsi_limits, }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index 5cdb0f67852e..2ae409fd65a3 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -28,6 +28,7 @@ struct pll { }) #define PLLCA55 PLL_PACK(0x60, 1) +#define PLLDSI PLL_PACK(0xc0, 1) #define PLLGPU PLL_PACK(0x120, 1) /** @@ -117,6 +118,8 @@ struct smuxed { #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON) +#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON) #define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) #define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) From patchwork Fri Apr 18 18:46:46 2025 Content-Type: text/plain; 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Fri, 18 Apr 2025 11:47:10 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:09 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v3 03/15] dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC Date: Fri, 18 Apr 2025 19:46:46 +0100 Message-ID: <20250418184658.456398-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The DU block on the RZ/V2H(P) SoC is identical to the one found on the RZ/G2L SoC. However, it only supports the DSI interface, whereas the RZ/G2L supports both DSI and DPI interfaces. Due to this difference, a SoC-specific compatible string 'renesas,r9a09g057-du' is added for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski --- v2->v3: - Collected reviewed tag from Krzysztof v1->v2: - Kept the sort order for schema validation - Added `port@1: false` for RZ/V2H(P) SoC --- .../bindings/display/renesas,rzg2l-du.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 95e3d5e74b87..1e32d14b6edb 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -20,6 +20,7 @@ properties: - enum: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} + - renesas,r9a09g057-du # RZ/V2H(P) - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -101,7 +102,12 @@ allOf: required: - port@0 - else: + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-du + then: properties: ports: properties: @@ -113,6 +119,21 @@ allOf: required: - port@0 - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-du + then: + properties: + ports: + properties: + port@0: + description: DSI + port@1: false + + required: + - port@0 examples: # RZ/G2L DU From patchwork Fri Apr 18 18:46:47 2025 Content-Type: text/plain; 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Fri, 18 Apr 2025 11:47:11 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v3 04/15] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC Date: Fri, 18 Apr 2025 19:46:47 +0100 Message-ID: <20250418184658.456398-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To accommodate these differences, a SoC-specific `renesas,r9a09g057-mipi-dsi` compatible string has been added for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski --- v2->v3: - No changes v1->v2: - Added enum for RZ/V2H as suggested by Krzysztof as the list will grow in the future (while adding RZ/G3E SoC). - Added Reviewed-by tag from Krzysztof. --- .../bindings/display/bridge/renesas,dsi.yaml | 116 +++++++++++++----- 1 file changed, 87 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926..5980df2b389b 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,17 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) + + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi reg: maxItems: 1 @@ -49,34 +50,56 @@ properties: - const: debug clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst power-domains: maxItems: 1 @@ -130,6 +153,41 @@ required: additionalProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include From patchwork Fri Apr 18 18:46:48 2025 Content-Type: text/plain; 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Fri, 18 Apr 2025 11:47:13 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:12 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 05/15] drm: renesas: rz-du: Add support for RZ/V2H(P) SoC Date: Fri, 18 Apr 2025 19:46:48 +0100 Message-ID: <20250418184658.456398-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame Compression Processor (FCPVD), Video Signal Processor (VSPD), and Display Unit (DU). There is one LCDC unit available on the RZ/V2H(P) SoC which is connected to the DSI. Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c index 5e40f0c1e7b0..e1aa6a719529 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -50,9 +50,20 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { } }; +static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = { + .channels_mask = BIT(0), + .routes = { + [RZG2L_DU_OUTPUT_DSI0] = { + .possible_outputs = BIT(0), + .port = 0, + }, + }, +}; + static const struct of_device_id rzg2l_du_of_table[] = { { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info }, { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info }, + { .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info }, { /* sentinel */ } }; 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Fri, 18 Apr 2025 11:47:14 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:13 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 06/15] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range Date: Fri, 18 Apr 2025 19:46:49 +0100 Message-ID: <20250418184658.456398-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar The VCLK range for Renesas RZ/G2L SoC is 148.5 MHz to 5.803 MHz. Add a minimum clock check in the mode_valid callback to ensure that the clock value does not fall below the valid range. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v2->v3: - No changes v1->v2: - Added Reviewed-by tag from Biju --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 4550c6d84796..ec8baecb9ba5 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -584,6 +584,9 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock > 148500) return MODE_CLOCK_HIGH; + if (mode->clock < 5803) + return MODE_CLOCK_LOW; + return MODE_OK; } From patchwork Fri Apr 18 18:46:50 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14057594 X-Patchwork-Delegate: kieran@bingham.xyz Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37DA82417F2; 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Fri, 18 Apr 2025 11:47:16 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:15 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 07/15] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation Date: Fri, 18 Apr 2025 19:46:50 +0100 Message-ID: <20250418184658.456398-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Simplify the high-speed clock frequency (HSFREQ) calculation by removing the redundant multiplication and division by 8. The updated equation: hsfreq = (mode->clock * bpp) / (dsi->lanes); produces the same result while improving readability and clarity. Additionally, update the comment to clarify the relationship between HS clock bit frequency, HS byte clock frequency, and HSFREQ. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v2->v3: - No changes v1->v2: - Added Reviewed-by tag from Biju --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index ec8baecb9ba5..c5f698cd74f1 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -277,10 +277,10 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, * hsclk: DSI HS Byte clock frequency (Hz) * lanes: number of data lanes * - * hsclk(bit) = hsclk(byte) * 8 + * hsclk(bit) = hsclk(byte) * 8 = hsfreq */ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); + hsfreq = (mode->clock * bpp) / dsi->lanes; ret = pm_runtime_resume_and_get(dsi->dev); if (ret < 0) From patchwork Fri Apr 18 18:46:51 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14057595 X-Patchwork-Delegate: kieran@bingham.xyz Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3512245033; 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Fri, 18 Apr 2025 11:47:17 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:16 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation Date: Fri, 18 Apr 2025 19:46:51 +0100 Message-ID: <20250418184658.456398-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VCLK rate instead of the mode clock. The relationship between HSCLK and VCLK is: vclk * bpp <= hsclk * 8 * lanes Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that HSFREQ accurately reflects the clock rate set in hardware, leading to better precision in data transmission. Additionally, use `DIV_ROUND_CLOSEST_ULL` for a more precise division when computing `hsfreq`. Also, update unit conversions to use correct scaling factors for better clarity and correctness. Since `clk_get_rate()` returns the clock rate in Hz, update the HSFREQ threshold comparisons to use Hz instead of kHz to ensure correct behavior. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 27 ++++++++++--------- 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index c5f698cd74f1..8fa86ae07fd2 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include #include @@ -199,7 +201,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, /* All DSI global operation timings are set with recommended setting */ for (i = 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { dphy_timings = &rzg2l_mipi_dsi_global_timings[i]; - if (hsfreq <= dphy_timings->hsfreq_max) + if (hsfreq <= (dphy_timings->hsfreq_max * KILO)) break; } @@ -258,7 +260,7 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq; + unsigned long hsfreq, vclk_rate; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -269,6 +271,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, u32 golpbkt; int ret; + ret = pm_runtime_resume_and_get(dsi->dev); + if (ret < 0) + return ret; + + clk_set_rate(dsi->vclk, mode->clock * KILO); + /* * Relationship between hsclk and vclk must follow * vclk * bpp = hsclk * 8 * lanes @@ -280,13 +288,8 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, * hsclk(bit) = hsclk(byte) * 8 = hsfreq */ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - hsfreq = (mode->clock * bpp) / dsi->lanes; - - ret = pm_runtime_resume_and_get(dsi->dev); - if (ret < 0) - return ret; - - clk_set_rate(dsi->vclk, mode->clock * 1000); + vclk_rate = clk_get_rate(dsi->vclk); + hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); if (ret < 0) @@ -304,12 +307,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, * - data lanes: maximum 4 lanes * Therefore maximum hsclk will be 891 Mbps. */ - if (hsfreq > 445500) { + if (hsfreq > 445500000) { clkkpt = 12; clkbfht = 15; clkstpt = 48; golpbkt = 75; - } else if (hsfreq > 250000) { + } else if (hsfreq > 250000000) { clkkpt = 7; clkbfht = 8; clkstpt = 27; @@ -753,7 +756,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) * mode->clock and format are not available. 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Fri, 18 Apr 2025 11:47:19 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:18 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 09/15] drm: renesas: rz-du: mipi_dsi: Add OF data support Date: Fri, 18 Apr 2025 19:46:52 +0100 Message-ID: <20250418184658.456398-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar In preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch introduces a mechanism to pass SoC-specific information via OF data in the DSI driver. This enables the driver to adapt dynamically to various SoC-specific requirements without hardcoding configurations. The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to the one on the RZ/G2L SoC. While the LINK registers are shared between the two SoCs, the D-PHY registers differ. Also the VCLK range differs on both these SoCs. To accommodate these differences `struct rzg2l_mipi_dsi_hw_info` is introduced and as now passed as OF data. These changes lay the groundwork for the upcoming RZ/V2H(P) SoC support by allowing SoC-specific data to be passed through OF. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Dropped !dsi->info check in rzg2l_mipi_dsi_probe() as it is not needed. v1->v2: - Added DPHY_RST as feature flag --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 65 ++++++++++++++----- .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 2 - 2 files changed, 48 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 8fa86ae07fd2..564c15b27c31 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -28,10 +28,26 @@ #include "rzg2l_mipi_dsi_regs.h" +#define RZ_MIPI_DSI_FEATURE_DPHY_RST BIT(0) + +struct rzg2l_mipi_dsi; + +struct rzg2l_mipi_dsi_hw_info { + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); + void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); + u32 phy_reg_offset; + u32 link_reg_offset; + unsigned long max_dclk; + unsigned long min_dclk; + u8 features; +}; + struct rzg2l_mipi_dsi { struct device *dev; void __iomem *mmio; + const struct rzg2l_mipi_dsi_hw_info *info; + struct reset_control *rstc; struct reset_control *arstc; struct reset_control *prstc; @@ -164,22 +180,22 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = { static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) { - iowrite32(data, dsi->mmio + reg); + iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); } static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) { - iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); + iowrite32(data, dsi->mmio + dsi->info->link_reg_offset + reg); } static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { - return ioread32(dsi->mmio + reg); + return ioread32(dsi->mmio + dsi->info->phy_reg_offset + reg); } static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) { - return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); + return ioread32(dsi->mmio + dsi->info->link_reg_offset + reg); } /* ----------------------------------------------------------------------------- @@ -291,7 +307,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, vclk_rate = clk_get_rate(dsi->vclk); hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); - ret = rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); + ret = dsi->info->dphy_init(dsi, hsfreq); if (ret < 0) goto err_phy; @@ -334,7 +350,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, return 0; err_phy: - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); return ret; @@ -342,7 +358,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi) { - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); } @@ -584,10 +600,12 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, const struct drm_display_info *info, const struct drm_display_mode *mode) { - if (mode->clock > 148500) + struct rzg2l_mipi_dsi *dsi = bridge_to_rzg2l_mipi_dsi(bridge); + + if (mode->clock > dsi->info->max_dclk) return MODE_CLOCK_HIGH; - if (mode->clock < 5803) + if (mode->clock < dsi->info->min_dclk) return MODE_CLOCK_LOW; return MODE_OK; @@ -713,6 +731,8 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dsi); dsi->dev = &pdev->dev; + dsi->info = of_device_get_match_data(&pdev->dev); + ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4); if (ret < 0) return dev_err_probe(dsi->dev, ret, @@ -728,10 +748,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); - dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); - if (IS_ERR(dsi->rstc)) - return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), - "failed to get rst\n"); + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_DPHY_RST) { + dsi->rstc = devm_reset_control_get_exclusive(dsi->dev, "rst"); + if (IS_ERR(dsi->rstc)) + return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), + "failed to get rst\n"); + } dsi->arstc = devm_reset_control_get_exclusive(dsi->dev, "arst"); if (IS_ERR(dsi->arstc)) @@ -756,13 +778,13 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) * mode->clock and format are not available. So initialize DPHY with * timing parameters for 80Mbps. */ - ret = rzg2l_mipi_dsi_dphy_init(dsi, 80000000); + ret = dsi->info->dphy_init(dsi, 80000000); if (ret < 0) goto err_phy; txsetr = rzg2l_mipi_dsi_link_read(dsi, TXSETR); dsi->num_data_lanes = min(((txsetr >> 16) & 3) + 1, num_data_lanes); - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); /* Initialize the DRM bridge. */ @@ -779,7 +801,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) return 0; err_phy: - rzg2l_mipi_dsi_dphy_exit(dsi); + dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); err_pm_disable: pm_runtime_disable(dsi->dev); @@ -794,8 +816,17 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); } +static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { + .dphy_init = rzg2l_mipi_dsi_dphy_init, + .dphy_exit = rzg2l_mipi_dsi_dphy_exit, + .link_reg_offset = 0x10000, + .max_dclk = 148500, + .min_dclk = 5803, + .features = RZ_MIPI_DSI_FEATURE_DPHY_RST, +}; + static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { - { .compatible = "renesas,rzg2l-mipi-dsi" }, + { .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h index 1dbc16ec64a4..16efe4dc59f4 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h @@ -41,8 +41,6 @@ #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) /* --------------------------------------------------------*/ -/* Link Registers */ -#define LINK_REG_OFFSET 0x10000 /* Link Status Register */ #define LINKSR 0x10 From patchwork Fri Apr 18 18:46:53 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14057597 X-Patchwork-Delegate: kieran@bingham.xyz Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B32F22D4DD; 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Fri, 18 Apr 2025 11:47:20 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:20 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 10/15] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Date: Fri, 18 Apr 2025 19:46:53 +0100 Message-ID: <20250418184658.456398-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve precision, especially for the RZ/V2H(P) SoC, where PLL dividers require high accuracy. These changes prepare the driver for upcoming RZ/V2H(P) SoC support. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Replaced `unsigned long long` with `u64` - Replaced *_mhz with *_millihz` in functions v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 564c15b27c31..0204af85fc64 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -33,7 +33,7 @@ struct rzg2l_mipi_dsi; struct rzg2l_mipi_dsi_hw_info { - int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq); + int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); u32 phy_reg_offset; u32 link_reg_offset; @@ -203,8 +203,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) */ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, - unsigned long hsfreq) + u64 hsfreq_millihz) { + unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); const struct rzg2l_mipi_dsi_timings *dphy_timings; unsigned int i; u32 dphyctrl0; @@ -277,6 +278,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { unsigned long hsfreq, vclk_rate; + u64 hsfreq_millihz; unsigned int bpp; u32 txsetr; u32 clstptsetr; @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, */ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); vclk_rate = clk_get_rate(dsi->vclk); - hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); + hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes); - ret = dsi->info->dphy_init(dsi, hsfreq); + ret = dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) goto err_phy; @@ -315,6 +317,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); + hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); /* * Global timings characteristic depends on high speed Clock Frequency * Currently MIPI DSI-IF just supports maximum FHD@60 with: @@ -778,7 +781,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) * mode->clock and format are not available. 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Fri, 18 Apr 2025 11:47:22 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:21 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 11/15] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support Date: Fri, 18 Apr 2025 19:46:54 +0100 Message-ID: <20250418184658.456398-12-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info` to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports 16BPP, whereas this feature is missing on the RZ/G2L SoC. Update the `mipi_dsi_host_attach()` function to check this flag before allowing 16BPP formats. If the SoC does not support 16BPP, return an error to prevent incorrect format selection. This change enables finer-grained format support control for different SoC variants. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - Renamed RZ_MIPI_DSI_FEATURE_16BPP --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 0204af85fc64..36b8ef95f20b 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -29,6 +29,7 @@ #include "rzg2l_mipi_dsi_regs.h" #define RZ_MIPI_DSI_FEATURE_DPHY_RST BIT(0) +#define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) struct rzg2l_mipi_dsi; @@ -643,8 +644,16 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, switch (mipi_dsi_pixel_format_to_bpp(device->format)) { case 24: + break; case 18: break; + case 16: + if (!(dsi->info->features & RZ_MIPI_DSI_FEATURE_16BPP)) { + dev_err(dsi->dev, "Unsupported format 0x%04x\n", + device->format); + return -EINVAL; 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Fri, 18 Apr 2025 11:47:23 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:22 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Date: Fri, 18 Apr 2025 19:46:55 +0100 Message-ID: <20250418184658.456398-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to allow additional D-PHY register configurations after enabling data and clock lanes. This is required for the RZ/V2H(P) SoC but not for the RZ/G2L SoC. Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined, ensuring SoC-specific initialization is performed only when necessary. This change prepares for RZ/V2H(P) SoC support while maintaining compatibility with existing platforms. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - No changes --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 36b8ef95f20b..c3bd3b21dd15 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -35,6 +35,7 @@ struct rzg2l_mipi_dsi; struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); + void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); u32 phy_reg_offset; u32 link_reg_offset; @@ -318,6 +319,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN; rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); + if (dsi->info->dphy_late_init) + dsi->info->dphy_late_init(dsi); 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Fri, 18 Apr 2025 11:47:25 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:24 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 13/15] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Date: Fri, 18 Apr 2025 19:46:56 +0100 Message-ID: <20250418184658.456398-14-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in `rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate supported display modes. On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as possible. To ensure compatibility with both RZ/G2L and RZ/V2H(P) SoCs, function pointers are introduced. Modify `rzg2l_mipi_dsi_startup()` to use `dphy_conf_clks` for clock configuration and `rzg2l_mipi_dsi_bridge_mode_valid()` to invoke `dphy_mode_clk_check` for mode validation. This change ensures proper operation across different SoC variants by allowing fine-grained control over clock configuration and mode validation. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Replaced unsigned long long with u64 v1->v2: - No changes --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 59 +++++++++++++------ 1 file changed, 42 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index c3bd3b21dd15..67520bb21dad 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -37,6 +37,10 @@ struct rzg2l_mipi_dsi_hw_info { int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); + int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq, + u64 *hsfreq_millihz); + unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq); u32 phy_reg_offset; u32 link_reg_offset; unsigned long max_dclk; @@ -276,12 +280,36 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) reset_control_assert(dsi->rstc); } +static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq, + u64 *hsfreq_millihz) +{ + unsigned long vclk_rate; + unsigned int bpp; + + clk_set_rate(dsi->vclk, mode_freq * KILO); + /* + * Relationship between hsclk and vclk must follow + * vclk * bpp = hsclk * 8 * lanes + * where vclk: video clock (Hz) + * bpp: video pixel bit depth + * hsclk: DSI HS Byte clock frequency (Hz) + * lanes: number of data lanes + * + * hsclk(bit) = hsclk(byte) * 8 = hsfreq + */ + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + vclk_rate = clk_get_rate(dsi->vclk); + *hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, + dsi->lanes); + + return 0; +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { - unsigned long hsfreq, vclk_rate; + unsigned long hsfreq; u64 hsfreq_millihz; - unsigned int bpp; u32 txsetr; u32 clstptsetr; u32 lptrnstsetr; @@ -295,21 +323,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, if (ret < 0) return ret; - clk_set_rate(dsi->vclk, mode->clock * KILO); - - /* - * Relationship between hsclk and vclk must follow - * vclk * bpp = hsclk * 8 * lanes - * where vclk: video clock (Hz) - * bpp: video pixel bit depth - * hsclk: DSI HS Byte clock frequency (Hz) - * lanes: number of data lanes - * - * hsclk(bit) = hsclk(byte) * 8 = hsfreq - */ - bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); - vclk_rate = clk_get_rate(dsi->vclk); - hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp * KILO * 1ULL, dsi->lanes); + ret = dsi->info->dphy_conf_clks(dsi, mode->clock, &hsfreq_millihz); + if (ret < 0) + goto err_phy; ret = dsi->info->dphy_init(dsi, hsfreq_millihz); if (ret < 0) @@ -616,6 +632,14 @@ rzg2l_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, if (mode->clock < dsi->info->min_dclk) return MODE_CLOCK_LOW; + if (dsi->info->dphy_mode_clk_check) { + enum drm_mode_status status; + + status = dsi->info->dphy_mode_clk_check(dsi, mode->clock); + if (status != MODE_OK) + return status; + } + return MODE_OK; } @@ -835,6 +859,7 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev) static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { .dphy_init = rzg2l_mipi_dsi_dphy_init, .dphy_exit = rzg2l_mipi_dsi_dphy_exit, + .dphy_conf_clks = rzg2l_dphy_conf_clks, .link_reg_offset = 0x10000, .max_dclk = 148500, .min_dclk = 5803, From patchwork Fri Apr 18 18:46:57 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 14057601 X-Patchwork-Delegate: kieran@bingham.xyz Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 495DB254B1D; Fri, 18 Apr 2025 18:47:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 18 Apr 2025 11:47:26 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:25 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 14/15] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK handling Date: Fri, 18 Apr 2025 19:46:57 +0100 Message-ID: <20250418184658.456398-15-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Introduce the `RZ_MIPI_DSI_FEATURE_LPCLK` feature flag in `rzg2l_mipi_dsi_hw_info` to indicate the need for LPCLK configuration. On the RZ/V2H(P) SoC, the LPCLK clock rate influences the required DPHY register configuration, whereas on the RZ/G2L SoC, this clock is not present. To accommodate this difference, add an `lpclk` clock handle in `rzg2l_mipi_dsi` and update the probe function to conditionally acquire LPCLK if the SoC supports it. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - No changes v1->v2: - Added LPCLK as feature flag --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 67520bb21dad..133a8f306d47 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -30,6 +30,7 @@ #define RZ_MIPI_DSI_FEATURE_DPHY_RST BIT(0) #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) +#define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2) struct rzg2l_mipi_dsi; @@ -63,6 +64,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; struct clk *vclk; + struct clk *lpclk; enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -788,6 +790,12 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); + if (dsi->info->features & RZ_MIPI_DSI_FEATURE_LPCLK) { + dsi->lpclk = devm_clk_get(dsi->dev, "lpclk"); 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Fri, 18 Apr 2025 11:47:28 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:36cb:c641:13d7:bd3d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39efa4931b8sm3404336f8f.80.2025.04.18.11.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Apr 2025 11:47:27 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Biju Das , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v3 15/15] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Date: Fri, 18 Apr 2025 19:46:58 +0100 Message-ID: <20250418184658.456398-16-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250418184658.456398-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v2->v3: - Simplifed V2H DSI timings array to save space - Switched to use fsleep() instead of udelay() v1->v2: - Dropped unused macros - Added missing LPCLK flag to rzvv2h info --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 344 ++++++++++++++++++ .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++ 2 files changed, 378 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 133a8f306d47..a957b6c5f28d 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corporation */ #include +#include #include #include #include @@ -32,6 +33,9 @@ #define RZ_MIPI_DSI_FEATURE_16BPP BIT(1) #define RZ_MIPI_DSI_FEATURE_LPCLK BIT(2) +#define RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA (80 * MEGA) +#define RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA (1500 * MEGA) + struct rzg2l_mipi_dsi; struct rzg2l_mipi_dsi_hw_info { @@ -42,6 +46,7 @@ struct rzg2l_mipi_dsi_hw_info { u64 *hsfreq_millihz); unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq); + const struct rzv2h_pll_div_limits *cpg_dsi_limits; u32 phy_reg_offset; u32 link_reg_offset; unsigned long max_dclk; @@ -49,6 +54,11 @@ struct rzg2l_mipi_dsi_hw_info { u8 features; }; +struct rzv2h_dsi_mode_calc { + unsigned long mode_freq; + u64 mode_freq_hz; +}; + struct rzg2l_mipi_dsi { struct device *dev; void __iomem *mmio; @@ -70,6 +80,18 @@ struct rzg2l_mipi_dsi { unsigned int num_data_lanes; unsigned int lanes; unsigned long mode_flags; + + struct rzv2h_dsi_mode_calc mode_calc; + struct rzv2h_plldsi_parameters dsi_parameters; +}; + +static const struct rzv2h_pll_div_limits rzv2h_plldsi_div_limits = { + .fvco = { .min = 1050 * MEGA, .max = 2100 * MEGA }, + .m = { .min = 64, .max = 1023 }, + .p = { .min = 1, .max = 4 }, + .s = { .min = 0, .max = 5 }, + .k = { .min = -32768, .max = 32767 }, + .csdiv = { .min = 1, .max = 1 }, }; static inline struct rzg2l_mipi_dsi * @@ -186,6 +208,155 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = { }, }; +struct rzv2h_mipi_dsi_timings { + const u8 *hsfreq; + u8 len; + u8 start_index; +}; + +enum { + TCLKPRPRCTL, + TCLKZEROCTL, + TCLKPOSTCTL, + TCLKTRAILCTL, + THSPRPRCTL, + THSZEROCTL, + THSTRAILCTL, + TLPXCTL, + THSEXITCTL, +}; + +static const u8 tclkprprctl[] = { + 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150, +}; + +static const u8 tclkzeroctl[] = { + 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38, + 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73, + 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105, + 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132, + 134, 137, 139, 141, 143, 146, 148, 150, +}; + +static const u8 tclkpostctl[] = { + 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150, +}; + +static const u8 tclktrailctl[] = { + 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150, +}; + +static const u8 thsprprctl[] = { + 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150, +}; + +static const u8 thszeroctl[] = { + 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90, + 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150, +}; + +static const u8 thstrailctl[] = { + 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150, +}; + +static const u8 tlpxctl[] = { + 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150, +}; + +static const u8 thsexitctl[] = { + 15, 23, 31, 39, 47, 55, 63, 71, 79, 87, + 95, 103, 111, 119, 127, 135, 143, 150, +}; + +static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] = { + [TCLKPRPRCTL] = { + .hsfreq = tclkprprctl, + .len = ARRAY_SIZE(tclkprprctl), + .start_index = 0, + }, + [TCLKZEROCTL] = { + .hsfreq = tclkzeroctl, + .len = ARRAY_SIZE(tclkzeroctl), + .start_index = 2, + }, + [TCLKPOSTCTL] = { + .hsfreq = tclkpostctl, + .len = ARRAY_SIZE(tclkpostctl), + .start_index = 6, + }, + [TCLKTRAILCTL] = { + .hsfreq = tclktrailctl, + .len = ARRAY_SIZE(tclktrailctl), + .start_index = 1, + }, + [THSPRPRCTL] = { + .hsfreq = thsprprctl, + .len = ARRAY_SIZE(thsprprctl), + .start_index = 0, + }, + [THSZEROCTL] = { + .hsfreq = thszeroctl, + .len = ARRAY_SIZE(thszeroctl), + .start_index = 0, + }, + [THSTRAILCTL] = { + .hsfreq = thstrailctl, + .len = ARRAY_SIZE(thstrailctl), + .start_index = 3, + }, + [TLPXCTL] = { + .hsfreq = tlpxctl, + .len = ARRAY_SIZE(tlpxctl), + .start_index = 0, + }, + [THSEXITCTL] = { + .hsfreq = thsexitctl, + .len = ARRAY_SIZE(thsexitctl), + .start_index = 1, + }, +}; + +static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq) +{ + const unsigned long hsfreq[] = { + 1953125UL, + 3906250UL, + 7812500UL, + 15625000UL, + }; + const u16 ulpsexit[] = {49, 98, 195, 391}; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(hsfreq); i++) { + if (freq <= hsfreq[i]) + break; + } + + if (i == ARRAY_SIZE(hsfreq)) + i -= 1; + + return ulpsexit[i]; +} + +static u16 rzv2h_dphy_find_timings_val(unsigned long freq, u8 index) +{ + const struct rzv2h_mipi_dsi_timings *timings; + u16 i; + + timings = &rzv2h_dsi_timings_tables[index]; + for (i = 0; i < timings->len; i++) { + unsigned long hsfreq = timings->hsfreq[i] * 10000000UL; + + if (freq <= hsfreq) + break; + } + + if (i == timings->len) + i -= 1; + + return timings->start_index + i; +}; + static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) { iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); @@ -307,6 +478,158 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_f return 0; } +static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq) +{ + struct rzv2h_plldsi_parameters *dsi_parameters = &dsi->dsi_parameters; + u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz; + struct rzv2h_plldsi_parameters cpg_dsi_parameters; + unsigned int bpp, i; + + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + + for (i = 0; i < 10; i += 1) { + unsigned long hsfreq; + bool parameters_found; + + mode_freq_hz = mode_freq * KILO + i; + mode_freq_millihz = mode_freq_hz * KILO * 1ULL; + parameters_found = rzv2h_dsi_get_pll_parameters_values(dsi->info->cpg_dsi_limits, + &cpg_dsi_parameters, + mode_freq_millihz); + if (!parameters_found) + continue; + + hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(cpg_dsi_parameters.freq_millihz * bpp, + dsi->lanes); + parameters_found = rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_div_limits, + dsi_parameters, + hsfreq_millihz); + if (!parameters_found) + continue; + + if (abs(dsi_parameters->error_millihz) >= 500) + continue; + + hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); + if (hsfreq >= RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA && + hsfreq <= RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA) { + dsi->mode_calc.mode_freq_hz = mode_freq_hz; + dsi->mode_calc.mode_freq = mode_freq; + return MODE_OK; + } + } + + return MODE_CLOCK_RANGE; +} + +static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq, + u64 *hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters = &dsi->dsi_parameters; + unsigned long status; + + if (dsi->mode_calc.mode_freq != mode_freq) { + status = rzv2h_dphy_mode_clk_check(dsi, mode_freq); + if (status != MODE_OK) { + dev_err(dsi->dev, "No PLL parameters found for mode clk %lu\n", + mode_freq); + return -EINVAL; + } + } + + clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz); + *hsfreq_millihz = dsi_parameters->freq_millihz; + + return 0; +} + +static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, + u64 hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters = &dsi->dsi_parameters; + unsigned long lpclk_rate = clk_get_rate(dsi->lpclk); + u32 phytclksetr, phythssetr, phytlpxsetr, phycr; + struct rzg2l_mipi_dsi_timings dphy_timings; + u16 ulpsexit; + u64 hsfreq; + + hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, KILO); + + if (dsi_parameters->freq_millihz == hsfreq_millihz) + goto parameters_found; + + if (rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_div_limits, + dsi_parameters, hsfreq_millihz)) + goto parameters_found; + + dev_err(dsi->dev, "No PLL parameters found for HSFREQ %lluHz\n", hsfreq); + return -EINVAL; + +parameters_found: + dphy_timings.tclk_trail = + rzv2h_dphy_find_timings_val(hsfreq, TCLKTRAILCTL); + dphy_timings.tclk_post = + rzv2h_dphy_find_timings_val(hsfreq, TCLKPOSTCTL); + dphy_timings.tclk_zero = + rzv2h_dphy_find_timings_val(hsfreq, TCLKZEROCTL); + dphy_timings.tclk_prepare = + rzv2h_dphy_find_timings_val(hsfreq, TCLKPRPRCTL); + dphy_timings.ths_exit = + rzv2h_dphy_find_timings_val(hsfreq, THSEXITCTL); + dphy_timings.ths_trail = + rzv2h_dphy_find_timings_val(hsfreq, THSTRAILCTL); + dphy_timings.ths_zero = + rzv2h_dphy_find_timings_val(hsfreq, THSZEROCTL); + dphy_timings.ths_prepare = + rzv2h_dphy_find_timings_val(hsfreq, THSPRPRCTL); + dphy_timings.tlpx = + rzv2h_dphy_find_timings_val(hsfreq, TLPXCTL); + ulpsexit = rzv2h_dphy_find_ulpsexit(lpclk_rate); + + phytclksetr = PHYTCLKSETR_TCLKTRAILCTL(dphy_timings.tclk_trail) | + PHYTCLKSETR_TCLKPOSTCTL(dphy_timings.tclk_post) | + PHYTCLKSETR_TCLKZEROCTL(dphy_timings.tclk_zero) | + PHYTCLKSETR_TCLKPRPRCTL(dphy_timings.tclk_prepare); + phythssetr = PHYTHSSETR_THSEXITCTL(dphy_timings.ths_exit) | + PHYTHSSETR_THSTRAILCTL(dphy_timings.ths_trail) | + PHYTHSSETR_THSZEROCTL(dphy_timings.ths_zero) | + PHYTHSSETR_THSPRPRCTL(dphy_timings.ths_prepare); + phytlpxsetr = rzg2l_mipi_dsi_phy_read(dsi, PHYTLPXSETR) & ~GENMASK(7, 0); + phytlpxsetr |= PHYTLPXSETR_TLPXCTL(dphy_timings.tlpx); + phycr = rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0); + phycr |= PHYCR_ULPSEXIT(ulpsexit); + + /* Setting all D-PHY Timings Registers */ + rzg2l_mipi_dsi_phy_write(dsi, PHYTCLKSETR, phytclksetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTHSSETR, phythssetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTLPXSETR, phytlpxsetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYCR, phycr); + + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET0R, + PLLCLKSET0R_PLL_S(dsi_parameters->s) | + PLLCLKSET0R_PLL_P(dsi_parameters->p) | + PLLCLKSET0R_PLL_M(dsi_parameters->m)); + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R, PLLCLKSET1R_PLL_K(dsi_parameters->k)); + fsleep(20); + + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, PLLENR_PLLEN); + fsleep(500); + + return 0; +} + +static void rzv2h_mipi_dsi_dphy_late_init(struct rzg2l_mipi_dsi *dsi) +{ + fsleep(220); + rzg2l_mipi_dsi_phy_write(dsi, PHYRSTR, PHYRSTR_PHYMRSTN); +} + +static void rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) +{ + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, 0); +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { @@ -409,6 +732,9 @@ static void rzg2l_mipi_dsi_set_display_timing(struct rzg2l_mipi_dsi *dsi, case 18: vich1ppsetr = VICH1PPSETR_DT_RGB18; break; + case 16: + vich1ppsetr = VICH1PPSETR_DT_RGB16; + break; } if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) && @@ -864,6 +1190,23 @@ static void rzg2l_mipi_dsi_remove(struct platform_device *pdev) pm_runtime_disable(&pdev->dev); } +RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits); + +static const struct rzg2l_mipi_dsi_hw_info rzv2h_mipi_dsi_info = { + .dphy_init = rzv2h_mipi_dsi_dphy_init, + .dphy_late_init = rzv2h_mipi_dsi_dphy_late_init, + .dphy_exit = rzv2h_mipi_dsi_dphy_exit, + .dphy_mode_clk_check = rzv2h_dphy_mode_clk_check, + .dphy_conf_clks = rzv2h_dphy_conf_clks, + .cpg_dsi_limits = &rzv2h_cpg_pll_dsi_limits, + .phy_reg_offset = 0x10000, + .link_reg_offset = 0, + .max_dclk = 187500, + .min_dclk = 5440, + .features = RZ_MIPI_DSI_FEATURE_16BPP | + RZ_MIPI_DSI_FEATURE_LPCLK, +}; + static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { .dphy_init = rzg2l_mipi_dsi_dphy_init, .dphy_exit = rzg2l_mipi_dsi_dphy_exit, @@ -875,6 +1218,7 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { }; static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { + { .compatible = "renesas,r9a09g057-mipi-dsi", .data = &rzv2h_mipi_dsi_info, }, { .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h index 16efe4dc59f4..68165395d61c 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h @@ -40,6 +40,39 @@ #define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) +/* RZ/V2H DPHY Registers */ +#define PLLENR 0x000 +#define PLLENR_PLLEN BIT(0) + +#define PHYRSTR 0x004 +#define PHYRSTR_PHYMRSTN BIT(0) + +#define PLLCLKSET0R 0x010 +#define PLLCLKSET0R_PLL_S(x) ((x) << 0) +#define PLLCLKSET0R_PLL_P(x) ((x) << 8) +#define PLLCLKSET0R_PLL_M(x) ((x) << 16) + +#define PLLCLKSET1R 0x014 +#define PLLCLKSET1R_PLL_K(x) ((x) << 0) + +#define PHYTCLKSETR 0x020 +#define PHYTCLKSETR_TCLKTRAILCTL(x) ((x) << 0) +#define PHYTCLKSETR_TCLKPOSTCTL(x) ((x) << 8) +#define PHYTCLKSETR_TCLKZEROCTL(x) ((x) << 16) +#define PHYTCLKSETR_TCLKPRPRCTL(x) ((x) << 24) + +#define PHYTHSSETR 0x024 +#define PHYTHSSETR_THSEXITCTL(x) ((x) << 0) +#define PHYTHSSETR_THSTRAILCTL(x) ((x) << 8) +#define PHYTHSSETR_THSZEROCTL(x) ((x) << 16) +#define PHYTHSSETR_THSPRPRCTL(x) ((x) << 24) + +#define PHYTLPXSETR 0x028 +#define PHYTLPXSETR_TLPXCTL(x) ((x) << 0) + +#define PHYCR 0x030 +#define PHYCR_ULPSEXIT(x) ((x) << 0) + /* --------------------------------------------------------*/ /* Link Status Register */ @@ -116,6 +149,7 @@ /* Video-Input Channel 1 Pixel Packet Set Register */ #define VICH1PPSETR 0x420 +#define VICH1PPSETR_DT_RGB16 (0x0e << 16) #define VICH1PPSETR_DT_RGB18 (0x1e << 16) #define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) #define VICH1PPSETR_DT_RGB24 (0x3e << 16)