From patchwork Fri Mar 22 20:25:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B7C71669 for ; Fri, 22 Mar 2019 20:26:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6A7862A830 for ; Fri, 22 Mar 2019 20:26:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5DFD32A832; Fri, 22 Mar 2019 20:26:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E240E2A832 for ; Fri, 22 Mar 2019 20:26:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727947AbfCVU0l (ORCPT ); Fri, 22 Mar 2019 16:26:41 -0400 Received: from mail-eopbgr720071.outbound.protection.outlook.com ([40.107.72.71]:57856 "EHLO NAM05-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726589AbfCVU0l (ORCPT ); Fri, 22 Mar 2019 16:26:41 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ypHsmOzKoO8CbtlP60gaGkfz+t4ohUU+fEsdKDjkjAE=; b=1Mf/49jvNxe1xlryohx96QjGlzd6wtu2MBqGnULysOHEgpy5L0F8YrMJCVkPAj8rwICNzZNbnRAPdr94WrQXsCeHFx+DCXtNqw/5Qz+Ff4YRj+YRESc6leVKzV+JInXhuWDhvvdSnGWvseD6dwOqDVNpcQDYazf9PnxVkcDSg7o= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2687.namprd12.prod.outlook.com (52.135.103.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.16; Fri, 22 Mar 2019 20:25:58 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b%5]) with mapi id 15.20.1709.015; Fri, 22 Mar 2019 20:25:58 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Natarajan, Janakarajan" Subject: [PATCH 1/6] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Topic: [PATCH 1/6] acpi/cppc: Ensure only supported CPPC sysfs entries are created Thread-Index: AQHU4O113BSSNkgmEEC187+8w8GSwQ== Date: Fri, 22 Mar 2019 20:25:58 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9fbdd0c2-848e-404d-60a9-08d6af0497b2 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2687; x-ms-traffictypediagnostic: SN6PR12MB2687: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(39860400002)(396003)(136003)(376002)(189003)(199004)(7736002)(11346002)(71190400001)(5660300002)(14454004)(71200400001)(478600001)(6436002)(446003)(72206003)(2616005)(476003)(305945005)(97736004)(68736007)(2501003)(6486002)(256004)(105586002)(486006)(118296001)(54906003)(53936002)(110136005)(81166006)(2906002)(81156014)(25786009)(99286004)(6512007)(106356001)(8936002)(36756003)(50226002)(102836004)(4326008)(26005)(6116002)(2201001)(6506007)(66066001)(3846002)(76176011)(316002)(386003)(86362001)(52116002)(186003)(8676002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2687;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Duckk0lyZt/Yc4po6656TX3h2XSloemvdd8vsmqGGDpB8st6Z0JQTKDZcCg+H0ynm1+qI84BTi2MO0bqR6MVC/9A5JpPxTS6R9rmkpHR3VclgtoaOOfq8NuCZXxfv64A5keVR4d/i9IUhikJCwUvc5I7T+Bt2F8G7BvLluVfeyHcmEzCzcwLh6lVWg2QLpsZyfue2x+lgeacPo6ZBnGIX8A2GooJ1VNA0xHbGkfjHmpL7vR46jxE0ffpZAqCu0iW/sqmlOeklK2wZ2gyo4w0/0FB/g8ZjwVncWHx6SueEPLEFqk8QKY2d/4s6FpQ7udilKPw2a0KEAqwV5vCtq4lPSjcIiWyz/h3c+FEuGw2txsFx6CZ6nkmBVWVLyraBMpVjl6MtyfnCo/u2igaLkV8joJZwjh6mw+LftQpL/YIfCg= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9fbdd0c2-848e-404d-60a9-08d6af0497b2 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:25:58.4617 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2687 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add attributes for registers that are supported by the platform. This prevents unsupported optional registers from having sysfs entries created. Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 70 ++++++++++++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 14 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 1b207fca1420..66fad270376c 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -179,22 +179,8 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, } define_one_cppc_ro(feedback_ctrs); -static struct attribute *cppc_attrs[] = { - &feedback_ctrs.attr, - &reference_perf.attr, - &wraparound_time.attr, - &highest_perf.attr, - &lowest_perf.attr, - &lowest_nonlinear_perf.attr, - &nominal_perf.attr, - &nominal_freq.attr, - &lowest_freq.attr, - NULL -}; - static struct kobj_type cppc_ktype = { .sysfs_ops = &kobj_sysfs_ops, - .default_attrs = cppc_attrs, }; static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit) @@ -709,6 +695,57 @@ static bool is_cppc_supported(int revision, int num_ent) * } */ +int set_cppc_attrs(struct cpc_desc *cpc, int entries) +{ + static struct attribute **cppc_attrs; + int i, attr_i = 0; + + /* Extra for feedback_ctrs to be exposed via sysfs */ + cppc_attrs = kcalloc(entries + 1, sizeof(*cppc_attrs), GFP_KERNEL); + if (!cppc_attrs) + return -ENOMEM; + + for (i = 0; i < MAX_CPC_REG_ENT && attr_i < entries; i++) { + if (!CPC_SUPPORTED(&cpc->cpc_regs[i])) + continue; + + switch (i) { + case HIGHEST_PERF: + cppc_attrs[attr_i++] = &highest_perf.attr; + break; + case NOMINAL_PERF: + cppc_attrs[attr_i++] = &nominal_perf.attr; + break; + case LOW_NON_LINEAR_PERF: + cppc_attrs[attr_i++] = &lowest_nonlinear_perf.attr; + break; + case LOWEST_PERF: + cppc_attrs[attr_i++] = &lowest_perf.attr; + break; + case NOMINAL_FREQ: + cppc_attrs[attr_i++] = &nominal_freq.attr; + break; + case LOWEST_FREQ: + cppc_attrs[attr_i++] = &lowest_freq.attr; + break; + case REFERENCE_PERF: + cppc_attrs[attr_i++] = &reference_perf.attr; + break; + case CTR_WRAP_TIME: + cppc_attrs[attr_i++] = &wraparound_time.attr; + break; + } + } + + /* Set feedback_ctr sysfs entry */ + cppc_attrs[attr_i] = &feedback_ctrs.attr; + + /* Set kobj_type member */ + cppc_ktype.default_attrs = cppc_attrs; + + return 0; +} + /** * acpi_cppc_processor_probe - Search for per CPU _CPC objects. * @pr: Ptr to acpi_processor containing this CPUs logical Id. @@ -863,6 +900,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) /* Plug PSD data into this CPUs CPC descriptor. */ per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr; + ret = set_cppc_attrs(cpc_ptr, num_ent - 2); + if (ret) + goto out_free; + ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj, "acpi_cppc"); if (ret) { @@ -924,6 +965,7 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr) iounmap(addr); } + kfree(cppc_ktype.default_attrs); kobject_put(&cpc_ptr->kobj); kfree(cpc_ptr); } From patchwork Fri Mar 22 20:26:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866519 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AEA5E1669 for ; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH 2/6] acpi/cppc: Modify show_cppc_data macro Thread-Topic: [PATCH 2/6] acpi/cppc: Modify show_cppc_data macro Thread-Index: AQHU4O1279XO3Ni5CkWTaxJe5psZ4A== Date: Fri, 22 Mar 2019 20:26:00 +0000 Message-ID: <5b049c67394c96a21f561399e577ff5dbf1fa0a4.1553285718.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 6d880b2e-954f-41ac-ee39-08d6af0498d6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2687; x-ms-traffictypediagnostic: SN6PR12MB2687: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(39860400002)(396003)(136003)(376002)(189003)(199004)(7736002)(11346002)(71190400001)(5660300002)(14454004)(71200400001)(478600001)(6436002)(446003)(72206003)(2616005)(476003)(305945005)(97736004)(68736007)(2501003)(6486002)(14444005)(256004)(105586002)(486006)(118296001)(54906003)(53936002)(110136005)(81166006)(2906002)(81156014)(25786009)(99286004)(6512007)(106356001)(8936002)(36756003)(50226002)(102836004)(4326008)(26005)(6116002)(2201001)(6506007)(66066001)(3846002)(76176011)(316002)(386003)(86362001)(52116002)(186003)(8676002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2687;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Vv/dmoG57YpzsbwBnb8CYfF827HeUnH6FpdX93/5MZHUOGiLwRaipZz+nhbcDtsP2eMx02/VE1nv3iWNY7mVxgM5sORT9v0m81IxsW+Ft0pC23K+XVcPVAALYXSM3o91/zgVuLdy/BcLkHlEik0Q58JoGwCBSiKugyNGAhWlP+lnJIFq+8K8fjN3kFfnXzVgSSyTBunTQaOeNeuYszX448T8QrsEfQ0/pTJbDM8ckSEfC/C/85LuW8SJa7pbneeZrUCNrIW3hd4MOtn0N1R5RfsZgFf6Q8zDTyTqvgTWmczNq2zm6sc+oqO2y/vRJ7c+RDk+qcTe2PzHZ7S3u8BfVxp/2OAqF/br1joX2gzIDur0IZlN25mWkUX5SUpyGROnkVqjML3+RoDhG8poP4RrdsN/6ZNWe6eTGsMt8WovPYM= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6d880b2e-954f-41ac-ee39-08d6af0498d6 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:26:00.2869 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2687 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam The show_cppc_data macro implicity uses define_one_cppc_ro. This will prevent the creation of an attribute with read and write permissions. Create a separate macro that defines a show attribute and creates a read-only sysfs entry. This is in preparation for adding a macro to create sysfs entries with read+write permission. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 66fad270376c..9daeb0b034d5 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -151,17 +151,20 @@ __ATTR(_name, 0444, show_##_name, NULL) return scnprintf(buf, PAGE_SIZE, "%llu\n", \ (u64)st_name.member_name); \ } \ + +#define show_cppc_data_ro(access_fn, struct_name, member_name) \ + show_cppc_data(access_fn, struct_name, member_name) \ define_one_cppc_ro(member_name) -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); -show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, highest_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); +show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); +show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); static ssize_t show_feedback_ctrs(struct kobject *kobj, struct attribute *attr, char *buf) From patchwork Fri Mar 22 20:26:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4AB1C139A for ; Fri, 22 Mar 2019 20:26:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C8D12A830 for ; Fri, 22 Mar 2019 20:26:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 304E12A834; Fri, 22 Mar 2019 20:26:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 992442A830 for ; Fri, 22 Mar 2019 20:26:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727899AbfCVU0k (ORCPT ); Fri, 22 Mar 2019 16:26:40 -0400 Received: from mail-eopbgr690060.outbound.protection.outlook.com ([40.107.69.60]:13587 "EHLO NAM04-CO1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727839AbfCVU0j (ORCPT ); Fri, 22 Mar 2019 16:26:39 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sgQachq8VeiInYdzKF4eJJorRhyrfl2FDTiMgRAfLLg=; b=xgSPojH4jeGcGUBu8Eq9ucWkCWrR6apGWqyG4C23HevvPU7JaNDlF522aiiwpDxGfmW7EnHndBwvXk68UadL/0Mzsr8B3Bk1gDxLJwtieNKdaM02QG5Rz8uzo9TwYVuHLBInOyGPgeY87ZB2AdH62CMQVVmsyxgAedMX6lJmos8= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2687.namprd12.prod.outlook.com (52.135.103.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.16; Fri, 22 Mar 2019 20:26:08 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b%5]) with mapi id 15.20.1709.015; Fri, 22 Mar 2019 20:26:08 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH 3/6] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Topic: [PATCH 3/6] acpi/cppc: Rework cppc_set_perf() to use cppc_regs index Thread-Index: AQHU4O17a9va4LXrc0+ezVzya9jPUw== Date: Fri, 22 Mar 2019 20:26:08 +0000 Message-ID: <13617b46c2ed526ffa614c39d50cd32d58fc3c3b.1553285718.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: ead36795-c8b9-4390-935d-08d6af049db4 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(4618075)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2687; x-ms-traffictypediagnostic: SN6PR12MB2687: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(39860400002)(396003)(136003)(376002)(189003)(199004)(7736002)(11346002)(71190400001)(5660300002)(14454004)(71200400001)(478600001)(6436002)(446003)(72206003)(2616005)(476003)(305945005)(97736004)(68736007)(2501003)(6486002)(14444005)(256004)(105586002)(486006)(118296001)(54906003)(53936002)(110136005)(81166006)(2906002)(81156014)(25786009)(99286004)(6512007)(106356001)(8936002)(36756003)(50226002)(102836004)(4326008)(26005)(6116002)(2201001)(6506007)(66066001)(3846002)(76176011)(316002)(386003)(86362001)(52116002)(186003)(8676002);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2687;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: qNuRoeB3CeBwJfLpA1Fg1GvMFax2pncfrFR630rrfphNZ1pSiFuqE0sPV1Mcx39EHzWeUM58XfsyZ7hI15JULyUIDvt4vAlNGOCLktiFRHyIDiICoYXxdrvQYUfRgES9RWMpSfs+AvtZX2fodBaXP9KAxjq/4rGj2bB8NFMVU1e8b5xqa9kKmcvzAQ5AyIRfXqGz5DGX+PM4Ek1fssJNJKtzp9gVukFIXw4N/p/zKpVHA6NKmFfgdsYRJDMs5wNv+VuNHmB/G5iS5ku7A8U4Z2RwTEsdKQnhrOFgWmmeqDa51H3K6scsOF9c1BFpLCSYAhCRppT+rOnO+aSJEasxpFnXhrOZbZJDNJDeG+D0hNst1Ciw47LNqpYQe4R1f6bu2/rV0fKlG1eiLIFZmsTiodQ9vGEScBH4XB7DZF0tWVI= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ead36795-c8b9-4390-935d-08d6af049db4 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:26:08.2962 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2687 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam The cppc_set_perf() currently only works for DESIRED_PERF. To make it generic, pass in the index of the register being accessed. Also, rename cppc_set_perf() to cppc_set_reg(). This is in preparation for it to be used for more than just the DESIRED_PERF register. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 36 ++++++++++++++++++++++------------ drivers/cpufreq/cppc_cpufreq.c | 6 +++--- include/acpi/cppc_acpi.h | 2 +- 3 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 9daeb0b034d5..e81c19316628 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -60,7 +60,7 @@ struct cppc_pcc_data { /* * Lock to provide controlled access to the PCC channel. * - * For performance critical usecases(currently cppc_set_perf) + * For performance-critical usecases(currently cppc_set_reg) * We need to take read_lock and check if channel belongs to OSPM * before reading or writing to PCC subspace * We need to take write_lock before transferring the channel @@ -1303,26 +1303,38 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); /** - * cppc_set_perf - Set a CPUs performance controls. - * @cpu: CPU for which to set performance controls. + * cppc_set_reg - Set the CPUs control register. + * @cpu: CPU for which to set the register. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * @reg_idx: Index of the register being accessed * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, + enum cppc_regs reg_idx) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); - struct cpc_register_resource *desired_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; + struct cpc_register_resource *reg; int ret = 0; + u32 value; if (!cpc_desc) { pr_debug("No CPC descriptor for CPU:%d\n", cpu); return -ENODEV; } - desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + switch (reg_idx) { + case DESIRED_PERF: + value = perf_ctrls->desired_perf; + break; + default: + pr_debug("CPC register index #%d not writeable\n", reg_idx); + return -EINVAL; + } + + reg = &cpc_desc->cpc_regs[reg_idx]; /* * This is Phase-I where we want to write to CPC registers @@ -1331,7 +1343,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Since read_lock can be acquired by multiple CPUs simultaneously we * achieve that goal here */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1358,14 +1370,14 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * Skip writing MIN/MAX until Linux knows how to come up with * useful values. */ - cpc_write(cpu, desired_reg, perf_ctrls->desired_perf); + cpc_write(cpu, reg, value); - if (CPC_IN_PCC(desired_reg)) + if (CPC_IN_PCC(reg)) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform * - * Short Summary: Basically if we think of a group of cppc_set_perf + * Short Summary: Basically if we think of a group of cppc_set_reg * requests that happened in short overlapping interval. The last CPU to * come out of Phase-I will enter Phase-II and ring the doorbell. * @@ -1408,7 +1420,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(desired_reg)) { + if (CPC_IN_PCC(reg)) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) @@ -1424,7 +1436,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } return ret; } -EXPORT_SYMBOL_GPL(cppc_set_perf); +EXPORT_SYMBOL_GPL(cppc_set_reg); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 2ae978d27e61..420bd44f6958 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -211,7 +211,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_policy *policy, freqs.new = target_freq; cpufreq_freq_transition_begin(policy, &freqs); - ret = cppc_set_perf(cpu->cpu, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu->cpu, &cpu->perf_ctrls, DESIRED_PERF); cpufreq_freq_transition_end(policy, &freqs, ret != 0); if (ret) @@ -235,7 +235,7 @@ static void cppc_cpufreq_stop_cpu(struct cpufreq_policy *policy) cpu->perf_ctrls.desired_perf = cpu->perf_caps.lowest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.lowest_perf, cpu_num, ret); @@ -348,7 +348,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) cpu->perf_caps.highest_perf); cpu->perf_ctrls.desired_perf = cpu->perf_caps.highest_perf; - ret = cppc_set_perf(cpu_num, &cpu->perf_ctrls); + ret = cppc_set_reg(cpu_num, &cpu->perf_ctrls, DESIRED_PERF); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", cpu->perf_caps.highest_perf, cpu_num, ret); diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index ba6fd7202775..ba3b3fb64572 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,7 +139,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Fri Mar 22 20:26:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF04E139A for ; Fri, 22 Mar 2019 20:27:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C34E12A832 for ; Fri, 22 Mar 2019 20:27:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B75042A830; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH 4/6] acpi/cppc: Add macros to define a R/W sysfs entry for CPPC registers Thread-Topic: [PATCH 4/6] acpi/cppc: Add macros to define a R/W sysfs entry for CPPC registers Thread-Index: AQHU4O18kO2+2skZzkCsZd86zVVTZg== Date: Fri, 22 Mar 2019 20:26:10 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: a2adc2bb-55db-40d7-51cb-08d6af049eca x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600127)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2622; x-ms-traffictypediagnostic: SN6PR12MB2622: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(396003)(376002)(39860400002)(136003)(189003)(199004)(256004)(14444005)(2906002)(2501003)(50226002)(53936002)(8936002)(68736007)(52116002)(99286004)(6506007)(102836004)(386003)(26005)(110136005)(6436002)(118296001)(6486002)(6512007)(316002)(76176011)(36756003)(97736004)(11346002)(446003)(5660300002)(186003)(486006)(476003)(2616005)(71200400001)(71190400001)(14454004)(54906003)(478600001)(72206003)(6116002)(106356001)(105586002)(25786009)(2201001)(86362001)(81156014)(81166006)(3846002)(8676002)(66066001)(305945005)(7736002)(4326008);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2622;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:3; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ik2m6RhSw/+7OjYUrUMxnSNg4HGExSbgusBoeZLoLgYavly/TOPOayMFGh6JK+ZUzbXgq0UfK0AbqmGPA8odgY1KB92/ZObVU6A8Uv+IEQ9XYicLUBgC9M96H8R79iv6W5HZBcGa8SYP2e6JHzjh7zOmpMk3WmqXE1gUDrBbQM+EFey5dMy49gmz16YkVI/RNQjZfUluVWy+4ybRdk4NR28pYguxiKe4WrTiJ8aNgdip0cEFUxDUXg4dRR6psRtixS7WU5XaAYwqa/8W3kgsaym8cQ92BfSf3RNFLyNPncMf05IS2grB5jv5NZbtUggRhFGKerx6Cwp8dU/39W34TJAsNksTmc2R6ah9IybPdgJVd5qEv12F302a4cIur33GpPhVLsaPGO18GTh9HjhodE3o8/i7AE6Rf1/h9iAqQwI= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a2adc2bb-55db-40d7-51cb-08d6af049eca X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:26:10.1325 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2622 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam Some CPPC registers can be used to configure the platform. To enable this, create macros to define the show, store routines and create sysfs entries with R/W permission. Signed-off-by: Yazen Ghannam [ carved into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index e81c19316628..7cb23b369fc7 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -134,6 +134,10 @@ struct cppc_attr { static struct cppc_attr _name = \ __ATTR(_name, 0444, show_##_name, NULL) +#define define_one_cppc_rw(_name) \ +static struct cppc_attr _name = \ +__ATTR(_name, 0644, show_##_name, store_##_name) + #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj) #define show_cppc_data(access_fn, struct_name, member_name) \ @@ -156,6 +160,33 @@ __ATTR(_name, 0444, show_##_name, NULL) show_cppc_data(access_fn, struct_name, member_name) \ define_one_cppc_ro(member_name) +#define store_cppc_data(struct_name, member_name, reg_idx) \ + static ssize_t store_##member_name(struct kobject *kobj, \ + struct attribute *attr, \ + const char *c, ssize_t count)\ + { \ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \ + struct struct_name st_name = {0}; \ + u32 val; \ + int ret; \ + \ + ret = kstrtou32(c, 0, &val); \ + if (ret) \ + return ret; \ + \ + st_name.member_name = val; \ + \ + ret = cppc_set_reg(cpc_ptr->cpu_id, &st_name, reg_idx); \ + if (ret) \ + return ret; \ + \ + return count; \ + } \ + +#define store_cppc_data_rw(struct_name, member_name, reg_idx) \ + store_cppc_data(struct_name, member_name, reg_idx) \ + define_one_cppc_rw(member_name) + show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, highest_perf); show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, lowest_perf); show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_perf); From patchwork Fri Mar 22 20:26:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866499 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6084C139A for ; Fri, 22 Mar 2019 20:26:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 432A02A830 for ; Fri, 22 Mar 2019 20:26:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3792A2A835; Fri, 22 Mar 2019 20:26:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 784442A830 for ; Fri, 22 Mar 2019 20:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727192AbfCVU01 (ORCPT ); Fri, 22 Mar 2019 16:26:27 -0400 Received: from mail-eopbgr800072.outbound.protection.outlook.com ([40.107.80.72]:17312 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727102AbfCVU01 (ORCPT ); Fri, 22 Mar 2019 16:26:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qaQuMBa6XLXHy89VWDagjQPsQYQRTKSdqvrknx5rglQ=; b=d8iaJqYDkSwr2yTCajAU5Ip/XycmkApR9lTT/3gTi1COhvzQZGTQ/1xnWwlI5hHMK8wXoFgM3OHoUVuQiwaS3WCALJXDZzB51QLLDTVZO8Bz9fZLFpdobAtszkevHfIpQhI3VV1p5c33Fcs5mJzujEHLX7jCKNscbt/7VbOef8M= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2622.namprd12.prod.outlook.com (52.135.103.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1730.18; Fri, 22 Mar 2019 20:26:11 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::9584:f1be:656e:b00b%5]) with mapi id 15.20.1709.015; Fri, 22 Mar 2019 20:26:11 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH 5/6] acpi/cppc: Add support for optional CPPC registers Thread-Topic: [PATCH 5/6] acpi/cppc: Add support for optional CPPC registers Thread-Index: AQHU4O191UcWlpu2CUepblWSsE7ChA== Date: Fri, 22 Mar 2019 20:26:11 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 9f651e3c-4d92-4a0d-cdf3-08d6af049fa6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600127)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2622; x-ms-traffictypediagnostic: SN6PR12MB2622: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(396003)(376002)(39860400002)(136003)(189003)(199004)(256004)(14444005)(2906002)(2501003)(50226002)(53936002)(8936002)(68736007)(52116002)(99286004)(6506007)(102836004)(386003)(26005)(110136005)(6436002)(118296001)(6486002)(6512007)(316002)(76176011)(36756003)(97736004)(11346002)(446003)(5660300002)(186003)(486006)(476003)(2616005)(71200400001)(71190400001)(14454004)(54906003)(478600001)(72206003)(6116002)(106356001)(105586002)(25786009)(2201001)(86362001)(81156014)(81166006)(3846002)(8676002)(66066001)(305945005)(7736002)(4326008);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2622;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: U4P/bpNzUsI4cZ00P1/Kr1PyeNq+eKPBLDjBqDHjbGj4MpRQSBnnGn6iZCbbIe+Ab1erMdbMUIPSKTwOsnvE+X/BxkwHKejZhDSBZprAhiXqL4nuwHanRJFrPQkQn/x844/C7Cl+fMT2DunApCK30YdswMXQdIrTX91g+WAD5ljbyuFpZDQT1uzJqo+06A5RJuHwCGEUVrA+G5hxxGk6hUX3Hgyn8iXP23SNZru5ybyTWEsGyfrqzWLXkXyj7/p3fEmpFEsIGlbOfT2ytttW4HsXO5JR2ONo90zd0pDJl5m9wsJhzvt7G1Gnhtg6OwYtoIwOxRnfF93tsbPf/m95r1BlLwtWFgFNYbTHmt0JGFH1LdyLssZcPPMfAFIntb9wk1IAZVzJ7f6hTpNFgIv22EAgOaBGM4JghxJS3tsopK8= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f651e3c-4d92-4a0d-cdf3-08d6af049fa6 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:26:11.5534 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2622 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam Newer AMD processors support a subset of the optional CPPC registers. Create show, store and helper routines for supported CPPC registers. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 119 ++++++++++++++++++++++++++++++++++++--- include/acpi/cppc_acpi.h | 3 + 2 files changed, 114 insertions(+), 8 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7cb23b369fc7..f8827ba7015d 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -196,6 +196,17 @@ show_cppc_data_ro(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); show_cppc_data_ro(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, desired_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, max_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, min_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, energy_perf); +show_cppc_data(cppc_get_perf, cppc_perf_ctrls, auto_sel_enable); + +store_cppc_data_rw(cppc_perf_ctrls, desired_perf, DESIRED_PERF); +store_cppc_data_rw(cppc_perf_ctrls, max_perf, MAX_PERF); +store_cppc_data_rw(cppc_perf_ctrls, min_perf, MIN_PERF); +store_cppc_data_rw(cppc_perf_ctrls, energy_perf, ENERGY_PERF); +store_cppc_data_rw(cppc_perf_ctrls, auto_sel_enable, AUTO_SEL_ENABLE); static ssize_t show_feedback_ctrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -768,6 +779,21 @@ int set_cppc_attrs(struct cpc_desc *cpc, int entries) case CTR_WRAP_TIME: cppc_attrs[attr_i++] = &wraparound_time.attr; break; + case MAX_PERF: + cppc_attrs[attr_i++] = &max_perf.attr; + break; + case MIN_PERF: + cppc_attrs[attr_i++] = &min_perf.attr; + break; + case ENERGY_PERF: + cppc_attrs[attr_i++] = &energy_perf.attr; + break; + case AUTO_SEL_ENABLE: + cppc_attrs[attr_i++] = &auto_sel_enable.attr; + break; + case DESIRED_PERF: + cppc_attrs[attr_i++] = &desired_perf.attr; + break; } } @@ -1348,7 +1374,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); struct cppc_pcc_data *pcc_ss_data = NULL; struct cpc_register_resource *reg; - int ret = 0; + int ret = 0, regs_in_pcc = 0; u32 value; if (!cpc_desc) { @@ -1360,6 +1386,18 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, case DESIRED_PERF: value = perf_ctrls->desired_perf; break; + case MAX_PERF: + value = perf_ctrls->max_perf; + break; + case MIN_PERF: + value = perf_ctrls->min_perf; + break; + case ENERGY_PERF: + value = perf_ctrls->energy_perf; + break; + case AUTO_SEL_ENABLE: + value = perf_ctrls->auto_sel_enable; + break; default: pr_debug("CPC register index #%d not writeable\n", reg_idx); return -EINVAL; @@ -1375,6 +1413,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, * achieve that goal here */ if (CPC_IN_PCC(reg)) { + regs_in_pcc = 1; if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1397,13 +1436,10 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, cpc_desc->write_cmd_status = 0; } - /* - * Skip writing MIN/MAX until Linux knows how to come up with - * useful values. - */ - cpc_write(cpu, reg, value); + if (CPC_SUPPORTED(reg)) + cpc_write(cpu, reg, value); - if (CPC_IN_PCC(reg)) + if (regs_in_pcc) up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */ /* * This is Phase-II where we transfer the ownership of PCC to Platform @@ -1451,7 +1487,7 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, * case during a CMD_READ and if there are pending writes it delivers * the write command before servicing the read command */ - if (CPC_IN_PCC(reg)) { + if (regs_in_pcc) { if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */ /* Update only if there are pending write commands */ if (pcc_ss_data->pending_pcc_write_cmd) @@ -1469,6 +1505,73 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } EXPORT_SYMBOL_GPL(cppc_set_reg); +int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_reg, *max_reg, *min_reg; + struct cpc_register_resource *energy_reg, *auto_sel_enable_reg; + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + u64 desired, max, min, energy, auto_sel_enable; + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU: %d\n", cpu); + return -ENODEV; + } + + desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; + max_reg = &cpc_desc->cpc_regs[MAX_PERF]; + min_reg = &cpc_desc->cpc_regs[MIN_PERF]; + energy_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + auto_sel_enable_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(max_reg) || + CPC_IN_PCC(min_reg) || CPC_IN_PCC(energy_reg) || + CPC_IN_PCC(auto_sel_enable_reg)) { + pcc_ss_data = pcc_data[pcc_ss_id]; + down_write(&pcc_ss_data->pcc_lock); + regs_in_pcc = 1; + + /*Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + /* desired_perf is the only mandatory value in perf_ctrls */ + if (cpc_read(cpu, desired_reg, &desired)) + ret = -EFAULT; + + if (CPC_SUPPORTED(max_reg) && cpc_read(cpu, max_reg, &max)) + ret = -EFAULT; + + if (CPC_SUPPORTED(min_reg) && cpc_read(cpu, min_reg, &min)) + ret = -EFAULT; + + if (CPC_SUPPORTED(energy_reg) && cpc_read(cpu, energy_reg, &energy)) + ret = -EFAULT; + + if (CPC_SUPPORTED(auto_sel_enable_reg) && + cpc_read(cpu, auto_sel_enable_reg, &auto_sel_enable)) + ret = -EFAULT; + + if (!ret) { + perf_ctrls->desired_perf = desired; + perf_ctrls->max_perf = max; + perf_ctrls->min_perf = min; + perf_ctrls->energy_perf = energy; + perf_ctrls->auto_sel_enable = auto_sel_enable; + } + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf); + /** * cppc_get_transition_latency - returns frequency transition latency in ns * diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index ba3b3fb64572..6f651235933c 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -117,6 +117,8 @@ struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 auto_sel_enable; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -140,6 +142,7 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); +extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu); From patchwork Fri Mar 22 20:26:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 10866513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7703C1575 for ; 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Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCH 6/6] acpi/cppc: Add support for CPPC Enable register Thread-Topic: [PATCH 6/6] acpi/cppc: Add support for CPPC Enable register Thread-Index: AQHU4O1+ZZ1rK3k8pk25gNdSxHOghw== Date: Fri, 22 Mar 2019 20:26:13 +0000 Message-ID: <7e20fe2349bff1dc14c477c5bb456b8b1cde2994.1553285718.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0011.namprd02.prod.outlook.com (2603:10b6:803:2b::21) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d3638d4c-5296-4a31-f483-08d6af04a0cd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600127)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020);SRVR:SN6PR12MB2622; x-ms-traffictypediagnostic: SN6PR12MB2622: x-microsoft-antispam-prvs: x-forefront-prvs: 09840A4839 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(346002)(366004)(396003)(376002)(39860400002)(136003)(189003)(199004)(256004)(14444005)(2906002)(2501003)(50226002)(53936002)(8936002)(68736007)(52116002)(99286004)(6506007)(102836004)(386003)(26005)(110136005)(6436002)(118296001)(6486002)(6512007)(316002)(76176011)(36756003)(97736004)(11346002)(446003)(5660300002)(186003)(486006)(476003)(2616005)(71200400001)(71190400001)(14454004)(54906003)(478600001)(72206003)(6116002)(106356001)(105586002)(25786009)(2201001)(86362001)(81156014)(81166006)(3846002)(8676002)(66066001)(305945005)(7736002)(4326008);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2622;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: orpD4nw41RS7d13v3D6qbMBPni3ofo9DqZBboX1+tdumvxWTdmFRhYhkDQgs0ZzAhHOx2eb/u/3oPyCrns4aEAyHabwrh9RvqyclSbKZEoXec4R823Ers8IqZJNy85NT7pp+9wOikuQc3nlMzmbGCoK3Lm78em8Bf8Jkw0qXz4TKZkUrDVk3sBIizbWeinCq3Ms+LvQWDdO26DJBAI/osgaX2YZI2psdIcSwpPVZg45ha42jkiNvprUJ65ZnbQBbO0fVAGtj6oIqaUNgpKKlPPaUrOxywfDb+JRuHoIO8B3gXLAqrxd7y4zDYbK6EH3LmyQbBkfnXZZiE0eXv8T4fI31f1/ncNUVcuQMzHO79ia2v0PU85afFzmoujh/AxiaotCBQfti88BWRZpm76HxacTh7Hz4BGd4vbnsKEYLF8M= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d3638d4c-5296-4a31-f483-08d6af04a0cd X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Mar 2019 20:26:13.4817 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2622 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam To enable CPPC on a processor, the OS should write a value "1" to the CPPC Enable register. Add support for this register. Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 96 ++++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 1 + 2 files changed, 97 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index f8827ba7015d..8c6804976bb8 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -224,6 +224,43 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, } define_one_cppc_ro(feedback_ctrs); +/* Used to move ENABLE register value between userspace and platform */ +static bool cppc_cpu_enable; + +static ssize_t show_enable(struct kobject *kobj, + struct attribute *attr, + char *buf) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + int ret; + + ret = cppc_get_enable(cpc_ptr->cpu_id); + if (ret) + return ret; + + return scnprintf(buf, PAGE_SIZE, "%d\n", cppc_cpu_enable); +} + +static ssize_t store_enable(struct kobject *kobj, + struct attribute *attr, + const char *c, ssize_t count) +{ + struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); + int ret; + + ret = kstrtobool(c, &cppc_cpu_enable); + if (ret) + return ret; + + ret = cppc_set_reg(cpc_ptr->cpu_id, NULL, ENABLE); + if (ret) + return ret; + + return count; +} + +define_one_cppc_rw(enable); + static struct kobj_type cppc_ktype = { .sysfs_ops = &kobj_sysfs_ops, }; @@ -794,6 +831,9 @@ int set_cppc_attrs(struct cpc_desc *cpc, int entries) case DESIRED_PERF: cppc_attrs[attr_i++] = &desired_perf.attr; break; + case ENABLE: + cppc_attrs[attr_i++] = &enable.attr; + break; } } @@ -1383,6 +1423,9 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } switch (reg_idx) { + case ENABLE: + value = cppc_cpu_enable; + break; case DESIRED_PERF: value = perf_ctrls->desired_perf; break; @@ -1572,6 +1615,59 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } EXPORT_SYMBOL_GPL(cppc_get_perf); +/** + * cppc_get_enable - Read a CPUs enable register. + * @cpu: CPU from which to read control values. + * + * Return: 0 for success. + */ +int cppc_get_enable(int cpu) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *enable_reg; + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0, regs_in_pcc = 0; + u64 enable; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU: %d\n", cpu); + return -ENODEV; + } + + enable_reg = &cpc_desc->cpc_regs[ENABLE]; + + if (!CPC_SUPPORTED(enable_reg)) { + pr_warn("CPC ENABLE register not supported.\n"); + return -ENOTSUPP; + } + + if (CPC_IN_PCC(enable_reg)) { + pcc_ss_data = pcc_data[pcc_ss_id]; + down_write(&pcc_ss_data->pcc_lock); + regs_in_pcc = 1; + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret = -EIO; + goto out_err; + } + } + + if (cpc_read(cpu, enable_reg, &enable)) { + ret = -EFAULT; + goto out_err; + } + + cppc_cpu_enable = enable; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_enable); + /** * cppc_get_transition_latency - returns frequency transition latency in ns * diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6f651235933c..fcdedff8e6bd 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { cpumask_var_t shared_cpu_map; }; +extern int cppc_get_enable(int cpu); extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx);