From patchwork Mon Mar 25 11:01:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 096941669 for ; Mon, 25 Mar 2019 11:08:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8ACD292AA for ; Mon, 25 Mar 2019 11:08:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DCD5D2930D; Mon, 25 Mar 2019 11:08:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 469C3292AA for ; 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Mon, 25 Mar 2019 12:02:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511740; bh=fim3p4zmaf3aFDPE3gcaY2aoXqpm/15izlSUkLSkHAQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=kOO+0ut1cFqycEDJ6vqpimJmGfOG3IYNfzvxVd/Q/82GrLI2Jy+fEzLgt77O8h5Qw nLyhAwhgffBFLMCoatU1s7OwjZP7X2+VaaDsYufpk/o7tEuqBqxyaUnW5iBwltni+t 2cr4y7TbAhNJ4s+mTdAyd150N1Kr40h53OIXZv2U= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:44 +0100 Message-Id: <19e6624397deb68db77526a8d25be42aafb3373e.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 01/17] Create Resettable QOM interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This commit defines an interface allowing multi-phase reset. The phases are INIT, HOLD and EXIT. The reset of a Resettable is controlled with 2 functions: - resettable_assert_reset which starts the reset operation. - resettable_deassert_reset which ends the reset operation. There is also a `resettable_reset` helper function which does assert then deassert allowing to do a proper reset in one call. The interface only contains 3 methods, one per phase. Each method should handle reset of the object and its sub-elements. Signed-off-by: Damien Hedde --- hw/core/Makefile.objs | 1 + hw/core/resettable.c | 69 ++++++++++++++++++++++++++++++++++ include/hw/resettable.h | 83 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 153 insertions(+) create mode 100644 hw/core/resettable.c create mode 100644 include/hw/resettable.h diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index a799c83815..97007454a8 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -1,6 +1,7 @@ # core qdev-related obj files, also used by *-user: common-obj-y += qdev.o qdev-properties.o common-obj-y += bus.o reset.o +common-obj-y += resettable.o common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o # irq.o needed for qdev GPIO handling: diff --git a/hw/core/resettable.c b/hw/core/resettable.c new file mode 100644 index 0000000000..6ea1e5b54a --- /dev/null +++ b/hw/core/resettable.c @@ -0,0 +1,69 @@ +/* + * Resettable interface. + * + * Copyright (c) 2019 GreenSocs SAS + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "hw/resettable.h" + +#define RESETTABLE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ResettableClass, (obj), TYPE_RESETTABLE) + +void resettable_init_phase(Object *obj, bool cold) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + + if (rc->phases.init) { + rc->phases.init(obj, cold); + } +} + +void resettable_hold_phase(Object *obj) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + + if (rc->phases.hold) { + rc->phases.hold(obj); + } +} + +void resettable_exit_phase(Object *obj) +{ + ResettableClass *rc = RESETTABLE_GET_CLASS(obj); + + if (rc->phases.exit) { + rc->phases.exit(obj); + } +} + +void resettable_assert_reset(Object *obj, bool cold) +{ + resettable_init_phase(obj, cold); + resettable_hold_phase(obj); +} + +void resettable_deassert_reset(Object *obj) +{ + resettable_exit_phase(obj); +} + +static const TypeInfo resettable_interface_info = { + .name = TYPE_RESETTABLE, + .parent = TYPE_INTERFACE, + .class_size = sizeof(ResettableClass), +}; + +static void reset_register_types(void) +{ + type_register_static(&resettable_interface_info); +} + +type_init(reset_register_types) diff --git a/include/hw/resettable.h b/include/hw/resettable.h new file mode 100644 index 0000000000..15d5bd878d --- /dev/null +++ b/include/hw/resettable.h @@ -0,0 +1,83 @@ +#ifndef HW_RESETTABLE_H +#define HW_RESETTABLE_H + +#include "qom/object.h" + +#define TYPE_RESETTABLE "resettable" + +#define RESETTABLE_CLASS(class) \ + OBJECT_CLASS_CHECK(ResettableClass, (class), TYPE_RESETTABLE) + +/* + * ResettableClass: + * Interface for resettable objects. + * + * The reset operation is divided in several phases each represented by a + * method. + * + * @phases.init: should reset local state only. Takes a bool @cold argument + * specifying whether the reset is cold or warm. It must not do side-effect + * on others objects. + * + * @phases.hold: side-effects action on others objects due to staying in a + * resetting state. + * + * @phases.exit: leave the reset state, may do side-effects action on others + * objects. + * + * "Entering the reset state" corresponds to the init and hold phases. + * "Leaving the reset state" corresponds to the exit phase. + */ +typedef void (*ResettableInitPhase)(Object *obj, bool cold); +typedef void (*ResettableHoldPhase)(Object *obj); +typedef void (*ResettableExitPhase)(Object *obj); +typedef struct ResettableClass { + InterfaceClass parent_class; + + struct ResettablePhases { + ResettableInitPhase init; + ResettableHoldPhase hold; + ResettableExitPhase exit; + } phases; +} ResettableClass; +typedef struct ResettablePhases ResettablePhases; + +/* + * Helpers to do a single phase of a Resettable. + * Call the corresponding ResettableClass method if it is not NULL. + */ +void resettable_init_phase(Object *obj, bool cold); +void resettable_hold_phase(Object *obj); +void resettable_exit_phase(Object *obj); + +/** + * resettable_assert_reset: + * Put an object in reset state. + * Each time resettable_assert_reset is called, resettable_deassert_reset + * must be eventually called once and only once. + * + * @obj object to reset, must implement Resettable interface. + * @cold boolean indicating the type of reset (cold or warm) + */ +void resettable_assert_reset(Object *obj, bool cold); + +/** + * resettable_deassert_reset: + * End the reset state if an object. + * + * @obj object to reset, must implement Resettable interface. + */ +void resettable_deassert_reset(Object *obj); + +/** + * resettable_reset: + * Calling this function is equivalent to call @assert_reset then + * @deassert_reset. + */ +static inline void resettable_reset(Object *obj, bool cold) +{ + resettable_assert_reset(obj, cold); + resettable_deassert_reset(obj); +} + +#endif From patchwork Mon Mar 25 11:01:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868813 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8088613B5 for ; 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Mon, 25 Mar 2019 12:02:20 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511741; bh=cBDNrVqzCnOtTlIzkEFIk84dWfLcrkL6ZiPFit50ywU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=agz82TQJJzW0VqXNBnQTRbch5BntogXBurtTTH79j9LxOHny78kCqT8ptyla47RoX k8USRz3XisL3w4dDaW0gATWUWRB/IT4bR/PkQRkCYZw1fztMwm0b0o+4rnNIaJoI1z k2SGamHA4cWagVwK/2uCSEx0W9Tdcf3RpBYnd9DI= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:45 +0100 Message-Id: <60e1f016cfd490b733aa649bbdc8723cdd1fd6b1.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 02/17] Create the ResetDomain QOM object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP ResetDomain is an object implementing the Resettable interface. It is a container of several other Resettable and therefore allows to control reset operation over a group of Resettable. Addition and removal in a ResetDomain is done using the functions *reset_domain_register_object* and *reset_domain_unregister_object* Signed-off-by: Damien Hedde --- hw/core/Makefile.objs | 1 + hw/core/reset-domain.c | 121 ++++++++++++++++++++++++++++++++++++++ include/hw/reset-domain.h | 49 +++++++++++++++ 3 files changed, 171 insertions(+) create mode 100644 hw/core/reset-domain.c create mode 100644 include/hw/reset-domain.h diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 97007454a8..320f71707c 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -2,6 +2,7 @@ common-obj-y += qdev.o qdev-properties.o common-obj-y += bus.o reset.o common-obj-y += resettable.o +common-obj-y += reset-domain.o common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o # irq.o needed for qdev GPIO handling: diff --git a/hw/core/reset-domain.c b/hw/core/reset-domain.c new file mode 100644 index 0000000000..b701eb5bdd --- /dev/null +++ b/hw/core/reset-domain.c @@ -0,0 +1,121 @@ +/* + * Reset Domain object. + * + * Copyright (c) 2019 GreenSocs + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/module.h" +#include "hw/reset-domain.h" + +void reset_domain_register_object(ResetDomain *domain, Object *obj) +{ + struct ResetDomainEntry *rde; + + INTERFACE_CHECK(ResettableClass, obj, TYPE_RESETTABLE); + + rde = g_malloc0(sizeof(*rde)); + rde->obj = obj; + object_ref(obj); + QLIST_INSERT_HEAD(&domain->members, rde, node); +} + +void reset_domain_unregister_object(ResetDomain *domain, Object *obj) +{ + struct ResetDomainEntry *rde; + + INTERFACE_CHECK(ResettableClass, obj, TYPE_RESETTABLE); + + QLIST_FOREACH(rde, &domain->members, node) { + if (rde->obj == obj) { + QLIST_REMOVE(rde, node); + object_unref(rde->obj); + g_free(rde); + return; + } + } +} + +static void reset_domain_init_phase(Object *obj, bool cold) +{ + struct ResetDomainEntry *rde; + ResetDomain *domain = RESET_DOMAIN(obj); + + QLIST_FOREACH(rde, &domain->members, node) { + resettable_init_phase(rde->obj, cold); + } +} + +static void reset_domain_hold_phase(Object *obj) +{ + struct ResetDomainEntry *rde; + ResetDomain *domain = RESET_DOMAIN(obj); + + QLIST_FOREACH(rde, &domain->members, node) { + resettable_hold_phase(rde->obj); + } +} + +static void reset_domain_exit_phase(Object *obj) +{ + struct ResetDomainEntry *rde; + ResetDomain *domain = RESET_DOMAIN(obj); + + QLIST_FOREACH(rde, &domain->members, node) { + resettable_exit_phase(rde->obj); + } +} + +static void reset_domain_init(Object *obj) +{ + ResetDomain *domain = RESET_DOMAIN(obj); + + QLIST_INIT(&domain->members); +} + +static void reset_domain_finalize(Object *obj) +{ + ResetDomain *domain = RESET_DOMAIN(obj); + struct ResetDomainEntry *rde, *nrde; + + QLIST_FOREACH_SAFE(rde, &domain->members, node, nrde) { + QLIST_REMOVE(rde, node); + object_unref(rde->obj); + g_free(rde); + } +} + +static void reset_domain_class_init(ObjectClass *class, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(class); + + rc->phases.init = reset_domain_init_phase; + rc->phases.hold = reset_domain_hold_phase; + rc->phases.exit = reset_domain_exit_phase; +} + +static const TypeInfo reset_domain_type_info = { + .name = TYPE_RESET_DOMAIN, + .parent = TYPE_OBJECT, + .instance_size = sizeof(ResetDomain), + .instance_init = reset_domain_init, + .instance_finalize = reset_domain_finalize, + .class_init = reset_domain_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_RESETTABLE }, + { } + }, +}; + +static void reset_register_types(void) +{ + type_register_static(&reset_domain_type_info); +} + +type_init(reset_register_types) diff --git a/include/hw/reset-domain.h b/include/hw/reset-domain.h new file mode 100644 index 0000000000..03b3a981de --- /dev/null +++ b/include/hw/reset-domain.h @@ -0,0 +1,49 @@ +#ifndef HW_RESET_DOMAIN_H +#define HW_RESET_DOMAIN_H + +#include "resettable.h" +#include "qemu/queue.h" + +#define TYPE_RESET_DOMAIN "reset-domain" + +#define RESET_DOMAIN(obj) OBJECT_CHECK(ResetDomain, (obj), TYPE_RESET_DOMAIN) + +/** + * ResetDomainClass: + * A ResetDomain holds several Resettable objects and implement the Resettable + * interface too. + * Doing a reset on it will also reset all objects it contained. Phases of + * every object will be executed in order: init_reset of all objects first, etc. + */ +typedef ObjectClass ResetDomainClass; + +/** + * ResetDomain: + * @members is a list of ResetDomainEntry. Every entry hold a pointer to a + * Resettable object. + * To avoid object to disapear while in the ResetDomain, the ResetDomain + * increases the refcount. + */ +struct ResetDomainEntry { + Object *obj; + QLIST_ENTRY(ResetDomainEntry) node; +}; +typedef struct ResetDomain { + Object parent_obj; + + QLIST_HEAD(, ResetDomainEntry) members; +} ResetDomain; + +/** + * reset_domain_register_objet: + * Register the Resettable object @obj into a ResetDomain @domain. + */ +void reset_domain_register_object(ResetDomain *domain, Object *obj); + +/** + * reset_domain_unregister_objet: + * Unregister the Resettable object @obj into a ResetDomain @domain. + */ +void reset_domain_unregister_object(ResetDomain *domain, Object *obj); + +#endif From patchwork Mon Mar 25 11:01:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868805 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E8B2513B5 for ; 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Mon, 25 Mar 2019 12:02:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511741; bh=YlmXDRZ1/RrwO+VhpRtYBJW25XnBqeYAw6/iPWTZaEI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UEWuR/rwKbG2FEXTXmDoDSDw+f4c1jqgQyLfM77RKIHppk0CyLvcyo+x/t8JA6zTi g8T2mgTtHnY3vl4xtosxcmzaBP+RppWm8CL78cmsQfkQT1Q4vZbTG522xvOrUMcJdQ LNSvVVOi9idkoFxXS/CInC5IXFELQb+aGzdFFn9Q= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:46 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 03/17] make Device and Bus Resettable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This add Resettable interface implementation for both Bus and Device. The init phase default implementation is to call the legacy reset handler. Add a *resetting* counter in both Device and Bus. This counter allows us to handle reentrancy in reset operation. If a device/bus has multiple source triggering reset, theses sources do not have to care about the current device/bus resetting state. Each source can independantly assert and eventually deassert the reset. The device/bus will behave as expected and gets out-of-reset state only when all sources have deasserted the reset. Signed-off-by: Damien Hedde --- hw/core/bus.c | 60 +++++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 61 ++++++++++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 30 +++++++++++++++++++++ 3 files changed, 151 insertions(+) diff --git a/hw/core/bus.c b/hw/core/bus.c index e09843f6ab..0a60bb4b24 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -21,6 +21,7 @@ #include "qemu-common.h" #include "hw/qdev.h" #include "qapi/error.h" +#include "hw/resettable.h" void qbus_set_hotplug_handler(BusState *bus, Object *handler, Error **errp) { @@ -67,6 +68,56 @@ int qbus_walk_children(BusState *bus, return 0; } +void qbus_reset(BusState *bus, bool cold) +{ + resettable_reset(OBJECT(bus), cold); +} + +bool qbus_is_resetting(BusState *bus) +{ + return (bus->resetting != 0); +} + +static void bus_reset_init_phase(Object *obj, bool cold) +{ + BusState *bus = BUS(obj); + BusClass *bc = BUS_GET_CLASS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + resettable_init_phase(OBJECT(kid->child), cold); + } + + bus->resetting += 1; + + if (bc->reset) { + bc->reset(bus); + } +} + +static void bus_reset_hold_phase(Object *obj) +{ + BusState *bus = BUS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + resettable_hold_phase(OBJECT(kid->child)); + } +} + +static void bus_reset_exit_phase(Object *obj) +{ + BusState *bus = BUS(obj); + BusChild *kid; + + QTAILQ_FOREACH(kid, &bus->children, sibling) { + resettable_exit_phase(OBJECT(kid->child)); + } + + assert(bus->resetting > 0); + bus->resetting -= 1; +} + static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) { const char *typename = object_get_typename(OBJECT(bus)); @@ -204,9 +255,14 @@ static char *default_bus_get_fw_dev_path(DeviceState *dev) static void bus_class_init(ObjectClass *class, void *data) { BusClass *bc = BUS_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = bus_unparent; bc->get_fw_dev_path = default_bus_get_fw_dev_path; + + rc->phases.init = bus_reset_init_phase; + rc->phases.hold = bus_reset_hold_phase; + rc->phases.exit = bus_reset_exit_phase; } static void qbus_finalize(Object *obj) @@ -225,6 +281,10 @@ static const TypeInfo bus_info = { .instance_init = qbus_initfn, .instance_finalize = qbus_finalize, .class_init = bus_class_init, + .interfaces = (InterfaceInfo[]) { + { TYPE_RESETTABLE }, + { } + }, }; static void bus_register_types(void) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index f9b6efe509..98d173f34f 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -37,6 +37,7 @@ #include "hw/hotplug.h" #include "hw/boards.h" #include "hw/sysbus.h" +#include "hw/resettable.h" bool qdev_hotplug = false; static bool qdev_hot_added = false; @@ -254,6 +255,56 @@ HotplugHandler *qdev_get_hotplug_handler(DeviceState *dev) return hotplug_ctrl; } +void qdev_reset(DeviceState *dev, bool cold) +{ + resettable_reset(OBJECT(dev), cold); +} + +bool qdev_is_resetting(DeviceState *dev) +{ + return (dev->resetting != 0); +} + +static void device_reset_init_phase(Object *obj, bool cold) +{ + DeviceState *dev = DEVICE(obj); + DeviceClass *dc = DEVICE_GET_CLASS(obj); + BusState *child; + + QLIST_FOREACH(child, &dev->child_bus, sibling) { + resettable_init_phase(OBJECT(child), cold); + } + + dev->resetting += 1; + + if (dc->reset) { + dc->reset(dev); + } +} + +static void device_reset_hold_phase(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + BusState *child; + + QLIST_FOREACH(child, &dev->child_bus, sibling) { + resettable_hold_phase(OBJECT(child)); + } +} + +static void device_reset_exit_phase(Object *obj) +{ + DeviceState *dev = DEVICE(obj); + BusState *child; + + QLIST_FOREACH(child, &dev->child_bus, sibling) { + resettable_exit_phase(OBJECT(child)); + } + + assert(dev->resetting > 0); + dev->resetting -= 1; +} + static int qdev_reset_one(DeviceState *dev, void *opaque) { device_reset(dev); @@ -954,6 +1005,7 @@ static void device_initfn(Object *obj) dev->instance_id_alias = -1; dev->realized = false; + dev->resetting = 0; object_property_add_bool(obj, "realized", device_get_realized, device_set_realized, NULL); @@ -1049,6 +1101,7 @@ static void device_unparent(Object *obj) static void device_class_init(ObjectClass *class, void *data) { DeviceClass *dc = DEVICE_CLASS(class); + ResettableClass *rc = RESETTABLE_CLASS(class); class->unparent = device_unparent; @@ -1060,6 +1113,10 @@ static void device_class_init(ObjectClass *class, void *data) */ dc->hotpluggable = true; dc->user_creatable = true; + + rc->phases.init = device_reset_init_phase; + rc->phases.hold = device_reset_hold_phase; + rc->phases.exit = device_reset_exit_phase; } void device_class_set_parent_reset(DeviceClass *dc, @@ -1117,6 +1174,10 @@ static const TypeInfo device_type_info = { .class_init = device_class_init, .abstract = true, .class_size = sizeof(DeviceClass), + .interfaces = (InterfaceInfo[]) { + { TYPE_RESETTABLE }, + { } + }, }; static void qdev_register_types(void) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 33ed3b8dde..f4aa8dbaa2 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -131,6 +131,8 @@ struct NamedGPIOList { /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. + * @resetting: Indicates whether the device is under reset. Also + * used to count how many times reset has been initiated on the device. * * This structure should not be accessed directly. We declare it here * so that it can be embedded in individual device state structures. @@ -152,6 +154,7 @@ struct DeviceState { int num_child_bus; int instance_id_alias; int alias_required_for_version; + uint32_t resetting; }; struct DeviceListener { @@ -198,6 +201,8 @@ typedef struct BusChild { /** * BusState: * @hotplug_handler: link to a hotplug handler associated with bus. + * @resetting: Indicates whether the device is under reset. Also + * used to count how many times reset has been initiated on the device. */ struct BusState { Object obj; @@ -209,6 +214,7 @@ struct BusState { int num_children; QTAILQ_HEAD(, BusChild) children; QLIST_ENTRY(BusState) sibling; + uint32_t resetting; }; /** @@ -378,6 +384,30 @@ int qdev_walk_children(DeviceState *dev, qdev_walkerfn *post_devfn, qbus_walkerfn *post_busfn, void *opaque); +/** + * @qdev_reset: + * Reset the device @dev, @cold tell whether to do a cold or warm reset. + */ +void qdev_reset(DeviceState *dev, bool cold); + +/** + * @qbus_reset: + * Reset the bus @bus, @cold tell whether to do a cold or warm reset. + */ +void qbus_reset(BusState *bus, bool cold); + +/** + * @qdev_is_resetting: + * Tell whether the device @dev is currently under reset. + */ +bool qdev_is_resetting(DeviceState *dev); + +/** + * @qbus_is_resetting: + * Tell whether the bus @bus is currently under reset. + */ +bool qbus_is_resetting(BusState *bus); + void qdev_reset_all(DeviceState *dev); void qdev_reset_all_fn(void *opaque); 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Mon, 25 Mar 2019 12:02:21 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511742; bh=4rCBKop/jhXKENgGNrYN0iCn8CMt31D2QPxCOMlalak=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LYUcHioC3epGowhEusABOmhAfvGtmgO0L4yu3RDPuUJSqdl15NEbFg+kZ/oNz48eO IaWqSosIkmy2O/3aquqvs4Y+2yQ8qcSPQc/AVEgOvovioWEivNy1Sgw24wLLCNkhvw HoX0vrVC/ZkqE+D+3iZMiHsK+tCWkAyRdycL1lGg= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:47 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 04/17] Add local reset methods in Device class X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add 3 methods in device class corresponding to the local part of the 3-phases reset. This allows specialization classes not to care about the ressetting counter and sub-buses. The exit phase method is called only if resetting counter hits 0. Also, these methods are called in `device_reset`. Specializations can switch from the single-phase reset to the 3-phases reset with no effects on the `device_reset` behavior. Signed-off-by: Damien Hedde --- hw/core/qdev.c | 44 ++++++++++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 17 ++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 98d173f34f..884a49efa4 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -280,21 +280,30 @@ static void device_reset_init_phase(Object *obj, bool cold) if (dc->reset) { dc->reset(dev); } + if (dc->reset_phases.init) { + dc->reset_phases.init(OBJECT(dev), cold); + } } static void device_reset_hold_phase(Object *obj) { DeviceState *dev = DEVICE(obj); + DeviceClass *dc = DEVICE_GET_CLASS(obj); BusState *child; QLIST_FOREACH(child, &dev->child_bus, sibling) { resettable_hold_phase(OBJECT(child)); } + + if (dc->reset_phases.hold) { + dc->reset_phases.hold(OBJECT(dev)); + } } static void device_reset_exit_phase(Object *obj) { DeviceState *dev = DEVICE(obj); + DeviceClass *dc = DEVICE_GET_CLASS(obj); BusState *child; QLIST_FOREACH(child, &dev->child_bus, sibling) { @@ -303,6 +312,12 @@ static void device_reset_exit_phase(Object *obj) assert(dev->resetting > 0); dev->resetting -= 1; + + if (dev->resetting == 0) { + if (dc->reset_phases.exit) { + dc->reset_phases.exit(OBJECT(dev)); + } + } } static int qdev_reset_one(DeviceState *dev, void *opaque) @@ -1143,6 +1158,24 @@ void device_class_set_parent_unrealize(DeviceClass *dc, dc->unrealize = dev_unrealize; } +void device_class_set_parent_reset_phases(DeviceClass *dc, + ResettableInitPhase dev_reset_init, + ResettableHoldPhase dev_reset_hold, + ResettableExitPhase dev_reset_exit, + ResettablePhases *parent_phases) +{ + *parent_phases = dc->reset_phases; + if (dev_reset_init) { + dc->reset_phases.init = dev_reset_init; + } + if (dev_reset_hold) { + dc->reset_phases.hold = dev_reset_hold; + } + if (dev_reset_exit) { + dc->reset_phases.exit = dev_reset_exit; + } +} + void device_reset(DeviceState *dev) { DeviceClass *klass = DEVICE_GET_CLASS(dev); @@ -1150,6 +1183,17 @@ void device_reset(DeviceState *dev) if (klass->reset) { klass->reset(dev); } + dev->resetting += 1; + if (klass->reset_phases.init) { + klass->reset_phases.init(OBJECT(dev), false); + } + if (klass->reset_phases.hold) { + klass->reset_phases.hold(OBJECT(dev)); + } + dev->resetting -= 1; + if (klass->reset_phases.exit) { + klass->reset_phases.exit(OBJECT(dev)); + } } Object *qdev_get_machine(void) diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index f4aa8dbaa2..0ef4d6c920 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -6,6 +6,7 @@ #include "qom/object.h" #include "hw/irq.h" #include "hw/hotplug.h" +#include "hw/resettable.h" enum { DEV_NVECTORS_UNSPECIFIED = -1, @@ -110,6 +111,7 @@ typedef struct DeviceClass { DeviceReset reset; DeviceRealize realize; DeviceUnrealize unrealize; + ResettablePhases reset_phases; /* device state */ const struct VMStateDescription *vmsd; @@ -455,6 +457,21 @@ void device_class_set_parent_unrealize(DeviceClass *dc, DeviceUnrealize dev_unrealize, DeviceUnrealize *parent_unrealize); +/** + * @device_class_set_parent_reset_phases: + * + * Save @dc current reset phases into @parent_phases and override @dc phases + * by the given new methods (@dev_reset_init, @dev_reset_hold and + * @dev_reset_exit). + * Each phase is overriden only if the new one is not NULL allowing to + * override a subset of phases. + */ +void device_class_set_parent_reset_phases(DeviceClass *dc, + ResettableInitPhase dev_reset_init, + ResettableHoldPhase dev_reset_hold, + ResettableExitPhase dev_reset_exit, + ResettablePhases *parent_phases); + const struct VMStateDescription *qdev_get_vmsd(DeviceState *dev); const char *qdev_fw_name(DeviceState *dev); From patchwork Mon Mar 25 11:01:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 506B513B5 for ; Mon, 25 Mar 2019 11:09:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 377AA291B4 for ; Mon, 25 Mar 2019 11:09:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24DAA29259; Mon, 25 Mar 2019 11:09:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B3161291B4 for ; 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Mon, 25 Mar 2019 12:02:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511742; bh=pK9FJbNdoyI0VAz9RM6Oo8TYJ2N+7i+dGeRy4KKzNO0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BQPwbnrL7viIukwx4WlVPAEeaKRRSJiu5LibDCyuDl1E1KbQ+ululT+1uTAXxL39u YqO9nWa7G7aBTsS4J7nf9OZBH60w47g3BrNb+Hn+oopdj+7UpJBbxTa7c9zxvhjaaC gLlmIusExZvYblu5DbfGQBWIkClNGLJzA7AS1w7w= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:48 +0100 Message-Id: <11cf0b4f9c333696f462753c47dc71641717fb08.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 05/17] add vmstate description for device reset state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The `device_vmstate_reset` can be added by device specialization, as vmsd subsection, to migrate the reset related device state part. Signed-off-by: Damien Hedde --- hw/core/Makefile.objs | 1 + hw/core/qdev-vmstate.c | 25 +++++++++++++++++++++++++ include/hw/qdev-core.h | 6 ++++++ 3 files changed, 32 insertions(+) create mode 100644 hw/core/qdev-vmstate.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 320f71707c..562cf1034e 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -5,6 +5,7 @@ common-obj-y += resettable.o common-obj-y += reset-domain.o common-obj-$(CONFIG_SOFTMMU) += qdev-fw.o common-obj-$(CONFIG_SOFTMMU) += fw-path-provider.o +common-obj-$(CONFIG_SOFTMMU) += qdev-vmstate.o # irq.o needed for qdev GPIO handling: common-obj-y += irq.o common-obj-y += hotplug.o diff --git a/hw/core/qdev-vmstate.c b/hw/core/qdev-vmstate.c new file mode 100644 index 0000000000..a9834f1a1c --- /dev/null +++ b/hw/core/qdev-vmstate.c @@ -0,0 +1,25 @@ +/* + * Device vmstate + * + * Copyright (c) 2019 GreenSocs + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/qdev.h" +#include "migration/vmstate.h" + +const struct VMStateDescription device_vmstate_reset = { + .name = "device_reset", + .version_id = 0, + .minimum_version_id = 0, + .fields = (VMStateField[]) { + VMSTATE_UINT32(resetting, DeviceState), + VMSTATE_END_OF_LIST() + } +}; diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 0ef4d6c920..baad2e7066 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -500,4 +500,10 @@ static inline bool qbus_is_hotpluggable(BusState *bus) void device_listener_register(DeviceListener *listener); void device_listener_unregister(DeviceListener *listener); +/** + * device_vmstate_reset: + * vmstate entry for reset related state + */ +extern const struct VMStateDescription device_vmstate_reset; + #endif From patchwork Mon Mar 25 11:01:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868801 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5682D13B5 for ; Mon, 25 Mar 2019 11:05:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 42191290BA for ; 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Mon, 25 Mar 2019 12:02:22 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511743; bh=clq3gvkosMEvBafp8I7Dl74ggYCNhXMTvzQ/+rm5LXM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UUfytm+MquilzR9zQJ7NG1FEinwlC8TA2ikP0pkoXNILexKX/N+6yt1mEwV46sHrr Thh+DeaRSvDh9SY4g2PXHIWrouFC1HrkCL4cR5ispjqfdILBzFso6w0Q6bIbpVFR+B QfWTM8rdROdDTm/pLkJ/iS5ss1j3ZywxxzLRSVmQ= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:49 +0100 Message-Id: <5a0f7fc13cd69586dba5475edf5a6bec46559858.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 06/17] Add function to control reset with gpio inputs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP It adds the possibility to add 2 gpios to control the warm and cold reset. With theses ios, the reset can be maintained during some time. Each io is associated with a state to detect level changes. The cold reset io function is named power_gate as it is really the meaning of this io. Signed-off-by: Damien Hedde --- hw/core/qdev-vmstate.c | 2 ++ hw/core/qdev.c | 57 ++++++++++++++++++++++++++++++++++++++++++ include/hw/qdev-core.h | 44 ++++++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/hw/core/qdev-vmstate.c b/hw/core/qdev-vmstate.c index a9834f1a1c..dec6a72f75 100644 --- a/hw/core/qdev-vmstate.c +++ b/hw/core/qdev-vmstate.c @@ -20,6 +20,8 @@ const struct VMStateDescription device_vmstate_reset = { .minimum_version_id = 0, .fields = (VMStateField[]) { VMSTATE_UINT32(resetting, DeviceState), + VMSTATE_BOOL(cold_reset_input.state, DeviceState), + VMSTATE_BOOL(warm_reset_input.state, DeviceState), VMSTATE_END_OF_LIST() } }; diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 884a49efa4..8dae26d957 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -464,6 +464,61 @@ void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n) qdev_init_gpio_in_named(dev, handler, NULL, n); } +static void device_reset_handler(DeviceState *dev, bool cold, bool level) +{ + DeviceResetInputState *dris; + + dris = cold ? &dev->cold_reset_input : &dev->warm_reset_input; + + if (level == dris->state) { + /* io state has not changed */ + return; + } + + dris->state = level; + switch (dris->type) { + case DEVICE_ACTIVE_LOW: + level = !level; + case DEVICE_ACTIVE_HIGH: + if (level) { + resettable_assert_reset(OBJECT(dev), cold); + } else { + resettable_deassert_reset(OBJECT(dev)); + } + break; + } +} + +static void device_cold_reset_handler(void *opaque, int n, int level) +{ + device_reset_handler((DeviceState *) opaque, true, level); +} + +static void device_warm_reset_handler(void *opaque, int n, int level) +{ + device_reset_handler((DeviceState *) opaque, false, level); +} + +void qdev_init_reset_gpio_in_named(DeviceState *dev, const char *name, + bool cold, DeviceActiveType type) +{ + qemu_irq_handler handler; + + if (cold) { + assert(!dev->cold_reset_input.exists); + dev->cold_reset_input.exists = true; + dev->cold_reset_input.type = type; + handler = device_cold_reset_handler; + } else { + assert(!dev->warm_reset_input.exists); + dev->warm_reset_input.exists = true; + dev->warm_reset_input.type = type; + handler = device_warm_reset_handler; + } + + qdev_init_gpio_in_named(dev, handler, name, 1); +} + void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins, const char *name, int n) { @@ -1021,6 +1076,8 @@ static void device_initfn(Object *obj) dev->instance_id_alias = -1; dev->realized = false; dev->resetting = 0; + dev->cold_reset_input.exists = false; + dev->warm_reset_input.exists = false; object_property_add_bool(obj, "realized", device_get_realized, device_set_realized, NULL); diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index baad2e7066..db997cc47d 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -130,6 +130,17 @@ struct NamedGPIOList { QLIST_ENTRY(NamedGPIOList) node; }; +typedef enum DeviceActiveType { + DEVICE_ACTIVE_LOW, + DEVICE_ACTIVE_HIGH, +} DeviceActiveType; + +typedef struct DeviceResetInputState { + bool exists; + DeviceActiveType type; + bool state; +} DeviceResetInputState; + /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. @@ -157,6 +168,8 @@ struct DeviceState { int instance_id_alias; int alias_required_for_version; uint32_t resetting; + DeviceResetInputState cold_reset_input; + DeviceResetInputState warm_reset_input; }; struct DeviceListener { @@ -361,6 +374,37 @@ static inline void qdev_init_gpio_in_named(DeviceState *dev, void qdev_pass_gpios(DeviceState *dev, DeviceState *container, const char *name); +/** + * qdev_init_reset_gpio_in_named: + * Create a gpio controlling the warm or cold reset of the device. + * @cold specify whether it triggers cold or warm reset + * @type what kind of reset io it is + */ +void qdev_init_reset_gpio_in_named(DeviceState *dev, const char *name, + bool cold, DeviceActiveType type); + +/** + * qdev_init_warm_reset_gpio: + * Create a reset input to control the device warm reset. + */ +static inline void qdev_init_warm_reset_gpio(DeviceState *dev, + const char *name, + DeviceActiveType type) +{ + qdev_init_reset_gpio_in_named(dev, name, false, type); +} + +/** + * qdev_init_power_gate_gpio: + * Create a power gate input to control the device cold reset. + */ +static inline void qdev_init_power_gate_gpio(DeviceState *dev, + const char *name, + DeviceActiveType type) +{ + qdev_init_reset_gpio_in_named(dev, name, true, type); +} + BusState *qdev_get_parent_bus(DeviceState *dev); /*** BUS API. ***/ From patchwork Mon Mar 25 11:01:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868803 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C915A13B5 for ; Mon, 25 Mar 2019 11:05:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4EF8290DF for ; Mon, 25 Mar 2019 11:05:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A890229149; 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b=e0ryLl+GV9GWIRdr7PF5n5ix/9+MGs7u9JDN55sjyzRHf2Wy+z8h0usJSnJW2N4gr tzX+5MLEZ4jV2xKqgkXZE1wGC+rd59C6KY0507RO2yxP5DrfrWOCtUyjtaTkzveQc7 UGDi2QT86aCXXCkd0Lx4l9UEe+0v03FaZklHZhZM= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:50 +0100 Message-Id: <126d324367f189b2f08df15ee1ff13add61add8a.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 07/17] convert qdev/bus_reset_all to Resettable X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Change qdev/bus_reset_all implementation. It now triggers a warm reset using the Resettable interface. Signed-off-by: Damien Hedde --- hw/core/qdev.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 8dae26d957..7adf234474 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -320,25 +320,9 @@ static void device_reset_exit_phase(Object *obj) } } -static int qdev_reset_one(DeviceState *dev, void *opaque) -{ - device_reset(dev); - - return 0; -} - -static int qbus_reset_one(BusState *bus, void *opaque) -{ - BusClass *bc = BUS_GET_CLASS(bus); - if (bc->reset) { - bc->reset(bus); - } - return 0; -} - void qdev_reset_all(DeviceState *dev) { - qdev_walk_children(dev, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + qdev_reset(dev, false); } void qdev_reset_all_fn(void *opaque) @@ -348,7 +332,7 @@ void qdev_reset_all_fn(void *opaque) void qbus_reset_all(BusState *bus) { - qbus_walk_children(bus, NULL, NULL, qdev_reset_one, qbus_reset_one, NULL); + qbus_reset(bus, false); } void qbus_reset_all_fn(void *opaque) From patchwork Mon Mar 25 11:01:51 2019 Content-Type: text/plain; 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Mon, 25 Mar 2019 12:02:24 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511745; bh=V2GiLuYeyXa93lsR6gIhPeq2caDfc8+2V/ubkHYglDo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=edE1SZalbNgt/MuvGPTcJtIAxP+NVai2oeV9YFBospvcQJMXW40hC6G0t34WouRxs 3leWGJ9gk6zQwmSs9yEUpERLgEAHFZw9qv8GQdklgXmLOrIjPVgwvxhOyiUrwEIauK 5hau4PKcLhW46cJCLTbqFVk1VrUswTsQuBkga5cg= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:51 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 08/17] Add a global ResetDomain object for system emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP All objects contained in this ResetDomain are cold-reset when calling qemu_devices_reset. Also add 2 functions to register/unregister object in this ResetDomain. Signed-off-by: Damien Hedde --- hw/core/reset.c | 56 +++++++++++++++++++++++++++++++++++++++++- include/sysemu/reset.h | 47 +++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/hw/core/reset.c b/hw/core/reset.c index 9c477f2bf5..d013c9feb9 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -3,6 +3,7 @@ * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2016 Red Hat, Inc. + * Copyright (c) 2019 GreenSocs * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,6 +27,7 @@ #include "qemu/osdep.h" #include "qemu/queue.h" #include "sysemu/reset.h" +#include "hw/reset-domain.h" /* reset/shutdown handler */ @@ -38,6 +40,49 @@ typedef struct QEMUResetEntry { static QTAILQ_HEAD(, QEMUResetEntry) reset_handlers = QTAILQ_HEAD_INITIALIZER(reset_handlers); +/* global/system reset domain */ +static ResetDomain *reset_domain; + +static ResetDomain *get_reset_domain(void) +{ + if (reset_domain == NULL) { + /* + * the ref to the object will be deleted by + * qemu_delete_system_reset_domain function below. + */ + reset_domain = RESET_DOMAIN(object_new(TYPE_RESET_DOMAIN)); + } + return reset_domain; +} + +ResetDomain *qemu_get_system_reset_domain(void) +{ + return get_reset_domain(); +} + +void qemu_delete_system_reset_domain(void) +{ + /* unref the reset_domain object if it exists */ + if (reset_domain != NULL) { + object_unref(OBJECT(reset_domain)); + reset_domain = NULL; + } +} + +void qemu_register_system_reset_domain_object(Object *obj) +{ + ResetDomain *domain = get_reset_domain(); + + reset_domain_register_object(domain, obj); +} + +void qemu_unregister_system_reset_domain_object(Object *obj) +{ + ResetDomain *domain = get_reset_domain(); + + reset_domain_unregister_object(domain, obj); +} + void qemu_register_reset(QEMUResetHandler *func, void *opaque) { QEMUResetEntry *re = g_malloc0(sizeof(QEMUResetEntry)); @@ -62,11 +107,20 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque) void qemu_devices_reset(void) { + qemu_system_reset_domain_reset(true); +} + +void qemu_system_reset_domain_reset(bool cold) +{ + ResetDomain *domain = get_reset_domain(); QEMUResetEntry *re, *nre; - /* reset all devices */ + /* call function handlers first */ QTAILQ_FOREACH_SAFE(re, &reset_handlers, entry, nre) { re->func(re->opaque); } + + /* then handle the objects in the ResetDomain */ + resettable_reset(OBJECT(domain), cold); } diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h index 0b0d6d7598..29843eca92 100644 --- a/include/sysemu/reset.h +++ b/include/sysemu/reset.h @@ -1,10 +1,57 @@ #ifndef QEMU_SYSEMU_RESET_H #define QEMU_SYSEMU_RESET_H +#include "qom/object.h" +#include "hw/reset-domain.h" + +/** + * qemu_get_system_reset_domain: + * Get the global system reset domain object + */ +ResetDomain *qemu_get_system_reset_domain(void); + +/** + * qemu_delete_system_reset_domain: + * Delete the global system reset domain object + */ +void qemu_delete_system_reset_domain(void); + +/** + * qemu_register_system_reset_domain_object: + * Register @obj in the system reset domain + */ +void qemu_register_system_reset_domain_object(Object *obj); + +/** + * qemu_unregister_system_reset_domain_object: + * Unregister @obj from the global reset domain + */ +void qemu_unregister_system_reset_domain_object(Object *obj); + +/** + * @qemu_system_reset_domain_reset: + * Do a cold or warm system reset based on @cold + */ +void qemu_system_reset_domain_reset(bool cold); + typedef void QEMUResetHandler(void *opaque); +/** + * qemu_resgiter_reset: + * Register @func with @opaque in the global reset procedure. + */ void qemu_register_reset(QEMUResetHandler *func, void *opaque); + +/** + * qemu_unregister_reset: + * Unregister @func with @opaque from the global reset procedure. + */ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque); + +/** + * qemu_devices_reset: + * Trigger a reset of registered handlers and objects. + */ void qemu_devices_reset(void); #endif From patchwork Mon Mar 25 11:01:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868845 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7B1BF13B5 for ; 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Mon, 25 Mar 2019 12:02:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511746; bh=Rj9t1gwEPvCQXgaespa0NYSplGJUEexyiDC/4aJcJ80=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LaTHN+u54Lo0ZaOByfK49EXd93FHs0TeHuuq7ZgEEfBYnvJdsZTw6GOAiNWSmWyhp Gmds46e9A7bNhg1jSIg5dps7DwyiWqZUWlTpeUPHTLg95ty1nSKnpN/hKze5wLI963 E1EsIqBk5ic5g7uVEuIax/in3FbV/DnDo3BhzeOE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:52 +0100 Message-Id: <1229faf2e82151a54b915d167f2071af36aceb5f.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 09/17] global ResetDomain support for legacy reset handlers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP INIT phase of the global ResetDomain now triggers the legacy reset handlers. *qemu_devices_reset* is now equivalent to do a cold reset of the global ResetDomain. Signed-off-by: Damien Hedde --- hw/core/reset.c | 109 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 95 insertions(+), 14 deletions(-) diff --git a/hw/core/reset.c b/hw/core/reset.c index d013c9feb9..1b25f9c8f8 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -26,9 +26,31 @@ #include "qemu/osdep.h" #include "qemu/queue.h" +#include "qemu/module.h" #include "sysemu/reset.h" #include "hw/reset-domain.h" +#define TYPE_SYSTEM_RESET_DOMAIN "system-reset-domain" +#define SYSTEM_RESET_DOMAIN(obj) \ + OBJECT_CHECK(SystemResetDomain, (obj), TYPE_SYSTEM_RESET_DOMAIN) +#define SYSTEM_RESET_DOMAIN_CLASS(class) \ + OBJECT_CLASS_CHECK(SystemResetDomainClass, (class), \ + TYPE_SYSTEM_RESET_DOMAIN) +#define SYSTEM_RESET_DOMAIN_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SystemResetDomainClass, (obj), \ + TYPE_SYSTEM_RESET_DOMAIN) + +/** + * SystemResetDomainClass: + * Class to hold the global reset domain and handlers + * @parent_init_phase hold parent init_phase method + */ +typedef struct SystemResetDomainClass { + ResetDomainClass parent_class; + + ResettableInitPhase parent_init_phase; +} SystemResetDomainClass; + /* reset/shutdown handler */ typedef struct QEMUResetEntry { @@ -37,27 +59,35 @@ typedef struct QEMUResetEntry { void *opaque; } QEMUResetEntry; -static QTAILQ_HEAD(, QEMUResetEntry) reset_handlers = - QTAILQ_HEAD_INITIALIZER(reset_handlers); +/** + * SystemResetDomain: + * @reset_handlers list of legacy reset handlers + */ +typedef struct SystemResetDomain { + ResetDomain parent_obj; + + QTAILQ_HEAD(, QEMUResetEntry) reset_handlers; +} SystemResetDomain; /* global/system reset domain */ -static ResetDomain *reset_domain; +static SystemResetDomain *reset_domain; -static ResetDomain *get_reset_domain(void) +static SystemResetDomain *get_reset_domain(void) { if (reset_domain == NULL) { + Object *obj = object_new(TYPE_SYSTEM_RESET_DOMAIN); /* * the ref to the object will be deleted by * qemu_delete_system_reset_domain function below. */ - reset_domain = RESET_DOMAIN(object_new(TYPE_RESET_DOMAIN)); + reset_domain = SYSTEM_RESET_DOMAIN(obj); } return reset_domain; } ResetDomain *qemu_get_system_reset_domain(void) { - return get_reset_domain(); + return RESET_DOMAIN(get_reset_domain()); } void qemu_delete_system_reset_domain(void) @@ -71,34 +101,36 @@ void qemu_delete_system_reset_domain(void) void qemu_register_system_reset_domain_object(Object *obj) { - ResetDomain *domain = get_reset_domain(); + ResetDomain *domain = RESET_DOMAIN(get_reset_domain()); reset_domain_register_object(domain, obj); } void qemu_unregister_system_reset_domain_object(Object *obj) { - ResetDomain *domain = get_reset_domain(); + ResetDomain *domain = RESET_DOMAIN(get_reset_domain()); reset_domain_unregister_object(domain, obj); } void qemu_register_reset(QEMUResetHandler *func, void *opaque) { + SystemResetDomain *domain = get_reset_domain(); QEMUResetEntry *re = g_malloc0(sizeof(QEMUResetEntry)); re->func = func; re->opaque = opaque; - QTAILQ_INSERT_TAIL(&reset_handlers, re, entry); + QTAILQ_INSERT_TAIL(&domain->reset_handlers, re, entry); } void qemu_unregister_reset(QEMUResetHandler *func, void *opaque) { + SystemResetDomain *domain = get_reset_domain(); QEMUResetEntry *re; - QTAILQ_FOREACH(re, &reset_handlers, entry) { + QTAILQ_FOREACH(re, &domain->reset_handlers, entry) { if (re->func == func && re->opaque == opaque) { - QTAILQ_REMOVE(&reset_handlers, re, entry); + QTAILQ_REMOVE(&domain->reset_handlers, re, entry); g_free(re); return; } @@ -112,15 +144,64 @@ void qemu_devices_reset(void) void qemu_system_reset_domain_reset(bool cold) { - ResetDomain *domain = get_reset_domain(); + resettable_reset(OBJECT(get_reset_domain()), cold); +} + +static void system_reset_domain_init_phase(Object *obj, bool cold) +{ + SystemResetDomain *domain = SYSTEM_RESET_DOMAIN(obj); + SystemResetDomainClass *srdc = SYSTEM_RESET_DOMAIN_GET_CLASS(obj); QEMUResetEntry *re, *nre; /* call function handlers first */ - QTAILQ_FOREACH_SAFE(re, &reset_handlers, entry, nre) { + QTAILQ_FOREACH_SAFE(re, &domain->reset_handlers, entry, nre) { re->func(re->opaque); } /* then handle the objects in the ResetDomain */ - resettable_reset(OBJECT(domain), cold); + srdc->parent_init_phase(OBJECT(domain), cold); +} + +static void system_reset_domain_init(Object *obj) +{ + SystemResetDomain *domain = SYSTEM_RESET_DOMAIN(obj); + + QTAILQ_INIT(&domain->reset_handlers); +} + +static void system_reset_domain_finalize(Object *obj) +{ + SystemResetDomain *domain = SYSTEM_RESET_DOMAIN(obj); + QEMUResetEntry *re, *nre; + + QTAILQ_FOREACH_SAFE(re, &domain->reset_handlers, entry, nre) { + QTAILQ_REMOVE(&domain->reset_handlers, re, entry); + g_free(re); + } +} + +static void system_reset_domain_class_init(ObjectClass *class, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(class); + SystemResetDomainClass *srdc = SYSTEM_RESET_DOMAIN_CLASS(class); + + srdc->parent_init_phase = rc->phases.init; + rc->phases.init = system_reset_domain_init_phase; +} + +static const TypeInfo system_reset_domain_type_info = { + .name = TYPE_SYSTEM_RESET_DOMAIN, + .parent = TYPE_RESET_DOMAIN, + .instance_size = sizeof(SystemResetDomain), + .instance_init = system_reset_domain_init, + .instance_finalize = system_reset_domain_finalize, + .class_init = system_reset_domain_class_init, + .class_size = sizeof(SystemResetDomainClass), +}; + +static void system_reset_register_types(void) +{ + type_register_static(&system_reset_domain_type_info); } +type_init(system_reset_register_types) From patchwork Mon Mar 25 11:01:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16E351669 for ; Mon, 25 Mar 2019 11:08:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0102E292F4 for ; Mon, 25 Mar 2019 11:08:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E8020292AA; Mon, 25 Mar 2019 11:08:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 73CE2292AA for ; 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Mon, 25 Mar 2019 12:02:26 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511747; bh=c3E94xCsfOaStIii3Bzkuh1u0yl828DPLI2z6qU2fU4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hzieZBGJA2wce4/bj/5NtWVzuyASvmLmrE1cgFfPqKr8xc3PbRpLBH3VjNOKzyDsK /wddgD8JGjI7zfoPq/7N4g+0gVoXB5QMsYZUzGj6rz3E2k1Zp/DHlGZfbCgKlsHZ9C JipK+GaqPyZ4mlg00xce3We+gNro9Xmu5BTenXt0= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:53 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 10/17] Delete the system ResetDomain at the end of emulation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Damien Hedde --- vl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/vl.c b/vl.c index d61d5604e5..cf081d5264 100644 --- a/vl.c +++ b/vl.c @@ -4611,6 +4611,7 @@ int main(int argc, char **argv, char **envp) monitor_cleanup(); qemu_chr_cleanup(); user_creatable_cleanup(); + qemu_delete_system_reset_domain(); /* TODO: unref root container, check all devices are ok */ return 0; From patchwork Mon Mar 25 11:01:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868827 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BFA61669 for ; Mon, 25 Mar 2019 11:12:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EDB5329242 for ; Mon, 25 Mar 2019 11:12:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E1C0A29322; Mon, 25 Mar 2019 11:12:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BB0A62932C for ; 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Signed-off-by: Damien Hedde --- hw/core/bus.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/core/bus.c b/hw/core/bus.c index 0a60bb4b24..73b215d2bb 100644 --- a/hw/core/bus.c +++ b/hw/core/bus.c @@ -150,7 +150,7 @@ static void qbus_realize(BusState *bus, DeviceState *parent, const char *name) } else if (bus != sysbus_get_default()) { /* TODO: once all bus devices are qdevified, only reset handler for main_system_bus should be registered here. */ - qemu_register_reset(qbus_reset_all_fn, bus); + qemu_register_system_reset_domain_object(OBJECT(bus)); } } @@ -169,7 +169,7 @@ static void bus_unparent(Object *obj) bus->parent = NULL; } else { assert(bus != sysbus_get_default()); /* main_system_bus is never freed */ - qemu_unregister_reset(qbus_reset_all_fn, bus); + qemu_unregister_system_reset_domain_object(OBJECT(bus)); } } From patchwork Mon Mar 25 11:01:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868855 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0096113B5 for ; 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Mon, 25 Mar 2019 12:02:28 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511749; bh=rS5NuPH0KWejCxspweaZSHPWSe35AiD/X4xqIKnJC4c=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=FHy3TTYmUKxF9JwyHjYXRM9a9W4opoCba8Q7JpI957jCmriCcS3S0fTm3jTQqA3SQ MJT9HZ6TJlMVKHsbFTHU9lssd1hFwJiQOSwxpPe+14eUpbpxrgCb3tEc8g1JRkYSKd iIAETAsXJyqfa3395AKsS4zZkOeC5TCL1TdLkikw= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:55 +0100 Message-Id: <31208397390bc323ec002cb8a3cb395cbd6fa9b5.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 12/17] Put default sysbus in system reset domain X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Switch from reset handler to Resettable interface. Signed-off-by: Damien Hedde --- vl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vl.c b/vl.c index cf081d5264..e67f6e6c50 100644 --- a/vl.c +++ b/vl.c @@ -4537,7 +4537,7 @@ int main(int argc, char **argv, char **envp) /* TODO: once all bus devices are qdevified, this should be done * when bus is created by qdev.c */ - qemu_register_reset(qbus_reset_all_fn, sysbus_get_default()); + qemu_register_system_reset_domain_object(OBJECT(sysbus_get_default())); qemu_run_machine_init_done_notifiers(); if (rom_check_and_register_reset() != 0) { From patchwork Mon Mar 25 11:01:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868859 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CA3B713B5 for ; Mon, 25 Mar 2019 11:18:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B2F2C291B4 for ; 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Mon, 25 Mar 2019 12:02:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511749; bh=HuL6AC9dOZFt5dcJMiZDlWJ+rqVxR3igcjeDAtYZ/zY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=z7JLzqVZha8XT+5GrmXcRRONPVgq8WnMGloBBRPGQho+IrwQGt6kf1rztztHEug2R N6lxpwcoft7ict0vM1oDV/yS6QT962VBVa5R9fxjbhP3hKZWhn+l8f9dLBGE6v53Fb iJlSKzIOmDDD/5g1AlXrlLpQl97P47KSe4RLiITY= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:56 +0100 Message-Id: <03ce654ebfc7f10c9b946e7561bf3f24a3d2a90c.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 13/17] hw/misc/zynq_slcr: use standard register definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Replace the zynq_slcr registers enum and macros using the hw/registerfields.h macros. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis --- hw/misc/zynq_slcr.c | 472 ++++++++++++++++++++++---------------------- 1 file changed, 236 insertions(+), 236 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d6bdd027ef..baa13d1316 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "sysemu/sysemu.h" #include "qemu/log.h" +#include "hw/registerfields.h" #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -35,138 +36,135 @@ #define XILINX_LOCK_KEY 0x767b #define XILINX_UNLOCK_KEY 0xdf0d -#define R_PSS_RST_CTRL_SOFT_RST 0x1 - -enum { - SCL = 0x000 / 4, - LOCK, - UNLOCK, - LOCKSTA, - - ARM_PLL_CTRL = 0x100 / 4, - DDR_PLL_CTRL, - IO_PLL_CTRL, - PLL_STATUS, - ARM_PLL_CFG, - DDR_PLL_CFG, - IO_PLL_CFG, - - ARM_CLK_CTRL = 0x120 / 4, - DDR_CLK_CTRL, - DCI_CLK_CTRL, - APER_CLK_CTRL, - USB0_CLK_CTRL, - USB1_CLK_CTRL, - GEM0_RCLK_CTRL, - GEM1_RCLK_CTRL, - GEM0_CLK_CTRL, - GEM1_CLK_CTRL, - SMC_CLK_CTRL, - LQSPI_CLK_CTRL, - SDIO_CLK_CTRL, - UART_CLK_CTRL, - SPI_CLK_CTRL, - CAN_CLK_CTRL, - CAN_MIOCLK_CTRL, - DBG_CLK_CTRL, - PCAP_CLK_CTRL, - TOPSW_CLK_CTRL, +REG32(SCL, 0x000) +REG32(LOCK, 0x004) +REG32(UNLOCK, 0x008) +REG32(LOCKSTA, 0x00c) + +REG32(ARM_PLL_CTRL, 0x100) +REG32(DDR_PLL_CTRL, 0x104) +REG32(IO_PLL_CTRL, 0x108) +REG32(PLL_STATUS, 0x10c) +REG32(ARM_PLL_CFG, 0x110) +REG32(DDR_PLL_CFG, 0x114) +REG32(IO_PLL_CFG, 0x118) + +REG32(ARM_CLK_CTRL, 0x120) +REG32(DDR_CLK_CTRL, 0x124) +REG32(DCI_CLK_CTRL, 0x128) +REG32(APER_CLK_CTRL, 0x12c) +REG32(USB0_CLK_CTRL, 0x130) +REG32(USB1_CLK_CTRL, 0x134) +REG32(GEM0_RCLK_CTRL, 0x138) +REG32(GEM1_RCLK_CTRL, 0x13c) +REG32(GEM0_CLK_CTRL, 0x140) +REG32(GEM1_CLK_CTRL, 0x144) +REG32(SMC_CLK_CTRL, 0x148) +REG32(LQSPI_CLK_CTRL, 0x14c) +REG32(SDIO_CLK_CTRL, 0x150) +REG32(UART_CLK_CTRL, 0x154) +REG32(SPI_CLK_CTRL, 0x158) +REG32(CAN_CLK_CTRL, 0x15c) +REG32(CAN_MIOCLK_CTRL, 0x160) +REG32(DBG_CLK_CTRL, 0x164) +REG32(PCAP_CLK_CTRL, 0x168) +REG32(TOPSW_CLK_CTRL, 0x16c) #define FPGA_CTRL_REGS(n, start) \ - FPGA ## n ## _CLK_CTRL = (start) / 4, \ - FPGA ## n ## _THR_CTRL, \ - FPGA ## n ## _THR_CNT, \ - FPGA ## n ## _THR_STA, - FPGA_CTRL_REGS(0, 0x170) - FPGA_CTRL_REGS(1, 0x180) - FPGA_CTRL_REGS(2, 0x190) - FPGA_CTRL_REGS(3, 0x1a0) - - BANDGAP_TRIP = 0x1b8 / 4, - PLL_PREDIVISOR = 0x1c0 / 4, - CLK_621_TRUE, - - PSS_RST_CTRL = 0x200 / 4, - DDR_RST_CTRL, - TOPSW_RESET_CTRL, - DMAC_RST_CTRL, - USB_RST_CTRL, - GEM_RST_CTRL, - SDIO_RST_CTRL, - SPI_RST_CTRL, - CAN_RST_CTRL, - I2C_RST_CTRL, - UART_RST_CTRL, - GPIO_RST_CTRL, - LQSPI_RST_CTRL, - SMC_RST_CTRL, - OCM_RST_CTRL, - FPGA_RST_CTRL = 0x240 / 4, - A9_CPU_RST_CTRL, - - RS_AWDT_CTRL = 0x24c / 4, - RST_REASON, - - REBOOT_STATUS = 0x258 / 4, - BOOT_MODE, - - APU_CTRL = 0x300 / 4, - WDT_CLK_SEL, - - TZ_DMA_NS = 0x440 / 4, - TZ_DMA_IRQ_NS, - TZ_DMA_PERIPH_NS, - - PSS_IDCODE = 0x530 / 4, - - DDR_URGENT = 0x600 / 4, - DDR_CAL_START = 0x60c / 4, - DDR_REF_START = 0x614 / 4, - DDR_CMD_STA, - DDR_URGENT_SEL, - DDR_DFI_STATUS, - - MIO = 0x700 / 4, + REG32(FPGA ## n ## _CLK_CTRL, (start)) \ + REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\ + REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\ + REG32(FPGA ## n ## _THR_STA, (start) + 0xc) +FPGA_CTRL_REGS(0, 0x170) +FPGA_CTRL_REGS(1, 0x180) +FPGA_CTRL_REGS(2, 0x190) +FPGA_CTRL_REGS(3, 0x1a0) + +REG32(BANDGAP_TRIP, 0x1b8) +REG32(PLL_PREDIVISOR, 0x1c0) +REG32(CLK_621_TRUE, 0x1c4) + +REG32(PSS_RST_CTRL, 0x200) + FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1) +REG32(DDR_RST_CTRL, 0x204) +REG32(TOPSW_RESET_CTRL, 0x208) +REG32(DMAC_RST_CTRL, 0x20c) +REG32(USB_RST_CTRL, 0x210) +REG32(GEM_RST_CTRL, 0x214) +REG32(SDIO_RST_CTRL, 0x218) +REG32(SPI_RST_CTRL, 0x21c) +REG32(CAN_RST_CTRL, 0x220) +REG32(I2C_RST_CTRL, 0x224) +REG32(UART_RST_CTRL, 0x228) +REG32(GPIO_RST_CTRL, 0x22c) +REG32(LQSPI_RST_CTRL, 0x230) +REG32(SMC_RST_CTRL, 0x234) +REG32(OCM_RST_CTRL, 0x238) +REG32(FPGA_RST_CTRL, 0x240) +REG32(A9_CPU_RST_CTRL, 0x244) + +REG32(RS_AWDT_CTRL, 0x24c) +REG32(RST_REASON, 0x250) + +REG32(REBOOT_STATUS, 0x258) +REG32(BOOT_MODE, 0x25c) + +REG32(APU_CTRL, 0x300) +REG32(WDT_CLK_SEL, 0x304) + +REG32(TZ_DMA_NS, 0x440) +REG32(TZ_DMA_IRQ_NS, 0x444) +REG32(TZ_DMA_PERIPH_NS, 0x448) + +REG32(PSS_IDCODE, 0x530) + +REG32(DDR_URGENT, 0x600) +REG32(DDR_CAL_START, 0x60c) +REG32(DDR_REF_START, 0x614) +REG32(DDR_CMD_STA, 0x618) +REG32(DDR_URGENT_SEL, 0x61c) +REG32(DDR_DFI_STATUS, 0x620) + +REG32(MIO, 0x700) #define MIO_LENGTH 54 - MIO_LOOPBACK = 0x804 / 4, - MIO_MST_TRI0, - MIO_MST_TRI1, +REG32(MIO_LOOPBACK, 0x804) +REG32(MIO_MST_TRI0, 0x808) +REG32(MIO_MST_TRI1, 0x80c) - SD0_WP_CD_SEL = 0x830 / 4, - SD1_WP_CD_SEL, +REG32(SD0_WP_CD_SEL, 0x830) +REG32(SD1_WP_CD_SEL, 0x834) - LVL_SHFTR_EN = 0x900 / 4, - OCM_CFG = 0x910 / 4, +REG32(LVL_SHFTR_EN, 0x900) +REG32(OCM_CFG, 0x910) - CPU_RAM = 0xa00 / 4, +REG32(CPU_RAM, 0xa00) - IOU = 0xa30 / 4, +REG32(IOU, 0xa30) - DMAC_RAM = 0xa50 / 4, +REG32(DMAC_RAM, 0xa50) - AFI0 = 0xa60 / 4, - AFI1 = AFI0 + 3, - AFI2 = AFI1 + 3, - AFI3 = AFI2 + 3, +REG32(AFI0, 0xa60) +REG32(AFI1, 0xa6c) +REG32(AFI2, 0xa78) +REG32(AFI3, 0xa84) #define AFI_LENGTH 3 - OCM = 0xa90 / 4, +REG32(OCM, 0xa90) - DEVCI_RAM = 0xaa0 / 4, +REG32(DEVCI_RAM, 0xaa0) - CSG_RAM = 0xab0 / 4, +REG32(CSG_RAM, 0xab0) - GPIOB_CTRL = 0xb00 / 4, - GPIOB_CFG_CMOS18, - GPIOB_CFG_CMOS25, - GPIOB_CFG_CMOS33, - GPIOB_CFG_HSTL = 0xb14 / 4, - GPIOB_DRVR_BIAS_CTRL, +REG32(GPIOB_CTRL, 0xb00) +REG32(GPIOB_CFG_CMOS18, 0xb04) +REG32(GPIOB_CFG_CMOS25, 0xb08) +REG32(GPIOB_CFG_CMOS33, 0xb0c) +REG32(GPIOB_CFG_HSTL, 0xb14) +REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) - DDRIOB = 0xb40 / 4, +REG32(DDRIOB, 0xb40) #define DDRIOB_LENGTH 14 -}; #define ZYNQ_SLCR_MMIO_SIZE 0x1000 #define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4) @@ -189,150 +187,152 @@ static void zynq_slcr_reset(DeviceState *d) DB_PRINT("RESET\n"); - s->regs[LOCKSTA] = 1; + s->regs[R_LOCKSTA] = 1; /* 0x100 - 0x11C */ - s->regs[ARM_PLL_CTRL] = 0x0001A008; - s->regs[DDR_PLL_CTRL] = 0x0001A008; - s->regs[IO_PLL_CTRL] = 0x0001A008; - s->regs[PLL_STATUS] = 0x0000003F; - s->regs[ARM_PLL_CFG] = 0x00014000; - s->regs[DDR_PLL_CFG] = 0x00014000; - s->regs[IO_PLL_CFG] = 0x00014000; + s->regs[R_ARM_PLL_CTRL] = 0x0001A008; + s->regs[R_DDR_PLL_CTRL] = 0x0001A008; + s->regs[R_IO_PLL_CTRL] = 0x0001A008; + s->regs[R_PLL_STATUS] = 0x0000003F; + s->regs[R_ARM_PLL_CFG] = 0x00014000; + s->regs[R_DDR_PLL_CFG] = 0x00014000; + s->regs[R_IO_PLL_CFG] = 0x00014000; /* 0x120 - 0x16C */ - s->regs[ARM_CLK_CTRL] = 0x1F000400; - s->regs[DDR_CLK_CTRL] = 0x18400003; - s->regs[DCI_CLK_CTRL] = 0x01E03201; - s->regs[APER_CLK_CTRL] = 0x01FFCCCD; - s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941; - s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001; - s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01; - s->regs[SMC_CLK_CTRL] = 0x00003C01; - s->regs[LQSPI_CLK_CTRL] = 0x00002821; - s->regs[SDIO_CLK_CTRL] = 0x00001E03; - s->regs[UART_CLK_CTRL] = 0x00003F03; - s->regs[SPI_CLK_CTRL] = 0x00003F03; - s->regs[CAN_CLK_CTRL] = 0x00501903; - s->regs[DBG_CLK_CTRL] = 0x00000F03; - s->regs[PCAP_CLK_CTRL] = 0x00000F01; + s->regs[R_ARM_CLK_CTRL] = 0x1F000400; + s->regs[R_DDR_CLK_CTRL] = 0x18400003; + s->regs[R_DCI_CLK_CTRL] = 0x01E03201; + s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD; + s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941; + s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001; + s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01; + s->regs[R_SMC_CLK_CTRL] = 0x00003C01; + s->regs[R_LQSPI_CLK_CTRL] = 0x00002821; + s->regs[R_SDIO_CLK_CTRL] = 0x00001E03; + s->regs[R_UART_CLK_CTRL] = 0x00003F03; + s->regs[R_SPI_CLK_CTRL] = 0x00003F03; + s->regs[R_CAN_CLK_CTRL] = 0x00501903; + s->regs[R_DBG_CLK_CTRL] = 0x00000F03; + s->regs[R_PCAP_CLK_CTRL] = 0x00000F01; /* 0x170 - 0x1AC */ - s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL] - = s->regs[FPGA3_CLK_CTRL] = 0x00101800; - s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA] - = s->regs[FPGA3_THR_STA] = 0x00010000; + s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL] + = s->regs[R_FPGA2_CLK_CTRL] + = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800; + s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA] + = s->regs[R_FPGA2_THR_STA] + = s->regs[R_FPGA3_THR_STA] = 0x00010000; /* 0x1B0 - 0x1D8 */ - s->regs[BANDGAP_TRIP] = 0x0000001F; - s->regs[PLL_PREDIVISOR] = 0x00000001; - s->regs[CLK_621_TRUE] = 0x00000001; + s->regs[R_BANDGAP_TRIP] = 0x0000001F; + s->regs[R_PLL_PREDIVISOR] = 0x00000001; + s->regs[R_CLK_621_TRUE] = 0x00000001; /* 0x200 - 0x25C */ - s->regs[FPGA_RST_CTRL] = 0x01F33F0F; - s->regs[RST_REASON] = 0x00000040; + s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F; + s->regs[R_RST_REASON] = 0x00000040; - s->regs[BOOT_MODE] = 0x00000001; + s->regs[R_BOOT_MODE] = 0x00000001; /* 0x700 - 0x7D4 */ for (i = 0; i < 54; i++) { - s->regs[MIO + i] = 0x00001601; + s->regs[R_MIO + i] = 0x00001601; } for (i = 2; i <= 8; i++) { - s->regs[MIO + i] = 0x00000601; + s->regs[R_MIO + i] = 0x00000601; } - s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF; + s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF; - s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3] - = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7] - = 0x00010101; - s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101; - s->regs[CPU_RAM + 6] = 0x00000001; + s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3] + = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7] + = 0x00010101; + s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101; + s->regs[R_CPU_RAM + 6] = 0x00000001; - s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3] - = 0x09090909; - s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909; - s->regs[IOU + 6] = 0x00000909; + s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2] + = s->regs[R_IOU + 3] = 0x09090909; + s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909; + s->regs[R_IOU + 6] = 0x00000909; - s->regs[DMAC_RAM] = 0x00000009; + s->regs[R_DMAC_RAM] = 0x00000009; - s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909; - s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909; - s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909; - s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909; - s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2] - = s->regs[AFI3 + 2] = 0x00000909; + s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909; + s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909; + s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909; + s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909; + s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2] + = s->regs[R_AFI3 + 2] = 0x00000909; - s->regs[OCM + 0] = 0x01010101; - s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909; + s->regs[R_OCM + 0] = 0x01010101; + s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909; - s->regs[DEVCI_RAM] = 0x00000909; - s->regs[CSG_RAM] = 0x00000001; + s->regs[R_DEVCI_RAM] = 0x00000909; + s->regs[R_CSG_RAM] = 0x00000001; - s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2] - = s->regs[DDRIOB + 3] = 0x00000e00; - s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6] - = 0x00000e00; - s->regs[DDRIOB + 12] = 0x00000021; + s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2] + = s->regs[R_DDRIOB + 3] = 0x00000e00; + s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6] + = 0x00000e00; + s->regs[R_DDRIOB + 12] = 0x00000021; } static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { switch (offset) { - case LOCK: - case UNLOCK: - case DDR_CAL_START: - case DDR_REF_START: + case R_LOCK: + case R_UNLOCK: + case R_DDR_CAL_START: + case R_DDR_REF_START: return !rnw; /* Write only */ - case LOCKSTA: - case FPGA0_THR_STA: - case FPGA1_THR_STA: - case FPGA2_THR_STA: - case FPGA3_THR_STA: - case BOOT_MODE: - case PSS_IDCODE: - case DDR_CMD_STA: - case DDR_DFI_STATUS: - case PLL_STATUS: + case R_LOCKSTA: + case R_FPGA0_THR_STA: + case R_FPGA1_THR_STA: + case R_FPGA2_THR_STA: + case R_FPGA3_THR_STA: + case R_BOOT_MODE: + case R_PSS_IDCODE: + case R_DDR_CMD_STA: + case R_DDR_DFI_STATUS: + case R_PLL_STATUS: return rnw;/* read only */ - case SCL: - case ARM_PLL_CTRL ... IO_PLL_CTRL: - case ARM_PLL_CFG ... IO_PLL_CFG: - case ARM_CLK_CTRL ... TOPSW_CLK_CTRL: - case FPGA0_CLK_CTRL ... FPGA0_THR_CNT: - case FPGA1_CLK_CTRL ... FPGA1_THR_CNT: - case FPGA2_CLK_CTRL ... FPGA2_THR_CNT: - case FPGA3_CLK_CTRL ... FPGA3_THR_CNT: - case BANDGAP_TRIP: - case PLL_PREDIVISOR: - case CLK_621_TRUE: - case PSS_RST_CTRL ... A9_CPU_RST_CTRL: - case RS_AWDT_CTRL: - case RST_REASON: - case REBOOT_STATUS: - case APU_CTRL: - case WDT_CLK_SEL: - case TZ_DMA_NS ... TZ_DMA_PERIPH_NS: - case DDR_URGENT: - case DDR_URGENT_SEL: - case MIO ... MIO + MIO_LENGTH - 1: - case MIO_LOOPBACK ... MIO_MST_TRI1: - case SD0_WP_CD_SEL: - case SD1_WP_CD_SEL: - case LVL_SHFTR_EN: - case OCM_CFG: - case CPU_RAM: - case IOU: - case DMAC_RAM: - case AFI0 ... AFI3 + AFI_LENGTH - 1: - case OCM: - case DEVCI_RAM: - case CSG_RAM: - case GPIOB_CTRL ... GPIOB_CFG_CMOS33: - case GPIOB_CFG_HSTL: - case GPIOB_DRVR_BIAS_CTRL: - case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1: + case R_SCL: + case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL: + case R_ARM_PLL_CFG ... R_IO_PLL_CFG: + case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL: + case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT: + case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT: + case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT: + case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT: + case R_BANDGAP_TRIP: + case R_PLL_PREDIVISOR: + case R_CLK_621_TRUE: + case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL: + case R_RS_AWDT_CTRL: + case R_RST_REASON: + case R_REBOOT_STATUS: + case R_APU_CTRL: + case R_WDT_CLK_SEL: + case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS: + case R_DDR_URGENT: + case R_DDR_URGENT_SEL: + case R_MIO ... R_MIO + MIO_LENGTH - 1: + case R_MIO_LOOPBACK ... R_MIO_MST_TRI1: + case R_SD0_WP_CD_SEL: + case R_SD1_WP_CD_SEL: + case R_LVL_SHFTR_EN: + case R_OCM_CFG: + case R_CPU_RAM: + case R_IOU: + case R_DMAC_RAM: + case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1: + case R_OCM: + case R_DEVCI_RAM: + case R_CSG_RAM: + case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33: + case R_GPIOB_CFG_HSTL: + case R_GPIOB_DRVR_BIAS_CTRL: + case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1: return true; default: return false; @@ -370,24 +370,24 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, } switch (offset) { - case SCL: - s->regs[SCL] = val & 0x1; + case R_SCL: + s->regs[R_SCL] = val & 0x1; return; - case LOCK: + case R_LOCK: if ((val & 0xFFFF) == XILINX_LOCK_KEY) { DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, (unsigned)val & 0xFFFF); - s->regs[LOCKSTA] = 1; + s->regs[R_LOCKSTA] = 1; } else { DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, (unsigned)val & 0xFFFF); } return; - case UNLOCK: + case R_UNLOCK: if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) { DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, (unsigned)val & 0xFFFF); - s->regs[LOCKSTA] = 0; + s->regs[R_LOCKSTA] = 0; } else { DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n", (int)offset, (unsigned)val & 0xFFFF); @@ -395,7 +395,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, return; } - if (s->regs[LOCKSTA]) { + if (s->regs[R_LOCKSTA]) { qemu_log_mask(LOG_GUEST_ERROR, "SCLR registers are locked. Unlock them first\n"); return; @@ -403,8 +403,8 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, s->regs[offset] = val; switch (offset) { - case PSS_RST_CTRL: - if (val & R_PSS_RST_CTRL_SOFT_RST) { + case R_PSS_RST_CTRL: + if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) { qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; From patchwork Mon Mar 25 11:01:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F12713B5 for ; Mon, 25 Mar 2019 11:11:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1C0AB29277 for ; Mon, 25 Mar 2019 11:11:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A7142931E; 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Mon, 25 Mar 2019 12:02:33 +0100 (CET) Received: by greensocs.com (Postfix, from userid 998) id 667B17D7887; Mon, 25 Mar 2019 12:02:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511752; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=dJTBW0M2is/2YCfUp4+QJ6ORlYrrXG/4xiGNRekIuQCYgxDQMf/5LMPXida4LJ1QY Oh1e+SeVA1K9vrHYYCrSUkH6egpqBQgz3ZsgJggJxr10xwBsPIF65cvN13lUz/bxDT Kz98GjhcOb9hGUxjoVR8kgFoSbekBVaLQvUIz8ng= Received: from kouign-amann.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: damien.hedde@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 4349E7D78BC; Mon, 25 Mar 2019 12:02:30 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511750; bh=WYEcYLOEIGBkhOa2aU0abUg66uqcWe4gaMtFGotmZkU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=DCYeiaZ7Txq3XDAmFnR36pIeypmNDiDxPYYOvhv438a42zSd5eZyz0glG9AePRVs3 GcBTQWWK6pQa5liMoSfC//ARoJma/8WLy8m89wm8noOCRkanDA5BSK5NSG32HGsclg fdTZAYC+E4od48qMSakc3XqykkOJhI4o1+gavKYE= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:57 +0100 Message-Id: <052e5afb8c6cbaf6fac894ee7bfdc7ed03d38788.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 14/17] convert cadence_uart to 3-phases reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Split the existing reset procedure into 3 phases. Test the resetting flag to discard register accesses and character reception. Also adds a active high reset io. Signed-off-by: Damien Hedde --- hw/char/cadence_uart.c | 48 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fbdbd463bb..694c8ea614 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -222,6 +222,10 @@ static int uart_can_receive(void *opaque) int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (qdev_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); } @@ -337,6 +341,10 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) CadenceUARTState *s = opaque; uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -350,6 +358,10 @@ static void uart_event(void *opaque, int event) CadenceUARTState *s = opaque; uint8_t buf = '\0'; + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + if (event == CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -382,6 +394,10 @@ static void uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s = opaque; + if (qdev_is_resetting((DeviceState *)opaque)) { + return; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { @@ -440,6 +456,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset, CadenceUARTState *s = opaque; uint32_t c = 0; + if (qdev_is_resetting((DeviceState *)opaque)) { + return 0; + } + offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { c = 0; @@ -459,9 +479,9 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, bool cold) { - CadenceUARTState *s = CADENCE_UART(dev); + CadenceUARTState *s = CADENCE_UART(obj); s->r[R_CR] = 0x00000128; s->r[R_IMR] = 0; @@ -470,6 +490,18 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] = 0x0000028B; s->r[R_BDIV] = 0x0000000F; s->r[R_TTRIG] = 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); + + qemu_set_irq(s->irq, 0); +} + +static void cadence_uart_reset_exit(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); uart_rx_reset(s); uart_tx_reset(s); @@ -498,6 +530,8 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; + + qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_ACTIVE_HIGH); } static int cadence_uart_post_load(void *opaque, int version_id) @@ -532,6 +566,10 @@ static const VMStateDescription vmstate_cadence_uart = { VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &device_vmstate_reset, + NULL } }; @@ -546,9 +584,11 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data) dc->realize = cadence_uart_realize; dc->vmsd = &vmstate_cadence_uart; - dc->reset = cadence_uart_reset; + dc->reset_phases.init = cadence_uart_reset_init; + dc->reset_phases.hold = cadence_uart_reset_hold; + dc->reset_phases.exit = cadence_uart_reset_exit; dc->props = cadence_uart_properties; - } +} static const TypeInfo cadence_uart_info = { .name = TYPE_CADENCE_UART, From patchwork Mon Mar 25 11:01:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0B222925 for ; Mon, 25 Mar 2019 11:21:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA60929276 for ; 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Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/zynq_slcr.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index baa13d1316..47f43e1d8d 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -180,9 +180,9 @@ typedef struct ZynqSLCRState { uint32_t regs[ZYNQ_SLCR_NUM_REGS]; } ZynqSLCRState; -static void zynq_slcr_reset(DeviceState *d) +static void zynq_slcr_reset_init(Object *obj, bool cold) { - ZynqSLCRState *s = ZYNQ_SLCR(d); + ZynqSLCRState *s = ZYNQ_SLCR(obj); int i; DB_PRINT("RESET\n"); @@ -346,6 +346,10 @@ static uint64_t zynq_slcr_read(void *opaque, hwaddr offset, offset /= 4; uint32_t ret = s->regs[offset]; + if (qdev_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (!zynq_slcr_check_offset(offset, true)) { qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to " " addr %" HWADDR_PRIx "\n", offset * 4); @@ -361,6 +365,10 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, ZynqSLCRState *s = (ZynqSLCRState *)opaque; offset /= 4; + if (qdev_is_resetting((DeviceState *) opaque)) { + return; + } + DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); if (!zynq_slcr_check_offset(offset, false)) { @@ -441,7 +449,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &vmstate_zynq_slcr; - dc->reset = zynq_slcr_reset; + dc->reset_phases.init = zynq_slcr_reset_init; } static const TypeInfo zynq_slcr_info = { From patchwork Mon Mar 25 11:01:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868849 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C93013B5 for ; Mon, 25 Mar 2019 11:14:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5732C28479 for ; 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Mon, 25 Mar 2019 12:02:32 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511753; bh=cHW197nSVdJdU8mrnmNppk6kPW0LZpeckZV4M1rzKSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=b9ti8lX+1jB/p50Qd+i9TV7PY51AjPUyWodE4uKylVctOvIokpeZfQjtSrgebl7I2 eOFE4wTt3/ajXzPw5FCia4PYOCO8SIt2FWpPKrsSWcR9ESOxcy2loX51iWt4LH9Kle tjhZHbNBphnIyJkfAkENNNq+clqokFhW0zuF68+E= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:01:59 +0100 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 16/17] Add uart reset support in zynq_slcr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add two gpio outputs to control the uart resets. Signed-off-by: Damien Hedde --- hw/misc/zynq_slcr.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 47f43e1d8d..5aa8f55b45 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -96,6 +96,10 @@ REG32(SPI_RST_CTRL, 0x21c) REG32(CAN_RST_CTRL, 0x220) REG32(I2C_RST_CTRL, 0x224) REG32(UART_RST_CTRL, 0x228) + FIELD(UART_RST_CTRL, UART0_CPU1X_RST, 0, 1) + FIELD(UART_RST_CTRL, UART1_CPU1X_RST, 1, 1) + FIELD(UART_RST_CTRL, UART0_REF_RST, 2, 1) + FIELD(UART_RST_CTRL, UART1_REF_RST, 3, 1) REG32(GPIO_RST_CTRL, 0x22c) REG32(LQSPI_RST_CTRL, 0x230) REG32(SMC_RST_CTRL, 0x234) @@ -178,8 +182,14 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + qemu_irq uart0_rst; + qemu_irq uart1_rst; } ZynqSLCRState; +#define ZYNQ_SLCR_REGFIELD_TO_OUT(state, irq, reg, field) \ + qemu_set_irq((state)->irq, ARRAY_FIELD_EX32((state)->regs, reg, field) != 0) + static void zynq_slcr_reset_init(Object *obj, bool cold) { ZynqSLCRState *s = ZYNQ_SLCR(obj); @@ -276,6 +286,18 @@ static void zynq_slcr_reset_init(Object *obj, bool cold) s->regs[R_DDRIOB + 12] = 0x00000021; } +static void zynq_slcr_compute_uart_reset(ZynqSLCRState *s) +{ + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart0_rst, UART_RST_CTRL, UART0_REF_RST); + ZYNQ_SLCR_REGFIELD_TO_OUT(s, uart1_rst, UART_RST_CTRL, UART1_REF_RST); +} + +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s = ZYNQ_SLCR(obj); + + zynq_slcr_compute_uart_reset(s); +} static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { @@ -416,6 +438,9 @@ static void zynq_slcr_write(void *opaque, hwaddr offset, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_UART_RST_CTRL: + zynq_slcr_compute_uart_reset(s); + break; } } @@ -432,6 +457,9 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_gpio_out_named(DEVICE(obj), &s->uart0_rst, "uart0_rst", 1); + qdev_init_gpio_out_named(DEVICE(obj), &s->uart1_rst, "uart1_rst", 1); } static const VMStateDescription vmstate_zynq_slcr = { @@ -450,6 +478,7 @@ static void zynq_slcr_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_zynq_slcr; dc->reset_phases.init = zynq_slcr_reset_init; + dc->reset_phases.hold = zynq_slcr_reset_hold; } static const TypeInfo zynq_slcr_info = { From patchwork Mon Mar 25 11:02:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 10868857 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 75B5013B5 for ; Mon, 25 Mar 2019 11:16:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5F73A29124 for ; Mon, 25 Mar 2019 11:16:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 52E86289B7; Mon, 25 Mar 2019 11:16:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E1819289B7 for ; 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Mon, 25 Mar 2019 12:02:33 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1553511754; bh=q6FilVEc49Ov6DKXMr4Va1XrZ/oFtHx1uhJ+EdQrj6s=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=BySBMNBbVboWmp3CeulUev72Cb7Gwq78sSccMqIzu9K8sMO/GeQJkvUT5YpJ1rf9m 3Y6gf6OSOqHM4eo2d4YoyeD3oYmwaczSnHOlBOXidqG99aSAs8poNq/JlgxlN84FMm PJrXCo0skFrE5MAsOSqs89jijg69FlCxxa8qdgZk= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 25 Mar 2019 12:02:00 +0100 Message-Id: <3530c02ee3b1c8c28930a6ff1aff6bf3308714d8.1553510737.git.damien.hedde@greensocs.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [RFC PATCH 17/17] Connect the uart reset gpios in the zynq platform X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, mark.burton@greensocs.com, Damien Hedde , qemu-arm@nongnu.org, alistair.francis@wdc.com, marcandre.lureau@redhat.com, pbonzini@redhat.com, philmd@redhat.com, luc.michel@greensocs.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Connect the two uart reset inputs to the slcr corresponding outputs. Signed-off-by: Damien Hedde --- hw/arm/xilinx_zynq.c | 14 ++++++++------ include/hw/char/cadence_uart.h | 10 +++++++++- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index b3b8215759..528d1c42fd 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -166,7 +166,7 @@ static void zynq_init(MachineState *machine) MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -211,9 +211,9 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); - dev = qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + slcr = qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -234,8 +234,10 @@ static void zynq_init(MachineState *machine) sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0), + slcr, "uart0-rst", 0); + cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1), + slcr, "uart1-rst", 0); sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h index 118e3f10de..b7489a711f 100644 --- a/include/hw/char/cadence_uart.h +++ b/include/hw/char/cadence_uart.h @@ -51,7 +51,10 @@ typedef struct { static inline DeviceState *cadence_uart_create(hwaddr addr, qemu_irq irq, - Chardev *chr) + Chardev *chr, + DeviceState *rst_dev, + const char *rst_name, + int rst_n) { DeviceState *dev; SysBusDevice *s; @@ -63,6 +66,11 @@ static inline DeviceState *cadence_uart_create(hwaddr addr, sysbus_mmio_map(s, 0, addr); sysbus_connect_irq(s, 0, irq); + if (rst_dev) { + qdev_connect_gpio_out_named(rst_dev, rst_name, rst_n, + qdev_get_gpio_in_named(dev, "rst", 0)); + } + return dev; }