From patchwork Mon Mar 25 16:35:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869605 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1591D14DE for ; Mon, 25 Mar 2019 16:36:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F401A28AC1 for ; Mon, 25 Mar 2019 16:36:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E7D912949B; Mon, 25 Mar 2019 16:36:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A8F4028AC1 for ; Mon, 25 Mar 2019 16:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726743AbfCYQgO (ORCPT ); Mon, 25 Mar 2019 12:36:14 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42069 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQgO (ORCPT ); Mon, 25 Mar 2019 12:36:14 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 6B2A825B780; Tue, 26 Mar 2019 03:36:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531770; bh=Oqb/hl/Z/0kQebo3QZgObCYRrnL6kqqCMEqs+9Fr+nQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LuKqBgKYD+W+HNIDfpsTdu7xMFyubh7W+hZIKYpyl/pQZ8n4tjLy4LSy6la4j31mQ EjZCHtKxmVqQjEdyL6/temktdzCuDkspmghbAGK57tTmgbR4hbJqpMZrfiCOKewXwi NmBVTBnFWSBOTZgKZcSOsdCFPMAd/+74xjSJnvZU= Received: by reginn.horms.nl (Postfix, from userid 7100) id 9FFEC9403ED; Mon, 25 Mar 2019 17:36:08 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Takeshi Kihara , Simon Horman Subject: [PATCH v6 1/7] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Date: Mon, 25 Mar 2019 17:35:50 +0100 Message-Id: <20190325163556.22025-2-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed divisor other than 2, the value used by all such clocks supported to date. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which has a fixed divisor of 4. Signed-off-by: Takeshi Kihara [simon: squashed several patches; rewrote changelog; added r8a774a1 change] Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v3 - Retain original whitespace alignment v2 - New patch --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 24 +++++++++++++++--------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 6 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 4d92b27a6153..99bcb7c8022f 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 86842c9fd314..d4cf1c91533e 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7795 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * @@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 12c455859f2c..77254f2b4519 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2016 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index eb1cca58a1e1..f8f73558c1ec 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index dcd4ac389326..be0940c8103c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -96,6 +96,7 @@ struct cpg_z_clk { void __iomem *reg; void __iomem *kick_reg; unsigned long mask; + unsigned int fixed_div; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -110,17 +111,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, val = readl(zclk->reg) & zclk->mask; mult = 32 - (val >> __ffs(zclk->mask)); - /* Factor of 2 is for fixed divider */ - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); } static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - /* Factor of 2 is for fixed divider */ - unsigned long prate = *parent_rate / 2; + struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned long prate; unsigned int mult; + prate = *parent_rate / zclk->fixed_div;; mult = div_u64(rate * 32ULL, prate); mult = clamp(mult, 1U, 32U); @@ -134,8 +136,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int mult; unsigned int i; - /* Factor of 2 is for fixed divider */ - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); + mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, + parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) @@ -178,7 +180,8 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, - unsigned long mask) + unsigned long mask, + unsigned int div) { struct clk_init_data init; struct cpg_z_clk *zclk; @@ -198,6 +201,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = mask; + zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) @@ -658,11 +662,13 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_Z: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_ZFC_MASK); + base, CPG_FRQCRC_ZFC_MASK, + core->div); case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_Z2FC_MASK); + base, CPG_FRQCRC_Z2FC_MASK, + core->div); case CLK_TYPE_GEN3_OSC: /* diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index eac1b057455a..802936625330 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -3,6 +3,7 @@ * R-Car Gen3 Clock Pulse Generator * * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * */ @@ -51,6 +52,9 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult; From patchwork Mon Mar 25 16:35:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869611 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 97411186D for ; Mon, 25 Mar 2019 16:36:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87C0B29166 for ; Mon, 25 Mar 2019 16:36:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7BFA6294AD; Mon, 25 Mar 2019 16:36:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F245F29166 for ; Mon, 25 Mar 2019 16:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728991AbfCYQgR (ORCPT ); Mon, 25 Mar 2019 12:36:17 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQgR (ORCPT ); Mon, 25 Mar 2019 12:36:17 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 77CE725BF11; Tue, 26 Mar 2019 03:36:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531770; bh=hTBOP4/q8S38Fvveefu/jLfh/8DqZvlAyVPGzLc5Ud4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i6shlfcV8yhiI7R231np1KUhUH9xLSpvhqDh+JCQTu/QBwmFVITybhu2GkAeFmXL3 Bz4/3Gbed/m4r/Ch1rzdev57NDPLu275M5IwsPnkfeZWzgXooYmBV1BeI7fF7hWo+g 1uEtMUTdPHzsRjTjfomXinDAMVn0lsfaxaUxsjPU= Received: by reginn.horms.nl (Postfix, from userid 7100) id B3DB19405D8; Mon, 25 Mar 2019 17:36:08 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Simon Horman Subject: [PATCH v6 2/7] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset Date: Mon, 25 Mar 2019 17:35:51 +0100 Message-Id: <20190325163556.22025-3-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Parameterise the offset of control bits within the FRQCRC register for Z and Z2 clocks. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which uses a different offset for control bits to other, already, supported SoCs. As suggested by Geert Uytterhoeven. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v6 - Revise changelog v3 - New patch --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 15 ++++----------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++-- 6 files changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 99bcb7c8022f..8e7bb43b6848 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index d4cf1c91533e..d09c0abb032d 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -74,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 77254f2b4519..7efd0311dcbd 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -74,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), - DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index f8f73558c1ec..fefa26a1a797 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index be0940c8103c..9af3e1ece81a 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -88,8 +88,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, #define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x000000e0 -#define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) -#define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) struct cpg_z_clk { struct clk_hw hw; @@ -180,8 +178,8 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, - unsigned long mask, - unsigned int div) + unsigned int div, + unsigned int offset) { struct clk_init_data init; struct cpg_z_clk *zclk; @@ -200,7 +198,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->reg = reg + CPG_FRQCRC; zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; - zclk->mask = mask; + zclk->mask = GENMASK(offset + 4, offset); zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); @@ -661,14 +659,9 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, break; case CLK_TYPE_GEN3_Z: - return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_ZFC_MASK, - core->div); - case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_Z2FC_MASK, - core->div); + base, core->div, core->offset); case CLK_TYPE_GEN3_OSC: /* diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 802936625330..9b4bb763f599 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -52,8 +52,8 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ - DEF_BASE(_name, _id, _type, _parent, .div = _div) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) struct rcar_gen3_cpg_pll_config { u8 extal_div; From patchwork Mon Mar 25 16:35:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869613 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B7D317E6 for ; Mon, 25 Mar 2019 16:36:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0774528AC1 for ; Mon, 25 Mar 2019 16:36:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F070C2948A; Mon, 25 Mar 2019 16:36:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8446328AC1 for ; Mon, 25 Mar 2019 16:36:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729489AbfCYQgT (ORCPT ); Mon, 25 Mar 2019 12:36:19 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQgT (ORCPT ); Mon, 25 Mar 2019 12:36:19 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id A022825BF14; Tue, 26 Mar 2019 03:36:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531770; bh=IQE8WE3zl0IXtAYgkk87m+oHFzh5mtrQqjbXc+ZriKE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iqlZTCofEg82klZTBKRmz+AJCGYMG6R0WC7jtEeqXCI59dpl/+Kg11deVV9r5VMWG MfeXcR6l2Io2ezEnviacGBDP6JWvYU471Y6WHpuQ+wr6joGjxyZcAJc20GAc2IspSH lOzDxj6E7rUpLNwB9aU334rF13XsebH0P2YjSlvU= Received: by reginn.horms.nl (Postfix, from userid 7100) id CA9F19406BB; Mon, 25 Mar 2019 17:36:08 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Simon Horman Subject: [PATCH v6 3/7] clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 Date: Mon, 25 Mar 2019 17:35:52 +0100 Message-Id: <20190325163556.22025-4-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP After recent reworking of Z and Z2 clk handling CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely the same meaning. Remove this redundancy by eliminating the latter. This is not expected to have any run-time effect. As suggested by Geert Uytterhoeven. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v6 - New patch --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +- drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 1 - drivers/clk/renesas/rcar-gen3-cpg.h | 1 - 5 files changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 8e7bb43b6848..44161fd0a09c 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -72,7 +72,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index d09c0abb032d..8287816523c3 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -75,7 +75,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 7efd0311dcbd..5cde1bff8923 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -75,7 +75,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 9af3e1ece81a..a46c5dffbc24 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -659,7 +659,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, break; case CLK_TYPE_GEN3_Z: - case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), base, core->div, core->offset); diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 9b4bb763f599..15700d219a05 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -21,7 +21,6 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_GEN3_Z, - CLK_TYPE_GEN3_Z2, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, From patchwork Mon Mar 25 16:35:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E42FF186D for ; Mon, 25 Mar 2019 16:36:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D3B1E29166 for ; Mon, 25 Mar 2019 16:36:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C833B2949B; Mon, 25 Mar 2019 16:36:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 81ED529166 for ; Mon, 25 Mar 2019 16:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729125AbfCYQgV (ORCPT ); Mon, 25 Mar 2019 12:36:21 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQgV (ORCPT ); Mon, 25 Mar 2019 12:36:21 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id BAC3325BF15; Tue, 26 Mar 2019 03:36:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531771; bh=40aXj6/gt4xoni++7qBcCs23s4Ow0DogxkOQvF6oujY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CZbkl2dQyUaMvdVt22tOByqEVMj5A0051fSzhmiI8eu0p7CIlLphJ01L3xxJvP/6h /6Kcxmgavfzsw+VE6uuOilgdIP8VGqtPQuH6nxNbvV/1woY6g3oH9ALuGvz2vxdwHl kv8Mc2gr1zeDNLvb16ugBpnHZRFX/2QCskssS59U= Received: by reginn.horms.nl (Postfix, from userid 7100) id DF306940857; Mon, 25 Mar 2019 17:36:08 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Simon Horman Subject: [PATCH v6 4/7] math64: New DIV64_U64_ROUND_CLOSEST helper Date: Mon, 25 Mar 2019 17:35:53 +0100 Message-Id: <20190325163556.22025-5-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Provide DIV64_U64_ROUND_CLOSEST helper which performs division rounded to the closest integer using an unsigned 64bit dividend and divisor. This will be used in a follow-up patch to allow calculation of clock divisors with high frequency parents in the R-Car Gen3 CPG MSSR driver where overflow occurs if either the dividend or divisor is 32bit. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v6 - Updated changelog as per suggestions from Sergei Shtylyov and Geert Uytterhoeven - Added Reviewed-by tag from Geert Uytterhoeven v5 - New separate patch to add DIV64_U64_ROUND_CLOSEST --- include/linux/math64.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/math64.h b/include/linux/math64.h index bb2c84afb80c..65bef21cdddb 100644 --- a/include/linux/math64.h +++ b/include/linux/math64.h @@ -284,4 +284,17 @@ static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor) #define DIV64_U64_ROUND_UP(ll, d) \ ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) +/** + * DIV64_U64_ROUND_CLOSEST - unsigned 64bit divide with 64bit divisor rounded to nearest integer + * @dividend: unsigned 64bit dividend + * @divisor: unsigned 64bit divisor + * + * Divide unsigned 64bit dividend by unsigned 64bit divisor + * and round to closest integer. + * + * Return: dividend / divisor rounded to nearest integer + */ +#define DIV64_U64_ROUND_CLOSEST(dividend, divisor) \ + ({ u64 _tmp = (divisor); div64_u64((dividend) + _tmp / 2, _tmp); }) + #endif /* _LINUX_MATH64_H */ From patchwork Mon Mar 25 16:35:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869627 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0A69186D for ; Mon, 25 Mar 2019 16:36:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D0BD029317 for ; Mon, 25 Mar 2019 16:36:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C3FF829166; Mon, 25 Mar 2019 16:36:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 71B5E29166 for ; Mon, 25 Mar 2019 16:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729238AbfCYQgZ (ORCPT ); Mon, 25 Mar 2019 12:36:25 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQgY (ORCPT ); Mon, 25 Mar 2019 12:36:24 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id CCFDA25BF18; Tue, 26 Mar 2019 03:36:12 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531773; bh=M23cGuAyZoTvu0YMCWt7hsmrDNWufMprF5M9Xl/hwco=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SXSSRpTUFrF1kveZ2QfT75DZWko9U7TfVJOK1XFNLoNmX9nqR4nCHCjsUyr6zOeA9 FhwY2S868gkXvFE34/ArMfrciAaV/psTA/GeNY5AezvZcCdPRuR1/Ga0+4tOnNMvpu OOGAjnxkEVbdeXjojyOJzvBRlhF27/A/lZRttmFQ= Received: by reginn.horms.nl (Postfix, from userid 7100) id 102F3940862; Mon, 25 Mar 2019 17:36:09 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Simon Horman Subject: [PATCH v6 5/7] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Date: Mon, 25 Mar 2019 17:35:54 +0100 Message-Id: <20190325163556.22025-6-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support Z and Z2 clocks with parent frequencies greater than UINT32_MAX Hz (~4.29GHz). The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit dividend and 32bit divisor. This leads to truncation of the divisor, which is the Z or Z2 parent clock frequency in HZ, on platforms where frequency of that clock is greater than UINT32_MAX Hz. To resolve this problem the DIV64_U64_ROUND_CLOSEST() macro, which takes on an unsigned 64bit dividend and divisor, is used. An earlier version of this patch made use of the existing DIV_ROUND_CLOSEST() macro, which accepts the prevailing type of the dividend and divisor. However, this does not compile on 32bit systems, such as i386 and mips, when called with the types used at this call site, an unsigned long long dividend and unsigned long divisor. This work is in preparation for supporting the Z2 clock on the R-Car Gen3 E3 (r8a77990) SoC which has a 4.8GHz parent clock. Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v6 - Revise changelog v5 - Move adding DIV64_U64_ROUND_CLOSEST to a separate patch - Revise changelog v4 - Add and use DIV64_U64_ROUND_CLOSEST v2 - New patch --- drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a46c5dffbc24..b64cd188c1ae 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -134,8 +134,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int mult; unsigned int i; - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, - parent_rate); + mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, + parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) From patchwork Mon Mar 25 16:35:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869633 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5C1E117E6 for ; Mon, 25 Mar 2019 16:36:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4831528AC1 for ; Mon, 25 Mar 2019 16:36:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CF662949B; Mon, 25 Mar 2019 16:36:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D477828AC1 for ; Mon, 25 Mar 2019 16:36:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729548AbfCYQg2 (ORCPT ); Mon, 25 Mar 2019 12:36:28 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQg2 (ORCPT ); Mon, 25 Mar 2019 12:36:28 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id D5B1725BF1A; Tue, 26 Mar 2019 03:36:12 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531773; bh=VTmfI1RpN8llD9o4cImJwuTvYsif2vel8g6Mje3h3aA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XDCqo2Q1L5IOmt9CFwWWqv0qMq8DpzBaR+3RyQv14+5MuF78NUEx9pU7V28khU6BB cHxfw905TVvmd11/hl4n1q3BHzwEijMSdboaAunBmivgNXIM9tq93B3pjaN3Kmg6Vy MSge6JcSnSWYIniEMpiigJBhg8kQzvPx9NUp2or4= Received: by reginn.horms.nl (Postfix, from userid 7100) id 224D6940A86; Mon, 25 Mar 2019 17:36:09 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Takeshi Kihara , Simon Horman Subject: [PATCH v6 6/7] clk: renesas: r8a77990: Add Z2 clock Date: Mon, 25 Mar 2019 17:35:55 +0100 Message-Id: <20190325163556.22025-7-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Adds support for R-Car E3 (r8a77990) Z2 clock. Signed-off-by: Takeshi Kihara [simon: reworked changelog; rebased] Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- v6 [Simon Horman] - Rebase for removal of CLK_TYPE_GEN3_Z2; use CLK_TYPE_GEN3_Z instead v3 [Simon Horman] - Pass new offset parameter v2 [Simon Horman] - Initialise as programmable clock v1 [Simon Horman] - Initialise as fixed clock v0 [Takeshi Kihara] - Initialise as programmable clock --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 9a278c75c918..99f602cb30a5 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), From patchwork Mon Mar 25 16:35:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10869629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 74CA414DE for ; Mon, 25 Mar 2019 16:36:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61E4528AC1 for ; Mon, 25 Mar 2019 16:36:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 565D12948A; Mon, 25 Mar 2019 16:36:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 05BF628AC1 for ; Mon, 25 Mar 2019 16:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729673AbfCYQg0 (ORCPT ); Mon, 25 Mar 2019 12:36:26 -0400 Received: from kirsty.vergenet.net ([202.4.237.240]:42086 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725788AbfCYQg0 (ORCPT ); Mon, 25 Mar 2019 12:36:26 -0400 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id D2B0325BF19; Tue, 26 Mar 2019 03:36:12 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1553531773; bh=phw8uEK8HnTFV4y9oxe8stMiFc92itA3xZMrS4YLCXI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o3VYZkUl59o+k1ffJtXRvtgZnKdUaegwAqk5sZgPm7Qqa+hJX8kP5AgdLgTT1Ri+L xbiodtBmn3MhwdBq9UWI44HcxkVu9H9lvF3XwOKoj7PhD27czEnjzUiHC3IFhnO9/e TMv8Qi9y7QGQpyMNIU7jP6PUtqrt1154iEtX9C+Y= Received: by reginn.horms.nl (Postfix, from userid 7100) id 36D56940AAE; Mon, 25 Mar 2019 17:36:09 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Simon Horman Subject: [PATCH v6 7/7] clk: renesas: r8a774c0: Add Z2 clock Date: Mon, 25 Mar 2019 17:35:56 +0100 Message-Id: <20190325163556.22025-8-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190325163556.22025-1-horms+renesas@verge.net.au> References: <20190325163556.22025-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds support for RZ/G2E (r8a774c0) Z2 clock. Signed-off-by: Simon Horman Tested-by: Fabrizio Castro Reviewed-by: Fabrizio Castro Reviewed-by: Geert Uytterhoeven --- v6 - Rebase for removal of CLK_TYPE_GEN3_Z2; use CLK_TYPE_GEN3_Z instead - Updated Changelog v3 - New patch --- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 34e274f2a273..57098b7e3d0e 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1),