From patchwork Wed Mar 27 05:56:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872609 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6D9C91575 for ; Wed, 27 Mar 2019 05:57:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4E29A28CD7 for ; Wed, 27 Mar 2019 05:57:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4143028CDA; Wed, 27 Mar 2019 05:57:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CFF2528CD7 for ; Wed, 27 Mar 2019 05:57:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725795AbfC0F5D (ORCPT ); Wed, 27 Mar 2019 01:57:03 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6957 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbfC0F5C (ORCPT ); Wed, 27 Mar 2019 01:57:02 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:56:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:02 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:01 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:01 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:00 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 01/26] spi: tegra114: fix PIO transfer Date: Tue, 26 Mar 2019 22:56:22 -0700 Message-ID: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666217; bh=jnKCDS2+fDqhI4VcNWBwJ5VdZIxqBkvA13qxpCzyHjg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=ZpJwqJdjFA+Uhw1ZZzUlNOH9xPq8lNWqN0BCcrgV0ay9r2/zvsC5AN1iauaAGae98 TU6U/8UxcUoKDp/28KufsxY1mXQ/QwjxHPCYv4QYorMwngIMTkq4ByGCMpobfR0xs+ I4vPKTLBg83EjDiqOL9s6ypznbV+dy1HL6itryNldrrOaAp5E/RbSE/xyGKzbT8Ojo M1oMEs1rucqt1co9ty7dkpc1ObJcjrfAX869o5J8SEKqOuR/L+1OG5pBZrfBh92xfm mXh0PM9ObD7UE8PuAxiRywnahDxLv9faOvBdBYZtJyfDBYWWIkIykAl2xadyCDLiRq h93BjKvMBcu4g== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: Use PIO bit in SPI_COMMAND1 register for PIO mode. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index a76acedd7e2f..5a21bc808bb6 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -570,8 +570,9 @@ static int tegra_spi_start_cpu_based_transfer( tspi->is_curr_dma_xfer = false; - val |= SPI_DMA_EN; - tegra_spi_writel(tspi, val, SPI_DMA_CTL); + val = tspi->command1_reg; + val |= SPI_PIO; + tegra_spi_writel(tspi, val, SPI_COMMAND1); return 0; } From patchwork Wed Mar 27 05:56:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDFCC139A for ; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D85FA26B41 for ; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id CCA31271FD; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8534926B41 for ; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732249AbfC0F5F (ORCPT ); Wed, 27 Mar 2019 01:57:05 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6965 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbfC0F5E (ORCPT ); Wed, 27 Mar 2019 01:57:04 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:56:58 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:03 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:03 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:03 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:03 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:02 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 02/26] spi: tegra114: clear packed bit for unpacked mode Date: Tue, 26 Mar 2019 22:56:23 -0700 Message-ID: <1553666207-11414-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666218; bh=6yXtfBMzY0mBKehXBhCNAfLgdVnlj0a4JIk5jPR7MxA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=bI/IREsxtcA2TJZCPz49O6IJ4i9w8T7Dy8iePmNwEvE2uyXyK8PG3zi+Bnd6pB8O0 Ffip77nDGT4tLpX04y7AzDytNEMf3v5+SCFQ9UxR7qrL8KEWZzqPBJelLor6w8BOWf V0H/xNhgrrgc+CMUJIEkURM4rfGwT0toPt/QQEBHtMvj7tBP9aYVemkhRsQF00qqaj Jpf3MpRE3kTpZd240IVb9NlVj7XsgweCgoosH5AFFeOqz47CtFOpLWT0OWGIpqFjrl pf5KSXoE2btLP5O+1xUpboMNUt/FjcMV6xDO5ib2EBbWBPYbGyXmiZoD6uLjPiblzp Yr8EfUAuE/2Xw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: Clear packed bit when not using packed mode. Packed bit is not cleared when not using packed mode. This results in transfer timeouts for the unpacked mode transfers followed by the packed mode transfers. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 5a21bc808bb6..82431115b7c0 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -731,6 +731,8 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, if (tspi->is_packed) command1 |= SPI_PACKED; + else + command1 &= ~SPI_PACKED; command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN); tspi->cur_direction = 0; From patchwork Wed Mar 27 05:56:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50D891874 for ; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C4CD26B41 for ; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2F810271FD; Wed, 27 Mar 2019 05:59:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C30527165 for ; Wed, 27 Mar 2019 05:59:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732659AbfC0F5I (ORCPT ); Wed, 27 Mar 2019 01:57:08 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6978 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbfC0F5I (ORCPT ); Wed, 27 Mar 2019 01:57:08 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:00 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:05 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:05 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:05 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:05 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:04 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 03/26] spi: tegra114: fix for unpacked mode transfers Date: Tue, 26 Mar 2019 22:56:24 -0700 Message-ID: <1553666207-11414-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666221; bh=BbVb8qftn7ikNLmb5ZIGDeTbmYh2XNlqSyxXW/Zu/c0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=axejtihWJbqmbiQ0LGd5Rtd7ZeSjDXpSfmJnajsJBjF4ZWNL/hqBRQcd6uS6MUiwF TCeQIVZfc/ve4VLXSSZiwBAfRN5Gu7zwgSEJsuyvC938rjhpI1f2jDTpmUUgdjXkxS HkULBVveETpJMV3easuid77NEPhN6Qfadw19/Pb2RVterxOP2KHDH0o1sb0Zo0R8lX 15FYc0ZGg+wl1wY2WoboSgeSpCKRrYUkr9xDCUoTU9uV66lCriGeuVu1lId4jyzckR pzeQENAkzfrOkxa3S/AHi934W5YugGrtlO9nItX63rq4XuKXNiOWJE3I1/PPrvMA8f cpeCw37Pzln/w== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked mode when transfer length is not a multiple of requested bits per word. unpacked mode transfers fails when the transfer includes partial bytes in the last word. Total words to be written/read to/from FIFO is computed based on transfer length and bits per word. Unpacked mode includes 0 padding bytes for partial words to align with bits per word and these extra bytes are also accounted for calculating bytes left to transfer in the current driver. This causes extra bytes access of tx/rx buffers along with buffer index position crossing actual length where remain_len becomes negative and due to unsigned type, negative value is a 32 bit representation of signed value and transferred bytes never meets the actual transfer length resulting in transfer timeout and a hang. This patch fixes this with proper computation of the actual bytes to fill in FIFO during transmit and the actual bytes to read from FIFO during receive ignoring 0 padded bytes. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 43 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 82431115b7c0..fdba302eb3b6 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -307,10 +307,16 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf( x |= (u32)(*tx_buf++) << (i * 8); tegra_spi_writel(tspi, x, SPI_TX_FIFO); } + + tspi->cur_tx_pos += written_words * tspi->bytes_per_word; } else { + unsigned int write_bytes; max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); written_words = max_n_32bit; nbytes = written_words * tspi->bytes_per_word; + if (nbytes > t->len - tspi->cur_pos) + nbytes = t->len - tspi->cur_pos; + write_bytes = nbytes; for (count = 0; count < max_n_32bit; count++) { u32 x = 0; @@ -319,8 +325,10 @@ static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf( x |= (u32)(*tx_buf++) << (i * 8); tegra_spi_writel(tspi, x, SPI_TX_FIFO); } + + tspi->cur_tx_pos += write_bytes; } - tspi->cur_tx_pos += written_words * tspi->bytes_per_word; + return written_words; } @@ -344,20 +352,27 @@ static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf( for (i = 0; len && (i < 4); i++, len--) *rx_buf++ = (x >> i*8) & 0xFF; } - tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; read_words += tspi->curr_dma_words; + tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; } else { u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; + u8 bytes_per_word = tspi->bytes_per_word; + unsigned int read_bytes; + len = rx_full_count * bytes_per_word; + if (len > t->len - tspi->cur_pos) + len = t->len - tspi->cur_pos; + read_bytes = len; for (count = 0; count < rx_full_count; count++) { u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask; - for (i = 0; (i < tspi->bytes_per_word); i++) + for (i = 0; len && (i < bytes_per_word); i++, len--) *rx_buf++ = (x >> (i*8)) & 0xFF; } - tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; read_words += rx_full_count; + tspi->cur_rx_pos += read_bytes; } + return read_words; } @@ -372,12 +387,17 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf( unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); + tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; } else { unsigned int i; unsigned int count; u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; + unsigned int write_bytes; + if (consume > t->len - tspi->cur_pos) + consume = t->len - tspi->cur_pos; + write_bytes = consume; for (count = 0; count < tspi->curr_dma_words; count++) { u32 x = 0; @@ -386,8 +406,9 @@ static void tegra_spi_copy_client_txbuf_to_spi_txbuf( x |= (u32)(*tx_buf++) << (i * 8); tspi->tx_dma_buf[count] = x; } + + tspi->cur_tx_pos += write_bytes; } - tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; /* Make the dma buffer to read by dma */ dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, @@ -405,20 +426,28 @@ static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf( unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); + tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; } else { unsigned int i; unsigned int count; unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; + unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; + unsigned int read_bytes; + if (consume > t->len - tspi->cur_pos) + consume = t->len - tspi->cur_pos; + read_bytes = consume; for (count = 0; count < tspi->curr_dma_words; count++) { u32 x = tspi->rx_dma_buf[count] & rx_mask; - for (i = 0; (i < tspi->bytes_per_word); i++) + for (i = 0; consume && (i < tspi->bytes_per_word); + i++, consume--) *rx_buf++ = (x >> (i*8)) & 0xFF; } + + tspi->cur_rx_pos += read_bytes; } - tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; /* Make the dma buffer to read by dma */ dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, From patchwork Wed Mar 27 05:56:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872655 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E9B35139A for ; Wed, 27 Mar 2019 05:59:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D633A26B41 for ; Wed, 27 Mar 2019 05:59:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C94C027E71; Wed, 27 Mar 2019 05:59:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7AD7C26B41 for ; Wed, 27 Mar 2019 05:59:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732715AbfC0F5I (ORCPT ); Wed, 27 Mar 2019 01:57:08 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17586 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732652AbfC0F5I (ORCPT ); Wed, 27 Mar 2019 01:57:08 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:10 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:07 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:07 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:07 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:07 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:06 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 04/26] spi: tegra114: use packed mode for 32 bits per word Date: Tue, 26 Mar 2019 22:56:25 -0700 Message-ID: <1553666207-11414-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; 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Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index fdba302eb3b6..dc63536dbda4 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -259,7 +259,7 @@ static unsigned tegra_spi_calculate_curr_xfer_param( tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); - if (bits_per_word == 8 || bits_per_word == 16) { + if (bits_per_word == 8 || bits_per_word == 16 || bits_per_word == 32) { tspi->is_packed = 1; tspi->words_per_32bit = 32/bits_per_word; } else { From patchwork Wed Mar 27 05:56:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872653 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 89D4B139A for ; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 743F126B41 for ; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 676D027FB0; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1ED9227165 for ; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732893AbfC0F5N (ORCPT ); Wed, 27 Mar 2019 01:57:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6986 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732858AbfC0F5K (ORCPT ); Wed, 27 Mar 2019 01:57:10 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:04 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:09 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:09 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:09 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:09 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:08 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 05/26] spi: tegra114: use unpacked mode for below 4 byte transfers Date: Tue, 26 Mar 2019 22:56:26 -0700 Message-ID: <1553666207-11414-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666224; bh=cDlXRQ1SN0n4d4SYvS+kdGr6T1K5bo/hbYzbW8FRIE4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=atBYM16PptrKQak4TkTQ++oDUsmQfq7yJAU7zxMZvI3NOI9Z1uSHyNgp1mvoCCgCY dxCg1iV4lsHg9ev0VEgTygAK/2W8kdhXRvKqF+xb7J3sDAj2FOHOtFqE2S3FrwgROT CINe/bI+oN2AFiT3eGi2UIz1aLE4YPl53zjAEU7DZM9e65uVGmhV5KLOsGTH+wuJPO kNADggy5naj0zrRHrJZCxB+mTjTyH7+TvP206sfSpuDtc2eSi4VoziEx5ct9NiPJHj g0rnnenaeQXb3dSrCfeHRpTap4zTLe5MynEMH4k51d+zGtfM54S2xJw6474ZXUSqHL 6jyjBGXBo5rNA== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: use unpacked mode when transfer length is less than 4 bytes. Packed mode expects minimum transfer length of 4 bytes. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index dc63536dbda4..716587b663a3 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -259,7 +259,8 @@ static unsigned tegra_spi_calculate_curr_xfer_param( tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); - if (bits_per_word == 8 || bits_per_word == 16 || bits_per_word == 32) { + if ((bits_per_word == 8 || bits_per_word == 16 || + bits_per_word == 32) && t->len > 3) { tspi->is_packed = 1; tspi->words_per_32bit = 32/bits_per_word; } else { From patchwork Wed Mar 27 05:56:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6BDF81575 for ; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56EBC26B41 for ; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4B0F427E71; Wed, 27 Mar 2019 05:59:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F298D26B41 for ; Wed, 27 Mar 2019 05:59:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732932AbfC0F5N (ORCPT ); Wed, 27 Mar 2019 01:57:13 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17592 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732652AbfC0F5M (ORCPT ); Wed, 27 Mar 2019 01:57:12 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:11 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:11 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:11 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:11 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:11 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:10 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 06/26] spi: tegra114: terminate dma and reset on transfer timeout Date: Tue, 26 Mar 2019 22:56:27 -0700 Message-ID: <1553666207-11414-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666235; bh=i8+ndFb16vHMuRawNGbZAarN3wV094Dxo/2p5bGP8Z4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ZI30UY6atBAsnOp5Gv7GSj14N2NbaxSBiVIUugbyTlZ7j8usygD/+/OvPlE2r2Nac ntg7LMlUUDlE13ao8WvKP1jiOPmYWb7HgIJjl2i1gGOUZhC5w/CiS81TvgVRAnYJqa zujLPDyG53S38UA8Meev0Aw/W8yFpQgdzOpDJio9SOx7vLOhnYcrLxWCT7UidPJY1P ZMA8x8o7JHDeW8woq05JgvhV8gzoElYMGxO//FsKXadyFgZseQE4va4lg4zPEkx/Oy IPJ+FzOt5ND0rU9XJX5ZGhmiuvByvmmjRt4be4G1N9q9Lb4XkBTsdWml6sJK/bqPQq Bh5txVnWtU4eA== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: terminate DMA and perform controller reset on transfer timeout to clear the FIFO's and errors. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 716587b663a3..0d20fc489134 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -871,7 +871,16 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, if (WARN_ON(ret == 0)) { dev_err(tspi->dev, "spi transfer timeout, err %d\n", ret); + if (tspi->is_curr_dma_xfer && + (tspi->cur_direction & DATA_DIR_TX)) + dmaengine_terminate_all(tspi->tx_dma_chan); + if (tspi->is_curr_dma_xfer && + (tspi->cur_direction & DATA_DIR_RX)) + dmaengine_terminate_all(tspi->rx_dma_chan); ret = -EIO; + reset_control_assert(tspi->rst); + udelay(2); + reset_control_deassert(tspi->rst); goto complete_xfer; } From patchwork Wed Mar 27 05:56:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872613 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B7977139A for ; Wed, 27 Mar 2019 05:57:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A259328CD7 for ; Wed, 27 Mar 2019 05:57:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 965CA28CDA; Wed, 27 Mar 2019 05:57:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C3F928CD7 for ; Wed, 27 Mar 2019 05:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733002AbfC0F5S (ORCPT ); Wed, 27 Mar 2019 01:57:18 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6212 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732949AbfC0F5P (ORCPT ); Wed, 27 Mar 2019 01:57:15 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:11 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:13 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:13 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:12 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:13 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:12 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 07/26] spi: tegra114: flush fifos Date: Tue, 26 Mar 2019 22:56:28 -0700 Message-ID: <1553666207-11414-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666231; bh=KT+g1+XtGBOoIwtSTct5X3UtWlKCsnsfrJ1PHIdXCrM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=ikKF5eImpkqRykDrH5TVc8VAhGcQErnQee0t85zBjzJKM8N1GmPB7aU9Y4V8xvp1R c963/47ieYxUP2RlIsCSBCH85mTc1FWkZVb1FJrk7zdCDPl5oIExChIeyhBRRz+GlD KQyJovyeWaoLFmLbk+TMHLfpIWfpwhn2nTnK22MIYMkdX4dVYKKZjCHFhYENTImkrF E0hoMapl2nKMS6XI5NzsTlocXgnFQ/5fetnv752kYSSb0dm8llgdj0PFixyKmhIQTr glDf7tT1x2Q1PE8c8tKXT+aeopVYTc8De9RVHISMIz0KCGecQQUXIrMtwFUl4I8Ti8 +SxtQXWXm9DDQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO overflow or underrun errors. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 0d20fc489134..477828051aba 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -500,22 +500,37 @@ static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len) return 0; } -static int tegra_spi_start_dma_based_transfer( - struct tegra_spi_data *tspi, struct spi_transfer *t) +static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi) { - u32 val; - unsigned int len; - int ret = 0; + unsigned long timeout = jiffies + HZ; u32 status; - /* Make sure that Rx and Tx fifo are empty */ status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) { - dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", - (unsigned)status); - return -EIO; + status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH; + tegra_spi_writel(tspi, status, SPI_FIFO_STATUS); + while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) { + status = tegra_spi_readl(tspi, SPI_FIFO_STATUS); + if (time_after(jiffies, timeout)) { + dev_err(tspi->dev, + "timeout waiting for fifo flush\n"); + return -EIO; + } + + udelay(1); + } } + return 0; +} + +static int tegra_spi_start_dma_based_transfer( + struct tegra_spi_data *tspi, struct spi_transfer *t) +{ + u32 val; + unsigned int len; + int ret = 0; + val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); tegra_spi_writel(tspi, val, SPI_DMA_BLK); @@ -781,6 +796,9 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n", tspi->def_command1_reg, (unsigned)command1); + ret = tegra_spi_flush_fifos(tspi); + if (ret < 0) + return ret; if (total_fifo_words > SPI_FIFO_DEPTH) ret = tegra_spi_start_dma_based_transfer(tspi, t); else @@ -878,6 +896,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, (tspi->cur_direction & DATA_DIR_RX)) dmaengine_terminate_all(tspi->rx_dma_chan); ret = -EIO; + tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); reset_control_deassert(tspi->rst); @@ -931,6 +950,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) tspi->status_reg); dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", tspi->command1_reg, tspi->dma_control_reg); + tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); reset_control_deassert(tspi->rst); @@ -1003,6 +1023,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) tspi->status_reg); dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", tspi->command1_reg, tspi->dma_control_reg); + tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); reset_control_deassert(tspi->rst); From patchwork Wed Mar 27 05:56:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872611 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D5BF01575 for ; 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Tue, 26 Mar 2019 22:57:14 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 08/26] spi: tegra114: configure dma burst size to fifo trig level Date: Tue, 26 Mar 2019 22:56:29 -0700 Message-ID: <1553666207-11414-8-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666239; bh=Nj/elAeLdFMfOLAFpS3A87IYAOW4dTIKTWuFL3/8PDU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DdyW7rCIuI4ONDCFGL/Z66ZHjs7Zkj1SJzl67O1fs2Jpktcwu9YPrgxeULbm0PJpb 3bK0jj7HTimvIzZVG1OGcgHtsqsX9QAV2c4FkWgRURUE4GKJR3QyAn4dzbydoJp+8z 4uCj3nc5JeUg6yIkXfLKQ/fBYxmwd9/lH01dRxIqxAZVOAqvpfwY5Ezvmz5L3wUAGT edWM2+Zq2AlT+zslCjDWYdKjzYHlI36VIW6nnFpzHNK4HMLmyLYP04Eba6VxJmtI5T G15+MUyG/RZO4QygwwMXMhiuyV///lsoJ/IWWYWpfFMh6/wilWHz58JPMzPkLqDf5L hUe+kOCP7BejQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels to avoid mismatch. SPI FIFO trigger levels are calculated based on the transfer length. So this patch moves DMA slave configuration to happen before start of DMAs. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 52 ++++++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 477828051aba..b7e71676a506 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -530,6 +530,8 @@ static int tegra_spi_start_dma_based_transfer( u32 val; unsigned int len; int ret = 0; + u8 dma_burst; + struct dma_slave_config dma_sconfig = {0}; val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1); tegra_spi_writel(tspi, val, SPI_DMA_BLK); @@ -541,12 +543,16 @@ static int tegra_spi_start_dma_based_transfer( len = tspi->curr_dma_words * 4; /* Set attention level based on length of transfer */ - if (len & 0xF) + if (len & 0xF) { val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1; - else if (((len) >> 4) & 0x1) + dma_burst = 1; + } else if (((len) >> 4) & 0x1) { val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4; - else + dma_burst = 4; + } else { val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8; + dma_burst = 8; + } if (tspi->cur_direction & DATA_DIR_TX) val |= SPI_IE_TX; @@ -557,7 +563,18 @@ static int tegra_spi_start_dma_based_transfer( tegra_spi_writel(tspi, val, SPI_DMA_CTL); tspi->dma_control_reg = val; + dma_sconfig.device_fc = true; if (tspi->cur_direction & DATA_DIR_TX) { + dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; + dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.dst_maxburst = dma_burst; + ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tspi->dev, + "DMA slave config failed: %d\n", ret); + return ret; + } + tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t); ret = tegra_spi_start_tx_dma(tspi, len); if (ret < 0) { @@ -568,6 +585,16 @@ static int tegra_spi_start_dma_based_transfer( } if (tspi->cur_direction & DATA_DIR_RX) { + dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; + dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_sconfig.src_maxburst = dma_burst; + ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig); + if (ret < 0) { + dev_err(tspi->dev, + "DMA slave config failed: %d\n", ret); + return ret; + } + /* Make the dma buffer to read by dma */ dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, tspi->dma_buf_size, DMA_FROM_DEVICE); @@ -628,7 +655,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, u32 *dma_buf; dma_addr_t dma_phys; int ret; - struct dma_slave_config dma_sconfig; dma_chan = dma_request_slave_channel_reason(tspi->dev, dma_to_memory ? "rx" : "tx"); @@ -649,19 +675,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, } if (dma_to_memory) { - dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO; - dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.src_maxburst = 0; - } else { - dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO; - dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.dst_maxburst = 0; - } - - ret = dmaengine_slave_config(dma_chan, &dma_sconfig); - if (ret) - goto scrub; - if (dma_to_memory) { tspi->rx_dma_chan = dma_chan; tspi->rx_dma_buf = dma_buf; tspi->rx_dma_phys = dma_phys; @@ -671,11 +684,6 @@ static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi, tspi->tx_dma_phys = dma_phys; } return 0; - -scrub: - dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); - dma_release_channel(dma_chan); - return ret; } static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, From patchwork Wed Mar 27 05:56:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8B2791575 for ; Wed, 27 Mar 2019 05:59:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 76A9326B41 for ; Wed, 27 Mar 2019 05:59:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6A555271FD; Wed, 27 Mar 2019 05:59:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 56CF826B41 for ; Wed, 27 Mar 2019 05:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387569AbfC0F7M (ORCPT ); Wed, 27 Mar 2019 01:59:12 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6222 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732984AbfC0F5R (ORCPT ); Wed, 27 Mar 2019 01:57:17 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:15 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:16 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:16 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:16 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:15 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout Date: Tue, 26 Mar 2019 22:56:30 -0700 Message-ID: <1553666207-11414-9-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666235; bh=s3KHjtXt1zgMVIUGUGMHh6JDkD3XIJDHG16DAqm1T5E=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=mQNFKuSWUt7o8ySMVu83+C+6TThCIQ+08xb1KF5FDL4ECUs+ok4epFohew92dasaU gAIGVk8TK8dUGXCYEz5M4gEoL4xlhHu0x9/LIRE0bhhGQoQ7oPxhdFsInCcYwpgjT4 WXM3y2FjxSOwm79zfY2wlKwtvbw35FFXEx6dhcfoulWWo76jc8JGIU4EiuxgpsgvuX /rgwq6hI0VmVj/0aYzMRoNjVfCgn0InF9P2+uGlSqQZV+oLFTvo0RUNtfiHYWVDqgm TuFPvKJLexhDNfEDACcm1d1O8doIpwhBFfrOl4GeTgnCrhJSm/xqn1OqjiB08f3e9K mXndgojDE+jkA== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch dumps SPI registers on DMA or transfer timeout for debug purpose. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index b7e71676a506..268a790a663e 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -858,6 +858,20 @@ static void tegra_spi_transfer_delay(int delay) udelay(delay % 1000); } +static void tegra_spi_dump_regs(struct tegra_spi_data *tspi) +{ + dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n"); + dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n", + tegra_spi_readl(tspi, SPI_COMMAND1), + tegra_spi_readl(tspi, SPI_COMMAND2)); + dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n", + tegra_spi_readl(tspi, SPI_DMA_CTL), + tegra_spi_readl(tspi, SPI_DMA_BLK)); + dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n", + tegra_spi_readl(tspi, SPI_TRANS_STATUS), + tegra_spi_readl(tspi, SPI_FIFO_STATUS)); +} + static int tegra_spi_transfer_one_message(struct spi_master *master, struct spi_message *msg) { @@ -904,6 +918,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, (tspi->cur_direction & DATA_DIR_RX)) dmaengine_terminate_all(tspi->rx_dma_chan); ret = -EIO; + tegra_spi_dump_regs(tspi); tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); @@ -913,6 +928,7 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, if (tspi->tx_status || tspi->rx_status) { dev_err(tspi->dev, "Error in Transfer\n"); + tegra_spi_dump_regs(tspi); ret = -EIO; goto complete_xfer; } @@ -958,6 +974,7 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) tspi->status_reg); dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n", tspi->command1_reg, tspi->dma_control_reg); + tegra_spi_dump_regs(tspi); tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); @@ -1031,6 +1048,7 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) tspi->status_reg); dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n", tspi->command1_reg, tspi->dma_control_reg); + tegra_spi_dump_regs(tspi); tegra_spi_flush_fifos(tspi); reset_control_assert(tspi->rst); udelay(2); From patchwork Wed Mar 27 05:56:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872647 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 05598139A for ; Wed, 27 Mar 2019 05:59:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E158F28CD7 for ; Wed, 27 Mar 2019 05:59:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D407328CDE; Wed, 27 Mar 2019 05:59:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7458B28CD7 for ; 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Wed, 27 Mar 2019 05:57:18 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:17 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 10/26] spi: tegra114: avoid reset call in atomic context Date: Tue, 26 Mar 2019 22:56:31 -0700 Message-ID: <1553666207-11414-10-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666233; bh=dOcLXRlYLfLbnWb83E/qzVVgUeO0EyFlz/F9ooYBdVI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=naCNHHhrpSmwHaQucT7wQxWJ6rn4UePbf/JIck0AigxVqsVOKTvScN18SmBdlMyGo 0dZWcrFQiFXbVG+6L6gbUE9ffNV2iBt52G8z60YnF49BI1WMLB1xMvugAJ+N6txY1s Bi+PrdsHuBtLGGaiP6OZWvGOR8u9bUTwU/mylvlqxeEfqe5TkQsl6bIBo1OCwDIFk3 83blkGVm467xht65XJ45i9B17hbPbRGQRlyks8z/HHhYeQLZ3QJ0A7uvIYeArP99m+ dtB0xCnByDKCule7/XSDcp7NFisiCB7lAuGiEFr6zX/EQNIDiuaBujbnqxcrwBgpHE cp23zQ8ZpLMSQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: move SPI controller reset out of spin lock. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 268a790a663e..5523936b21f5 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -976,11 +976,12 @@ static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi) tspi->command1_reg, tspi->dma_control_reg); tegra_spi_dump_regs(tspi); tegra_spi_flush_fifos(tspi); + complete(&tspi->xfer_completion); + spin_unlock_irqrestore(&tspi->lock, flags); reset_control_assert(tspi->rst); udelay(2); reset_control_deassert(tspi->rst); - complete(&tspi->xfer_completion); - goto exit; + return IRQ_HANDLED; } if (tspi->cur_direction & DATA_DIR_RX) @@ -1050,11 +1051,11 @@ static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi) tspi->command1_reg, tspi->dma_control_reg); tegra_spi_dump_regs(tspi); tegra_spi_flush_fifos(tspi); + complete(&tspi->xfer_completion); + spin_unlock_irqrestore(&tspi->lock, flags); reset_control_assert(tspi->rst); udelay(2); reset_control_deassert(tspi->rst); - complete(&tspi->xfer_completion); - spin_unlock_irqrestore(&tspi->lock, flags); return IRQ_HANDLED; } From patchwork Wed Mar 27 05:56:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872645 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E06921575 for ; Wed, 27 Mar 2019 05:59:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C96E728CD7 for ; Wed, 27 Mar 2019 05:59:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BD20728CDE; Wed, 27 Mar 2019 05:59:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5914828CD7 for ; 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Wed, 27 Mar 2019 05:57:20 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:20 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:19 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 11/26] spi: tegra114: reset controller on probe Date: Tue, 26 Mar 2019 22:56:32 -0700 Message-ID: <1553666207-11414-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666239; bh=XOOfuDefqq5ngbWhNxsWlTHkCm/Rd/ZkGBVSxxex63c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=WWhwB3eAdBq5t4JBb6Y7ZKcJgZnQAFDZU4Rr5Bb0xbcstFP5waI0ez6yCQCAwB1HF M6+l3JgGQlsfuIyCrS+jNSDXlxyc7GUQlf8BkwRhZBt82owp/0up2RJ1Js0mcgEkAE h+JZpdnkzQu7BDP/M6JRD02V27VUZMaBINOm4IanOVfCJVejy9ZFGbLaeVA+rAm/UW wxk5CB2372SyHIGh7PUFMayMZLFb9HfVWYF12cOfjWvNC56F+JCAJ+Q9I/cUmWFzB2 Vb279o9/sp6DVjk4DrJPaogWjVnZjvd6+xnb/EiHNbxmE03E4L4aR4MsFybcZu5vSG +mzsXH14lWAUg== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fixes: SPI driver can be built as module so perform SPI controller reset on probe to make sure it is in valid state before initiating transfer. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 5523936b21f5..0e228f1e910e 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -1157,27 +1157,19 @@ static int tegra_spi_probe(struct platform_device *pdev) spi_irq = platform_get_irq(pdev, 0); tspi->irq = spi_irq; - ret = request_threaded_irq(tspi->irq, tegra_spi_isr, - tegra_spi_isr_thread, IRQF_ONESHOT, - dev_name(&pdev->dev), tspi); - if (ret < 0) { - dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", - tspi->irq); - goto exit_free_master; - } tspi->clk = devm_clk_get(&pdev->dev, "spi"); if (IS_ERR(tspi->clk)) { dev_err(&pdev->dev, "can not get clock\n"); ret = PTR_ERR(tspi->clk); - goto exit_free_irq; + goto exit_free_master; } tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); if (IS_ERR(tspi->rst)) { dev_err(&pdev->dev, "can not get reset\n"); ret = PTR_ERR(tspi->rst); - goto exit_free_irq; + goto exit_free_master; } tspi->max_buf_size = SPI_FIFO_DEPTH << 2; @@ -1185,7 +1177,7 @@ static int tegra_spi_probe(struct platform_device *pdev) ret = tegra_spi_init_dma_param(tspi, true); if (ret < 0) - goto exit_free_irq; + goto exit_free_master; ret = tegra_spi_init_dma_param(tspi, false); if (ret < 0) goto exit_rx_dma_free; @@ -1207,18 +1199,32 @@ static int tegra_spi_probe(struct platform_device *pdev) dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); goto exit_pm_disable; } + + reset_control_assert(tspi->rst); + udelay(2); + reset_control_deassert(tspi->rst); tspi->def_command1_reg = SPI_M_S; tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); pm_runtime_put(&pdev->dev); + ret = request_threaded_irq(tspi->irq, tegra_spi_isr, + tegra_spi_isr_thread, IRQF_ONESHOT, + dev_name(&pdev->dev), tspi); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", + tspi->irq); + goto exit_pm_disable; + } master->dev.of_node = pdev->dev.of_node; ret = devm_spi_register_master(&pdev->dev, master); if (ret < 0) { dev_err(&pdev->dev, "can not register to master err %d\n", ret); - goto exit_pm_disable; + goto exit_free_irq; } return ret; +exit_free_irq: + free_irq(spi_irq, tspi); exit_pm_disable: pm_runtime_disable(&pdev->dev); if (!pm_runtime_status_suspended(&pdev->dev)) @@ -1226,8 +1232,6 @@ static int tegra_spi_probe(struct platform_device *pdev) tegra_spi_deinit_dma_param(tspi, false); exit_rx_dma_free: tegra_spi_deinit_dma_param(tspi, true); -exit_free_irq: - free_irq(spi_irq, tspi); exit_free_master: spi_master_put(master); return ret; From patchwork Wed Mar 27 05:56:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872643 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13B7F1575 for ; Wed, 27 Mar 2019 05:58:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F376728CD7 for ; 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Tue, 26 Mar 2019 22:57:20 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:22 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:22 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:22 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:21 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:21 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:21 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 12/26] spi: tegra114: add SPI_LSB_FIRST support Date: Tue, 26 Mar 2019 22:56:33 -0700 Message-ID: <1553666207-11414-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666240; bh=WzENTHCRfV1Ar8i1tgLhzT35ys8oaN1gLEZymgIl3jE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=oXI9FNA8IZ47oJrstEU7HzSCPD7U5o309RME92Tcgg8jZNBblrLvw2/bCSn5QmUKs ZoBlAbJOLvuFwd0XyOt1vowD9VkZz68VrMPqk2cH+amkUnLoNFE79JGW9H8Hg2ge23 +4Cv7MMyY/q+tdCRlgbw28T2oUFVE1KJ8VQGYzzssZFuDDU6lLE8hu2Gl8xaHng54q DPRqNOCGiWRtRlQAT3s2YUQQFR17ZCmXBp3s01DgcfgvqwpO5zhzl7+IQ0pMdb0Z7L Vl7Hwy7cDtZsaToiYd15AHaie7ASQiYb2Y6rKazD5AG11DLl0aJtMhByWAbmTvrWwf 563fOstPPtCvQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 0e228f1e910e..d39f7b05b824 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -750,6 +750,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else if (req_mode == SPI_MODE_3) command1 |= SPI_CONTROL_MODE_3; + if (spi->mode & SPI_LSB_FIRST) + command1 |= SPI_LSBIT_FE; + else + command1 &= ~SPI_LSBIT_FE; + if (tspi->cs_control) { if (tspi->cs_control != spi) tegra_spi_writel(tspi, command1, SPI_COMMAND1); @@ -1137,7 +1142,7 @@ static int tegra_spi_probe(struct platform_device *pdev) master->max_speed_hz = 25000000; /* 25MHz */ /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; From patchwork Wed Mar 27 05:56:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872641 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C1DF7139A for ; Wed, 27 Mar 2019 05:58:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AA2FA28CD7 for ; Wed, 27 Mar 2019 05:58:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9E64728CDA; Wed, 27 Mar 2019 05:58:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4833C28CD7 for ; Wed, 27 Mar 2019 05:58:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733121AbfC0F50 (ORCPT ); Wed, 27 Mar 2019 01:57:26 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17608 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733086AbfC0F5Y (ORCPT ); Wed, 27 Mar 2019 01:57:24 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:27 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:24 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:24 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:23 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:23 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:23 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:22 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 13/26] spi: tegra114: add dual mode support Date: Tue, 26 Mar 2019 22:56:34 -0700 Message-ID: <1553666207-11414-13-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666247; bh=gLDxLguUtkZngVQg1d51ZG6XgZGuaEBgMnBe1HRDfsE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=T8d7grJL07T8ufERmYx7JmEtEBumKI5+SkakLzRr8UZo3xxwM2tUkNaTZ8F/8fR6i bCkSNSpB2ELs4teYtQjObVdHaLhE69JJbdsrxnnlvhaJ5C4Faaz//tolkSObP9ul51 XmAHVEUYcwS1B/B+Kw9MJbKBdFNsFa6QOZWh3ghyiSKc4IATxRCPJxkh0Fhizy697G tF0l1QO41IVFAPxkEzMB9HiqphKdRMv2i8OCyMNOmiQ3zjNVYO1aNSf3PZz+JekPsE tUHVZ18/0Bws+YsYwk79jkAzD5XNJ20moHyjypjwmKLO7XncECakl0TCXJlxA8Ympb sjhlKawN5HZKw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for dual mode SPI transfer. Dual mode uses both MOSI and MISO lines in parallel where the data is interleaved on MOSI and MISO lines increasing the throughput. Packet from Tx FIFO is transmitted on both MOSI and MISO lines and packet to Rx FIFO is received from both MOSI and MISO lines. Even bits are transmitted or received on the MOSI data line and odd bits are transmitted or received on the MISO data line. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index d39f7b05b824..335c594d5b74 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -787,6 +787,11 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t); + if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL) + command1 |= SPI_BOTH_EN_BIT; + else + command1 &= ~SPI_BOTH_EN_BIT; + if (tspi->is_packed) command1 |= SPI_PACKED; else @@ -1142,7 +1147,8 @@ static int tegra_spi_probe(struct platform_device *pdev) master->max_speed_hz = 25000000; /* 25MHz */ /* the spi->mode bits understood by this driver: */ - master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | + SPI_TX_DUAL | SPI_RX_DUAL; master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; From patchwork Wed Mar 27 05:56:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872639 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 46755139A for ; Wed, 27 Mar 2019 05:58:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2CAE328CD8 for ; Wed, 27 Mar 2019 05:58:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 20F5728CDA; Wed, 27 Mar 2019 05:58:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C458628CDE for ; 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Wed, 27 Mar 2019 05:57:25 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:25 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:24 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 14/26] spi: tegra114: add 3 wire transfer mode support Date: Tue, 26 Mar 2019 22:56:35 -0700 Message-ID: <1553666207-11414-14-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666249; bh=dqiaYl9e3e2zWmKkKdtYcyIMQJtt/a5spEADASNXdDQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=FcqSXsxh41eoJ+7DDjQp17apzKFbNHw2Z9svxwaygDOCnpdnTEf3Bc+NRqE6VRTrq uzEPyhfZGFOdELP8D319CpFeqdCuP9q7eS8MV2m2ZSbuz3RpA68n0jADYqTLmZAAOW Twggz3mimHDmVzawpRkzHbqNxfMY9iO62hl7JYNqMstqwwaT/63m0smorBJK62evGs QLnNq97CWVhB4QcHlVt0jLYS/9ObDo2+6sBKnCJcfu/peGeOc+Bu8MAf9UAf0Dcs36 3Dus0U21CQVp6zPw0lY594CHRH6ugWlcNr6EnGHoyJD0Rcr4QzhXEVWAkpq1x4CbbG XvG76s92kInXQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds 3 wire transfer support to SPI mode list and also implements it. 3 wire or Bi-directional mode uses only one serial data pin for the transfer. SPI in master mode uses MOSI data line only and MISO data line is not used by the SPI. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 335c594d5b74..01efb615a196 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -755,6 +755,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else command1 &= ~SPI_LSBIT_FE; + if (spi->mode & SPI_3WIRE) + command1 |= SPI_BIDIROE; + else + command1 &= ~SPI_BIDIROE; + if (tspi->cs_control) { if (tspi->cs_control != spi) tegra_spi_writel(tspi, command1, SPI_COMMAND1); @@ -1148,7 +1153,7 @@ static int tegra_spi_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | - SPI_TX_DUAL | SPI_RX_DUAL; + SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; From patchwork Wed Mar 27 05:56:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872637 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E6CC1575 for ; Wed, 27 Mar 2019 05:58:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E95DC28CD7 for ; Wed, 27 Mar 2019 05:58:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DBBB128CDA; Wed, 27 Mar 2019 05:58:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9177628CD7 for ; Wed, 27 Mar 2019 05:58:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733171AbfC0F53 (ORCPT ); Wed, 27 Mar 2019 01:57:29 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6246 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733161AbfC0F52 (ORCPT ); Wed, 27 Mar 2019 01:57:28 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:27 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:27 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:27 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:27 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:27 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:26 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 15/26] spi: tegra114: set supported bits_per_word Date: Tue, 26 Mar 2019 22:56:36 -0700 Message-ID: <1553666207-11414-15-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666246; bh=FqWacQcKCC1NOLc+TEjLZo+749IlFaDK7ZnSCU/kNd4=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Y4E1hncqFFG7RJ08BMWhvN3nLiqiay3iDMniJQw+V5hqELpknTuRnLQ/kGL8Nj8Rx w5ZiMyUh5By7c1el8+1d6Ql7/jXlpDpBTew6YkVdcQcrTJh/y1taTH6k2MDjt5EYZL oQMrDC6l2MBmRCWY7vqWkxO+uDIsjvbNqCWfXcYVaX5x6AUN7dTsTUxVqa63eLtiu5 b1OBBMZdHsudmPy8yfWP9kpZZin8+4USGsE+jpzi1BMlGV16zyvJN0raMGOUJcOFhL d3gZ81R531i5pFAjEMaQODeFbovr7w62zgEWRWtgQrdfCtUP/CK9vkFwDgaBjgBsMb mXKq2m32AKdNA== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SPI supports 4 through 32 bits per word. This patch sets bits_per_word_mask accordingly to support transfer with these bits per word. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 01efb615a196..94acef0f5ea5 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -1154,6 +1154,7 @@ static int tegra_spi_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = tegra_spi_setup; master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; From patchwork Wed Mar 27 05:56:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872615 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D16331575 for ; Wed, 27 Mar 2019 05:57:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B866428CD7 for ; Wed, 27 Mar 2019 05:57:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A977F28CDA; Wed, 27 Mar 2019 05:57:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5615228CD7 for ; Wed, 27 Mar 2019 05:57:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733208AbfC0F5d (ORCPT ); Wed, 27 Mar 2019 01:57:33 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7007 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733184AbfC0F5a (ORCPT ); Wed, 27 Mar 2019 01:57:30 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:24 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:29 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:29 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:29 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:29 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:28 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 16/26] spi: tegra114: set bus number based on id Date: Tue, 26 Mar 2019 22:56:37 -0700 Message-ID: <1553666207-11414-16-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666244; bh=wwyBPb+L2vkj/16eV8z6d34NZ+I/fcKs3EMH2g9KMdk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=MbpooTTu+lKG7kM8A8l9OqhM+LE8l+QJeMaAC1a23iZexMl6zI1g6U+4D4w3pzfa8 lEmHgSqHVj9dMbOTqMD93wrDpFG5i2sE3hVkJY2ogY837vaZM0ukbx+hHS4+flIFc7 j4Py5G8eAI8/1AYc49wuBmX4EtCQGaKkAhWRnFfkcZVzyyFU+p/ZoE6/PjCRMWPl6a mOK+uXRQw4RNZsSt3SD8jvNV5UJpws4Vineela3IFRNAZYs28nynQt8p7nK8tz9XmS q3XIpX+qU7rVHxJC1FRFCuNUIqcIUtPfA8Tj9MFC9JljrwNjZNbZhinc/8j2Zi7Zvj 9aXQ024gHG+9Q== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch sets the SPI device id from the device tree as the bus number. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 94acef0f5ea5..9b9d4b9e1f3e 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -1138,6 +1138,7 @@ static int tegra_spi_probe(struct platform_device *pdev) struct tegra_spi_data *tspi; struct resource *r; int ret, spi_irq; + int bus_num; master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); if (!master) { @@ -1159,6 +1160,9 @@ static int tegra_spi_probe(struct platform_device *pdev) master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; master->auto_runtime_pm = true; + bus_num = of_alias_get_id(pdev->dev.of_node, "spi"); + if (bus_num >= 0) + master->bus_num = bus_num; tspi->master = master; tspi->dev = &pdev->dev; From patchwork Wed Mar 27 05:56:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872635 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 441231575 for ; Wed, 27 Mar 2019 05:58:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2EA5F28CD7 for ; Wed, 27 Mar 2019 05:58:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2308828CDA; Wed, 27 Mar 2019 05:58:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AC3EB28CD7 for ; Wed, 27 Mar 2019 05:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733194AbfC0F5d (ORCPT ); Wed, 27 Mar 2019 01:57:33 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7013 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733161AbfC0F5c (ORCPT ); Wed, 27 Mar 2019 01:57:32 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:31 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:31 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:30 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:30 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:30 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 17/26] spi: tegra114: add support for interrupt mask Date: Tue, 26 Mar 2019 22:56:38 -0700 Message-ID: <1553666207-11414-17-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666246; bh=KGrbRWFDE8MJ7cCeVt161Ip485lq9EQqvw7bRJCw30U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=dHWgIF488aE5c1Y/wxcNXBrIYlcOMkXAlE9joK1bozGT6mCK+Y5FZyWL49WHdO86k n3psvZ4l2Y6R8HUOEj9PPDyvv2BM0uqKx+/3HgjGvIvz7Z9XnzSTJxWuRVuSUInUJ4 dDAq7OHH/QbdrkH50kykl2lG8Cc2BtPxFSzkQ7apJ6U2JskZC/hM3ISt/eTeiNSJ/y xkI2CqVrR+D8NZ/bO6xnsKZEQl6Evm28mAC0xk5fHSWZ7fw8n8YqDXEi6ChFgYopgN gKOYR8XI/o8iluRDb7Gr1WBz9f6Wip8hIxFR1O5hUyQI9nIPAnWUFzPuEiZkybvWDy 5kZhE+X+XUOwQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch creates tegra_spi_soc_data structure to maintain and implement SPI HW feature differences between different Tegra chips and also creates a separate compatible string for T124/T210/T186. Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK for enabling or disabling interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 53 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 9b9d4b9e1f3e..68fee474580b 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -149,6 +149,8 @@ #define SPI_TX_FIFO 0x108 #define SPI_RX_FIFO 0x188 +#define SPI_INTR_MASK 0x18c +#define SPI_INTR_ALL_MASK (0x1fUL << 25) #define MAX_CHIP_SELECT 4 #define SPI_FIFO_DEPTH 64 #define DATA_DIR_TX (1 << 0) @@ -161,6 +163,10 @@ #define MAX_HOLD_CYCLES 16 #define SPI_DEFAULT_SPEED 25000000 +struct tegra_spi_soc_data { + bool has_intr_mask_reg; +}; + struct tegra_spi_data { struct device *dev; struct spi_master *master; @@ -211,6 +217,7 @@ struct tegra_spi_data { u32 *tx_dma_buf; dma_addr_t tx_dma_phys; struct dma_async_tx_descriptor *tx_dma_desc; + const struct tegra_spi_soc_data *soc_data; }; static int tegra_spi_runtime_suspend(struct device *dev); @@ -554,11 +561,13 @@ static int tegra_spi_start_dma_based_transfer( dma_burst = 8; } - if (tspi->cur_direction & DATA_DIR_TX) - val |= SPI_IE_TX; + if (!tspi->soc_data->has_intr_mask_reg) { + if (tspi->cur_direction & DATA_DIR_TX) + val |= SPI_IE_TX; - if (tspi->cur_direction & DATA_DIR_RX) - val |= SPI_IE_RX; + if (tspi->cur_direction & DATA_DIR_RX) + val |= SPI_IE_RX; + } tegra_spi_writel(tspi, val, SPI_DMA_CTL); tspi->dma_control_reg = val; @@ -848,6 +857,12 @@ static int tegra_spi_setup(struct spi_device *spi) return ret; } + if (tspi->soc_data->has_intr_mask_reg) { + val = tegra_spi_readl(tspi, SPI_INTR_MASK); + val &= ~SPI_INTR_ALL_MASK; + tegra_spi_writel(tspi, val, SPI_INTR_MASK); + } + spin_lock_irqsave(&tspi->lock, flags); val = tspi->def_command1_reg; if (spi->mode & SPI_CS_HIGH) @@ -1126,8 +1141,29 @@ static irqreturn_t tegra_spi_isr(int irq, void *context_data) return IRQ_WAKE_THREAD; } +static struct tegra_spi_soc_data tegra114_spi_soc_data = { + .has_intr_mask_reg = false, +}; + +static struct tegra_spi_soc_data tegra124_spi_soc_data = { + .has_intr_mask_reg = false, +}; + +static struct tegra_spi_soc_data tegra210_spi_soc_data = { + .has_intr_mask_reg = true, +}; + static const struct of_device_id tegra_spi_of_match[] = { - { .compatible = "nvidia,tegra114-spi", }, + { + .compatible = "nvidia,tegra114-spi", + .data = &tegra114_spi_soc_data, + }, { + .compatible = "nvidia,tegra124-spi", + .data = &tegra124_spi_soc_data, + }, { + .compatible = "nvidia,tegra210-spi", + .data = &tegra210_spi_soc_data, + }, {} }; MODULE_DEVICE_TABLE(of, tegra_spi_of_match); @@ -1168,6 +1204,13 @@ static int tegra_spi_probe(struct platform_device *pdev) tspi->dev = &pdev->dev; spin_lock_init(&tspi->lock); + tspi->soc_data = of_device_get_match_data(&pdev->dev); + if (!tspi->soc_data) { + dev_err(&pdev->dev, "unsupported tegra\n"); + ret = -ENODEV; + goto exit_free_master; + } + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); tspi->base = devm_ioremap_resource(&pdev->dev, r); if (IS_ERR(tspi->base)) { From patchwork Wed Mar 27 05:56:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872633 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0341D139A for ; Wed, 27 Mar 2019 05:58:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E128528CD7 for ; Wed, 27 Mar 2019 05:58:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D421128CDA; Wed, 27 Mar 2019 05:58:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 392DF28CD7 for ; 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Wed, 27 Mar 2019 05:57:32 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:32 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:32 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 18/26] spi: tegra114: add support for hw based cs Date: Tue, 26 Mar 2019 22:56:39 -0700 Message-ID: <1553666207-11414-18-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666256; bh=1fDrF2d8T+/5SvtPC6xRUMYUQdbIEgGT9t99Qqtc3BE=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=p/BhiLl50hNFlMai4+2DOVG82gV7Xc3hY+WG4DS8XwDTX+fYXii69GMk2KM4npOyY ShgJRg39w5wIxn6QbQMiC3eRgbZOwkCwsNnptnEnbS6CHkAxrqSd2hiBjJkRWeo49T uoSaRlIuHiAMQpEjl8Vl5o57NQF0RHPzT8ZzI41Ch6NoCHly1uNGP46SaoXMAUloi5 PJ0fEXCmmTyHRpBj7RPPTG/0C6SdfhKYuPElk8dqHw+6Ez3Yuv2hS2EZNJ5EAQ4ajK hq46VWPDOMMD1Uxbf0dJewqE/Y+haGWViuofHBEO9k0BTrHDn/7ZzqzXfXoQib+tao fy4w7fS2HadFA== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for HW based CS control. Tegra SPI controller supports both HW and SW based CS control transfers. Tegra SPI driver default uses SW CS control for transfers and HW CS control can be enabled through SPI client device node DT property nvidia,enable-hw-based-cs and is used only for single transfers. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 71 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 68fee474580b..86c34f02d13a 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -167,6 +167,10 @@ struct tegra_spi_soc_data { bool has_intr_mask_reg; }; +struct tegra_spi_client_data { + bool is_hw_based_cs; +}; + struct tegra_spi_data { struct device *dev; struct spi_master *master; @@ -193,6 +197,7 @@ struct tegra_spi_data { unsigned dma_buf_size; unsigned max_buf_size; bool is_curr_dma_xfer; + bool use_hw_based_cs; struct completion rx_dma_complete; struct completion tx_dma_complete; @@ -723,9 +728,11 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, } static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, - struct spi_transfer *t, bool is_first_of_msg) + struct spi_transfer *t, bool is_first_of_msg, + bool is_single_xfer) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); + struct tegra_spi_client_data *cdata = spi->controller_data; u32 speed = t->speed_hz; u8 bits_per_word = t->bits_per_word; u32 command1; @@ -776,11 +783,19 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, } else tegra_spi_writel(tspi, command1, SPI_COMMAND1); - command1 |= SPI_CS_SW_HW; - if (spi->mode & SPI_CS_HIGH) - command1 |= SPI_CS_SW_VAL; - else - command1 &= ~SPI_CS_SW_VAL; + tspi->use_hw_based_cs = false; + if (cdata && cdata->is_hw_based_cs && is_single_xfer) + tspi->use_hw_based_cs = true; + + if (!tspi->use_hw_based_cs) { + command1 |= SPI_CS_SW_HW; + if (spi->mode & SPI_CS_HIGH) + command1 |= SPI_CS_SW_VAL; + else + command1 &= ~SPI_CS_SW_VAL; + } else { + command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); + } tegra_spi_writel(tspi, 0, SPI_COMMAND2); } else { @@ -838,9 +853,41 @@ static int tegra_spi_start_transfer_one(struct spi_device *spi, return ret; } +static struct tegra_spi_client_data + *tegra_spi_parse_cdata_dt(struct spi_device *spi) +{ + struct tegra_spi_client_data *cdata; + struct device_node *slave_np; + + slave_np = spi->dev.of_node; + if (!slave_np) { + dev_dbg(&spi->dev, "device node not found\n"); + return NULL; + } + + cdata = kzalloc(sizeof(*cdata), GFP_KERNEL); + if (!cdata) + return NULL; + + if (of_property_read_bool(slave_np, "nvidia,enable-hw-based-cs")) + cdata->is_hw_based_cs = true; + + return cdata; +} + +static void tegra_spi_cleanup(struct spi_device *spi) +{ + struct tegra_spi_client_data *cdata = spi->controller_data; + + spi->controller_data = NULL; + if (spi->dev.of_node) + kfree(cdata); +} + static int tegra_spi_setup(struct spi_device *spi) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); + struct tegra_spi_client_data *cdata = spi->controller_data; u32 val; unsigned long flags; int ret; @@ -851,9 +898,15 @@ static int tegra_spi_setup(struct spi_device *spi) spi->mode & SPI_CPHA ? "" : "~", spi->max_speed_hz); + if (!cdata) { + cdata = tegra_spi_parse_cdata_dt(spi); + spi->controller_data = cdata; + } + ret = pm_runtime_get_sync(tspi->dev); if (ret < 0) { dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); + tegra_spi_cleanup(spi); return ret; } @@ -909,18 +962,21 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, struct tegra_spi_data *tspi = spi_master_get_devdata(master); struct spi_transfer *xfer; struct spi_device *spi = msg->spi; + int single_xfer; int ret; bool skip = false; msg->status = 0; msg->actual_length = 0; + single_xfer = list_is_singular(&msg->transfers); list_for_each_entry(xfer, &msg->transfers, transfer_list) { u32 cmd1; reinit_completion(&tspi->xfer_completion); - cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg); + cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg, + single_xfer); if (!xfer->len) { ret = 0; @@ -1193,6 +1249,7 @@ static int tegra_spi_probe(struct platform_device *pdev) SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = tegra_spi_setup; + master->cleanup = tegra_spi_cleanup; master->transfer_one_message = tegra_spi_transfer_one_message; master->num_chipselect = MAX_CHIP_SELECT; master->auto_runtime_pm = true; From patchwork Wed Mar 27 05:56:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 921891575 for ; Wed, 27 Mar 2019 05:58:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C7E128CD8 for ; Wed, 27 Mar 2019 05:58:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 709A028CDE; Wed, 27 Mar 2019 05:58:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 12A4E28CD8 for ; Wed, 27 Mar 2019 05:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732999AbfC0F61 (ORCPT ); Wed, 27 Mar 2019 01:58:27 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6258 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733221AbfC0F5f (ORCPT ); Wed, 27 Mar 2019 01:57:35 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:33 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:35 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:34 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:34 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:34 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:33 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 19/26] DT bindings: spi: add spi client device properties Date: Tue, 26 Mar 2019 22:56:40 -0700 Message-ID: <1553666207-11414-19-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds below cs timing properties to allow SPI master configuring setup, hold and time interval between two SPI transactions to meet specific SPI client device requirements. CS setup time CS hold time CS inactive delay DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666253; bh=TbJVgRAIkjok3TkKNkfcvYc4WGyZhOpiH6sUZvadGrQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Tud9guY5XCzkjKA2k2n0+xO/vTfMTNhH1e0viAyYmlgoG/j+uSBAAmOeZucVUlmEa rwqxlSm+rkYMUfgSWqmJXqEjgRIAqMhA32FOJmhgpblGwYUR22hnbdhbk4TcqMNsIO mXBgiIq3sOB7dKCDIv4+YSUreRrnXrvrDN0NE9zN7D+AQWYLF5dI4v+UDalNYJU2hz TusNrURxuHgtpModvYVQRPgPDv+nJ2QE6L7yZH/M6XP7jYprtQHWnHAiMwqqSXBcrf 8vlhV96anQSaGkioOUTp8ThlHSwBKLRFHRofVlrhT53K0xvTCvVst4aHvA1aq3QPw0 sVr25yohIPq7w== Signed-off-by: Sowjanya Komatineni --- Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index 9ba7c5a273b4..6167c5234b64 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt @@ -23,6 +23,13 @@ Required properties: Recommended properties: - spi-max-frequency: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt + +spi-client device controller properties: +- nvidia,cs-setup-clk-count: CS setup timing parameter. +- nvidia,cs-hold-clk-count: CS hold timing parameter. +- nvidia,cs-inactive-cycles: CS inactive delay in terms of clock between + transfers. + Example: spi@7000d600 { From patchwork Wed Mar 27 05:56:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 95D981575 for ; Wed, 27 Mar 2019 05:58:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 806D928CD7 for ; Wed, 27 Mar 2019 05:58:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 744FC28CDA; Wed, 27 Mar 2019 05:58:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E303928CD7 for ; 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Wed, 27 Mar 2019 05:57:36 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:35 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 20/26] spi: tegra114: add support for tuning HW CS timing Date: Tue, 26 Mar 2019 22:56:41 -0700 Message-ID: <1553666207-11414-20-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666255; bh=GK+sDhPMw03lTs35xJuVfysz/Evjc1/5Qm35wIZmiSc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=oM39EhrF3ROOQgHRpeUWMcQCh6KY0l3OEDY3NxfqkBiZuNi3bnUioUeSkGB9PKUMx 2fsryg3zyp7F2qHdhbP1Wkf7/REzzWZhc/CF6HF3JuRcpUwc28nMqZzr9wMmHfDJB/ EjrpQlnKQtg/GL6GHK+jklS25XKNzw1G6xPtaLhbd6dG2caXL8v8UsQFi+/CbfFiLO zK17N3GD2jhQqO45W7sDHLvzOuJ04VMEb+ztqlW2uFkpxtSg5lT/OtpicQuRNjufK1 1fy2mk1oPIX6lhq01T28aVkKEt3l9mi79O6GWKT/FclzPXyM14wx1ea/AAEpvqsKGi Er4cvOeFBTMMQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some slaves may need certain CS setup time, hold time, CS inactive delay between the packets. Tegra SPI controller supports configuring these CS timing parameters and are applicable when using HW CS. This patch adds support for configuring these HW CS timing parameters through device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 61 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 86c34f02d13a..e01962344bde 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -95,8 +95,10 @@ (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \ ((reg) & ~(1 << ((cs) * 8 + 5)))) #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \ - (reg = (((val) & 0xF) << ((cs) * 8)) | \ - ((reg) & ~(0xF << ((cs) * 8)))) + (reg = (((val) & 0x1F) << ((cs) * 8)) | \ + ((reg) & ~(0x1F << ((cs) * 8)))) +#define MAX_SETUP_HOLD_CYCLES 16 +#define MAX_INACTIVE_CYCLES 32 #define SPI_TRANS_STATUS 0x010 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF) @@ -169,6 +171,9 @@ struct tegra_spi_soc_data { struct tegra_spi_client_data { bool is_hw_based_cs; + int cs_setup_clk_count; + int cs_hold_clk_count; + int cs_inactive_cycles; }; struct tegra_spi_data { @@ -210,6 +215,8 @@ struct tegra_spi_data { u32 command1_reg; u32 dma_control_reg; u32 def_command1_reg; + u32 spi_cs_timing1; + u32 spi_cs_timing2; struct completion xfer_completion; struct spi_transfer *curr_xfer; @@ -727,6 +734,43 @@ static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi, dma_release_channel(dma_chan); } +static void tegra_spi_set_hw_cs_timing(struct spi_device *spi) +{ + struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); + struct tegra_spi_client_data *cdata = spi->controller_data; + u32 setup_dly; + u32 hold_dly; + u32 setup_hold; + u32 spi_cs_timing; + u32 inactive_cycles; + u8 cs_state; + + setup_dly = min(cdata->cs_setup_clk_count, MAX_SETUP_HOLD_CYCLES); + hold_dly = min(cdata->cs_hold_clk_count, MAX_SETUP_HOLD_CYCLES); + setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1); + spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1, + spi->chip_select, + setup_hold); + if (tspi->spi_cs_timing1 != spi_cs_timing) { + tspi->spi_cs_timing1 = spi_cs_timing; + tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1); + } + + spi_cs_timing = tspi->spi_cs_timing2; + inactive_cycles = min(cdata->cs_inactive_cycles, MAX_INACTIVE_CYCLES); + if (inactive_cycles) + inactive_cycles--; + cs_state = inactive_cycles ? 0 : 1; + SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, + cs_state); + SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi->chip_select, + inactive_cycles); + if (tspi->spi_cs_timing2 != spi_cs_timing) { + tspi->spi_cs_timing2 = spi_cs_timing; + tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2); + } +} + static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, struct spi_transfer *t, bool is_first_of_msg, bool is_single_xfer) @@ -784,8 +828,10 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, tegra_spi_writel(tspi, command1, SPI_COMMAND1); tspi->use_hw_based_cs = false; - if (cdata && cdata->is_hw_based_cs && is_single_xfer) + if (cdata && cdata->is_hw_based_cs && is_single_xfer) { tspi->use_hw_based_cs = true; + tegra_spi_set_hw_cs_timing(spi); + } if (!tspi->use_hw_based_cs) { command1 |= SPI_CS_SW_HW; @@ -871,7 +917,12 @@ static struct tegra_spi_client_data if (of_property_read_bool(slave_np, "nvidia,enable-hw-based-cs")) cdata->is_hw_based_cs = true; - + of_property_read_u32(slave_np, "nvidia,cs-setup-clk-count", + &cdata->cs_setup_clk_count); + of_property_read_u32(slave_np, "nvidia,cs-hold-clk-count", + &cdata->cs_hold_clk_count); + of_property_read_u32(slave_np, "nvidia,cs-inactive-cycles", + &cdata->cs_inactive_cycles); return cdata; } @@ -1326,6 +1377,8 @@ static int tegra_spi_probe(struct platform_device *pdev) reset_control_deassert(tspi->rst); tspi->def_command1_reg = SPI_M_S; tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); + tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); + tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); pm_runtime_put(&pdev->dev); ret = request_threaded_irq(tspi->irq, tegra_spi_isr, tegra_spi_isr_thread, IRQF_ONESHOT, From patchwork Wed Mar 27 05:56:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872627 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F5C7139A for ; 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Wed, 27 Mar 2019 01:57:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:41 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:38 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:38 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:38 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:38 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:37 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Date: Tue, 26 Mar 2019 22:56:42 -0700 Message-ID: <1553666207-11414-21-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666261; bh=ZhooVT7e7y0UvpyK4jtj0c+ZzgA5KeS46L9eKsUYhhg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EaIXBjrRc3l56FkjN08LgIdJx2fncM3u/HK2HdHZQ58GjFTe/H9xkcBSqns7hgSUy NVWe5AzzbfxyKBME1wHZyAO2zFOKWVzHtK8z2FarQp+lzZOqU9GZM5TyY4P9JFiot1 gMntU+KZVeWxgwJHPTw7RnDPJKRk62kWCJlldYQ3qLxTXl25STC/JZaDDsVD+i1Vg0 ddfdwSsLhmxVIfkAOuE2CgTcL1edecoDQHgWhcRSyajDhiF+eDAI3dJpwnKrSzTO+L 01iagCH6gD2FST0ilngLddvmtJdCK7pJG2Ytjp3waXEUVV3qTz3LXrNWJbErRPe8zK qml8x2nDgfBtw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds Tegra SPI master tx and rx clock delay properties. TX/RX clock delays may vary depending on the platform design trace lengths for each client on the Tegra SPI bus. These properties helps to tune the clock delays. Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/spi/nvidia,tegra114-spi.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index 6167c5234b64..2b84b7b726ce 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt @@ -29,6 +29,12 @@ spi-client device controller properties: - nvidia,cs-hold-clk-count: CS hold timing parameter. - nvidia,cs-inactive-cycles: CS inactive delay in terms of clock between transfers. +- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device + with this tap value. This property is used to tune the outgoing data from + Tegra SPI master with respect to outgoing Tegra SPI master clock. +- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device + with this tap value. This property is used to adjust the Tegra SPI master + clock with respect to the data from the SPI slave device. Example: @@ -45,4 +51,14 @@ spi@7000d600 { reset-names = "spi"; dmas = <&apbdma 16>, <&apbdma 16>; dma-names = "rx", "tx"; + + @ { + ... + ... + nvidia,cs-setup-clk-count = <10>; + nvidia,cs-hold-clk-count = <10>; + nvidia,rx-clk-tap-delay = <0>; + nvidia,tx-clk-tap-delay = <16>; + ... + }; }; From patchwork Wed Mar 27 05:56:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C61331874 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B101428CD7 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A534728CDA; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 390CD28CD7 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733278AbfC0F5m (ORCPT ); Wed, 27 Mar 2019 01:57:42 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17631 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733198AbfC0F5l (ORCPT ); Wed, 27 Mar 2019 01:57:41 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:40 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:39 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:39 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:39 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 22/26] spi: tegra114: add support for tuning clock delay Date: Tue, 26 Mar 2019 22:56:43 -0700 Message-ID: <1553666207-11414-22-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666263; bh=NkBXpKQJ407zfskKrIvF7fFzgILoKGcrrlOTed2L25U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=n+pYY9aa1xnP3miROvQHcG+A3IDpBfYygKziesyBFj5+MBdsGgI8v3y4USO9UM15f CqX4UU+hbR2Ozl57GVYChOydBnuZF4Bcl8GZ2a6eDSU2VLS43J/FSjZe5g1eMbJcC5 vBv6RNHxvi2qrbiNizKPh7DblZxm5clO5pKRCnBJGqGIZsKi3sKaKVkuz4nTyd+2Xd jJ2CeEBByKjSnErYFhFhOR4B6rG4nO3OaxGW4bFiKF2h41fBPTyYfS4kpzJw80ssSx 1JjbWYGewY9PsLrR4/px03HouMednHT7TNbjEuzUSzl5u8JAczy505Qf5prU5eWnzy YP6nhyWxk6u7g== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Tegra SPI controller has TX_CLK_TAP_DELAY and RX_CLK_TAP_DELAY in COMMAND2 register to tune delay of the clock going out to external device during transmit and also for the clock coming in from external device during receive. TX/RX clock tap delays may vary based on the trace lengths of the platform design for each of the slaves on the SPI bus. This patch adds support for configuring TX/RX clock delays specified through device tree properties. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index e01962344bde..725d60364ec6 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -174,6 +174,8 @@ struct tegra_spi_client_data { int cs_setup_clk_count; int cs_hold_clk_count; int cs_inactive_cycles; + int tx_clk_tap_delay; + int rx_clk_tap_delay; }; struct tegra_spi_data { @@ -215,8 +217,10 @@ struct tegra_spi_data { u32 command1_reg; u32 dma_control_reg; u32 def_command1_reg; + u32 def_command2_reg; u32 spi_cs_timing1; u32 spi_cs_timing2; + u8 last_used_cs; struct completion xfer_completion; struct spi_transfer *curr_xfer; @@ -780,7 +784,9 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, u32 speed = t->speed_hz; u8 bits_per_word = t->bits_per_word; u32 command1; + u32 command2; int req_mode; + u32 tx_tap = 0, rx_tap = 0; if (speed != tspi->cur_speed) { clk_set_rate(tspi->clk, speed); @@ -843,7 +849,18 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); } - tegra_spi_writel(tspi, 0, SPI_COMMAND2); + if (tspi->last_used_cs != spi->chip_select) { + if (cdata && cdata->tx_clk_tap_delay) + tx_tap = cdata->tx_clk_tap_delay; + if (cdata && cdata->rx_clk_tap_delay) + rx_tap = cdata->rx_clk_tap_delay; + command2 = SPI_TX_TAP_DELAY(tx_tap) | + SPI_RX_TAP_DELAY(rx_tap); + if (command2 != tspi->def_command2_reg) + tegra_spi_writel(tspi, command2, SPI_COMMAND2); + tspi->last_used_cs = spi->chip_select; + } + } else { command1 = tspi->command1_reg; command1 &= ~SPI_BIT_LENGTH(~0); @@ -923,6 +940,10 @@ static struct tegra_spi_client_data &cdata->cs_hold_clk_count); of_property_read_u32(slave_np, "nvidia,cs-inactive-cycles", &cdata->cs_inactive_cycles); + of_property_read_u32(slave_np, "nvidia,tx-clk-tap-delay", + &cdata->tx_clk_tap_delay); + of_property_read_u32(slave_np, "nvidia,rx-clk-tap-delay", + &cdata->rx_clk_tap_delay); return cdata; } @@ -1379,6 +1400,8 @@ static int tegra_spi_probe(struct platform_device *pdev) tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1); tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2); + tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2); + tspi->last_used_cs = master->num_chipselect + 1; pm_runtime_put(&pdev->dev); ret = request_threaded_irq(tspi->irq, tegra_spi_isr, tegra_spi_isr_thread, IRQF_ONESHOT, @@ -1451,6 +1474,8 @@ static int tegra_spi_resume(struct device *dev) return ret; } tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1); + tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2); + tspi->last_used_cs = master->num_chipselect + 1; pm_runtime_put(dev); return spi_master_resume(master); From patchwork Wed Mar 27 05:56:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9A4B3139A for ; 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Tue, 26 Mar 2019 22:57:41 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 23/26] spi: tegra114: add support for gpio based cs Date: Tue, 26 Mar 2019 22:56:44 -0700 Message-ID: <1553666207-11414-23-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666258; bh=/86OHmZnYJfA0YFuZZCn2gQJnXRXfxAICbV/k0gmLhI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=LuoeiBXIO6ajTocBdJc0kSAfj/isD+sOiGM6dPL9iye6Shke6OR+S5SCKqGX9FeDq THHPWJnygwVQnNHV/akzW31CPXfxxq5XCmooFB+mBod7JXbfnaGYZDhYX/Ql9tXJo5 wvhbAJyauZ2Dg1m2ajdI8vf7m+pY9fQti+EDzCTESFrxl0PxO60U7EL6EA/NeMGovv TSmzxBDgmIOsKisrWw8bA5yKNM8MCchNL60wZgGMQPNU96K4muOFiELDr4GzKGlQdv FcBpqsBRN2/CkVkaQ1y4k58ssV4qQO5OUPz4lA2+r+l965EaoqP0IaOmlQ3TuBwSL+ j+Fj0gk0qpIFw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds supports for chip select control using GPIO if valid CS gpio exists rather than controlling from the SPI controller. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 725d60364ec6..9b216e9d6079 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -178,6 +179,10 @@ struct tegra_spi_client_data { int rx_clk_tap_delay; }; +struct tegra_spi_client_state { + bool cs_gpio_valid; +}; + struct tegra_spi_data { struct device *dev; struct spi_master *master; @@ -781,6 +786,7 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); struct tegra_spi_client_data *cdata = spi->controller_data; + struct tegra_spi_client_state *cstate = spi->controller_state; u32 speed = t->speed_hz; u8 bits_per_word = t->bits_per_word; u32 command1; @@ -849,6 +855,12 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL); } + if (cstate->cs_gpio_valid) { + int val = (spi->mode & SPI_CS_HIGH) ? 1 : 0; + + gpio_set_value(spi->cs_gpio, val); + } + if (tspi->last_used_cs != spi->chip_select) { if (cdata && cdata->tx_clk_tap_delay) tx_tap = cdata->tx_clk_tap_delay; @@ -950,7 +962,12 @@ static struct tegra_spi_client_data static void tegra_spi_cleanup(struct spi_device *spi) { struct tegra_spi_client_data *cdata = spi->controller_data; + struct tegra_spi_client_state *cstate = spi->controller_state; + spi->controller_state = NULL; + if (cstate && cstate->cs_gpio_valid) + gpio_free(spi->cs_gpio); + kfree(cstate); spi->controller_data = NULL; if (spi->dev.of_node) kfree(cdata); @@ -960,6 +977,7 @@ static int tegra_spi_setup(struct spi_device *spi) { struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master); struct tegra_spi_client_data *cdata = spi->controller_data; + struct tegra_spi_client_state *cstate = spi->controller_state; u32 val; unsigned long flags; int ret; @@ -970,11 +988,41 @@ static int tegra_spi_setup(struct spi_device *spi) spi->mode & SPI_CPHA ? "" : "~", spi->max_speed_hz); + if (!cstate) { + cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); + if (!cstate) + return -ENOMEM; + spi->controller_state = cstate; + } + if (!cdata) { cdata = tegra_spi_parse_cdata_dt(spi); spi->controller_data = cdata; } + if (spi->master->cs_gpios && gpio_is_valid(spi->cs_gpio)) { + if (!cstate->cs_gpio_valid) { + int gpio_flag = GPIOF_OUT_INIT_HIGH; + + if (spi->mode & SPI_CS_HIGH) + gpio_flag = GPIOF_OUT_INIT_LOW; + + ret = gpio_request_one(spi->cs_gpio, gpio_flag, + "cs_gpio"); + if (ret < 0) { + dev_err(&spi->dev, + "GPIO request failed: %d\n", ret); + tegra_spi_cleanup(spi); + return ret; + } + cstate->cs_gpio_valid = true; + } else { + int val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; + + gpio_set_value(spi->cs_gpio, val); + } + } + ret = pm_runtime_get_sync(tspi->dev); if (ret < 0) { dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); @@ -1034,9 +1082,11 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, struct tegra_spi_data *tspi = spi_master_get_devdata(master); struct spi_transfer *xfer; struct spi_device *spi = msg->spi; + struct tegra_spi_client_state *cstate = spi->controller_state; int single_xfer; int ret; bool skip = false; + int cs_val; msg->status = 0; msg->actual_length = 0; @@ -1093,7 +1143,10 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, msg->actual_length += xfer->len; complete_xfer: + cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1; if (ret < 0 || skip) { + if (cstate->cs_gpio_valid) + gpio_set_value(spi->cs_gpio, cs_val); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); @@ -1103,11 +1156,15 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, if (xfer->cs_change) tspi->cs_control = spi; else { + if (cstate->cs_gpio_valid) + gpio_set_value(spi->cs_gpio, cs_val); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); } } else if (xfer->cs_change) { + if (cstate->cs_gpio_valid) + gpio_set_value(spi->cs_gpio, cs_val); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); From patchwork Wed Mar 27 05:56:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 510531575 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3B1B028CD8 for ; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EEC428CDA; Wed, 27 Mar 2019 05:58:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C514428CD7 for ; Wed, 27 Mar 2019 05:58:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733302AbfC0F5s (ORCPT ); Wed, 27 Mar 2019 01:57:48 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6275 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725795AbfC0F5q (ORCPT ); Wed, 27 Mar 2019 01:57:46 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:43 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:45 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:45 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:44 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:44 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:44 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default Date: Tue, 26 Mar 2019 22:56:45 -0700 Message-ID: <1553666207-11414-24-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666263; bh=qqcxJt6Vkn8IPNbfhZkyYZ2kfpA+TQeqAqxGiomjZbY=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=j/YsHbxJBF8Tt7C+TuyXooW6iNYA4KM+B6lpkBm9ej7etjTtdle8lJ3RRj5t4lE+T NGD2K3aNngR5QNoHMPZq2qbh/2pYH9sYSch7neZq6RrI7vj2BnOe8PG1JV6Iiu6xLl BsMc4rz7Tot9hH4recMkPu7e7ODZ9DiEHFdxSrQrvH+8iVbZrJEwoxJTylu6Z8EC+v XHppunBEnmaSr1DzwoUMrHzcuDn8Do83W7JBojOwTyTboNzAhF/xVv01uzVuD7CBbv xs7Ixeome1T9ahFqvXG/QyNodoLH/+umw00dvbd7nAnibwHcgV41uqBDYzP/67ZvoG vB2tVec/+Bqtw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP With SW CS, during transfer completion CS is de-asserted by writing the default command1 register value to SPI_COMMAND1 register. With this both mode and CS state are set at the same time and if current transfer mode is different to default SPI mode and if mode change happens prior to CS de-assert, clock polarity can change while CS is active before transfer finishes. This causes Slave to see spurious clock edges resulting in data mismatch. This patch fixes this by de-asserting CS before writing SPI_COMMAND1 to its default value so through out the transfer it will be in same SPI mode. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index 9b216e9d6079..e1669ab3b0fe 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -1147,6 +1147,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, if (ret < 0 || skip) { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); @@ -1158,6 +1164,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, else { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); @@ -1165,6 +1177,12 @@ static int tegra_spi_transfer_one_message(struct spi_master *master, } else if (xfer->cs_change) { if (cstate->cs_gpio_valid) gpio_set_value(spi->cs_gpio, cs_val); + if (cs_val && !tspi->use_hw_based_cs) + tspi->command1_reg |= SPI_CS_SW_VAL; + else + tspi->command1_reg &= ~SPI_CS_SW_VAL; + tegra_spi_writel(tspi, tspi->command1_reg, + SPI_COMMAND1); tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1); tegra_spi_transfer_delay(xfer->delay_usecs); From patchwork Wed Mar 27 05:56:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872619 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 8D6B3139A for ; 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Wed, 27 Mar 2019 01:57:47 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:47 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:47 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:46 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:46 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:46 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 25/26] spi: expand mode and mode_bits support Date: Tue, 26 Mar 2019 22:56:46 -0700 Message-ID: <1553666207-11414-25-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666262; bh=D1NqmMHYGMgeORLpgd4zuUBbBNj0Q0aWQBKVBrqrC/k=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=DssW5oqsnQ1avGVOxgQ7yRGX5cH7c9rgTzev0omdz4DtImZZ/xhSaVWnlqCXdSCYk 3IwmVsp1Qn9yACfGv1JouW5YBSZhVTpS3d25624V/AlcruQ1REQltOhCngZX2nxuCn z9knJqAPAz2GeibEyzGTlEOaTmmEirVoiiIjZnoNXcI8BMD5Ne2554wACne29UaySG QS22sDPO6x0fqnitMGvjr31fBQV1+an2hxEB150XyeO2P9/04PbzPDDPu/acUqwDcx sM5QzATYxbIwe8F+hXp3KcMo7lf9mQwK9MhG9vVgWioRGAQ20VoC05vt3jSt/SK+ai +lKKaEpW4gRJQ== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP mode and mode_bits is declared as u16 and all bits are used. This patch changes mode and mode_bits to be u32 to allow for more mode configurations. Some SPI Master controllers support configuring Least significant byte first or Most significant byte first order for transfers. Also some SPI slave devices expect bytes to be in Least significant first order and some devices expect Most significant first order. This patch creates SPI_LSBYTE_FIRST mode for this purpose. Signed-off-by: Sowjanya Komatineni --- include/linux/spi/spi.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index a0975cf76cf6..0032aa47dea0 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -143,7 +143,7 @@ struct spi_device { u32 max_speed_hz; u8 chip_select; u8 bits_per_word; - u16 mode; + u32 mode; #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ #define SPI_MODE_0 (0|0) /* (original MicroWire) */ @@ -164,6 +164,7 @@ struct spi_device { #define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */ #define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */ #define SPI_3WIRE_HIZ 0x8000 /* high impedance turnaround */ +#define SPI_LSBYTE_FIRST 0x10000 /* per-word bytes-on-wire */ int irq; void *controller_state; void *controller_data; @@ -439,7 +440,7 @@ struct spi_controller { u16 dma_alignment; /* spi_device.mode flags understood by this controller driver */ - u16 mode_bits; + u32 mode_bits; /* bitmask of supported bits_per_word for transfers */ u32 bits_per_word_mask; From patchwork Wed Mar 27 05:56:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 10872617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1AB781575 for ; Wed, 27 Mar 2019 05:58:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 03B5028CD8 for ; Wed, 27 Mar 2019 05:58:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EA86D28CD7; Wed, 27 Mar 2019 05:58:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91AA528CD7 for ; Wed, 27 Mar 2019 05:58:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1733002AbfC0F6B (ORCPT ); Wed, 27 Mar 2019 01:58:01 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:17645 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387406AbfC0F5t (ORCPT ); Wed, 27 Mar 2019 01:57:49 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 26 Mar 2019 22:57:52 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:48 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 26 Mar 2019 22:57:48 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:48 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:48 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 26 Mar 2019 22:57:47 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , Subject: [PATCH V1 26/26] spi: tegra114: add support for LSBYTE_FIRST Date: Tue, 26 Mar 2019 22:56:47 -0700 Message-ID: <1553666207-11414-26-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666272; bh=/XZ4IshDFOLzy+RB+n/+PgOUFcOCn4VIRsjaG5l/eXk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=boK/UY6ij5fuOrbvq3x0gyZ7ufn9xbksGQcQV6xG1oKBm+/M92/eO5Kg83JbMk3fo 47D6rx6J1eSzcpA08IfwegLmwt3yATaoxdCEqlQbWSDykH/OaMAxWhnnB/sTOfpNGs eFHt0K4mJOp/jSiI0Y8SXDPTCFifIn5KYuknSj+mQJlkxAamXubDy6v0Qbva6wLMMu iILcU8ESxVKdzn7iKnlEUNa2q+FPInC7hFXXlb28o0Q4LAtobquZgOTx7K1CfmIGKv i5jflwksELVM/N7UDMoF27OCdT+QMIegHcSM5UXdnC1DAAIaUIQ7C3B6ZGdVH2EnIf vE+rz89FGhsGw== Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some SPI devices expects SPI transfers to be in Least significant byte first order and some devices expect Most significant byte first order. This patch adds SPI_LSBYTE_FIRST to supported mode list and implements configuration accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/spi/spi-tegra114.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index e1669ab3b0fe..a2e809af96da 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -827,6 +827,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi, else command1 &= ~SPI_LSBIT_FE; + if (spi->mode & SPI_LSBYTE_FIRST) + command1 |= SPI_LSBYTE_FE; + else + command1 &= ~SPI_LSBYTE_FE; + if (spi->mode & SPI_3WIRE) command1 |= SPI_BIDIROE; else @@ -1393,7 +1398,8 @@ static int tegra_spi_probe(struct platform_device *pdev) /* the spi->mode bits understood by this driver: */ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST | - SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE; + SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE | + SPI_LSBYTE_FIRST; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = tegra_spi_setup; master->cleanup = tegra_spi_cleanup;