From patchwork Fri Mar 29 12:49:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10876957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E0E3314DE for ; Fri, 29 Mar 2019 12:23:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CEA3A28FD8 for ; Fri, 29 Mar 2019 12:23:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C2E7D28FF0; Fri, 29 Mar 2019 12:23:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 799E028FD8 for ; Fri, 29 Mar 2019 12:23:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1041B6E8E3; Fri, 29 Mar 2019 12:23:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id B602C6E8E3 for ; Fri, 29 Mar 2019 12:23:53 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 05:23:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,284,1549958400"; d="scan'208";a="135887794" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.34.49]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2019 05:23:51 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 18:19:18 +0530 Message-Id: <1553863759-20436-2-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1553863759-20436-1-git-send-email-uma.shankar@intel.com> References: <1553863759-20436-1-git-send-email-uma.shankar@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GC MAX register is used to program values from 1.0 to less than 3.0. A different register was used instead of the intended one. Fixed the same. Currently limiting it to 1.0 due to ABI limitations. Reported-by: Ville Syrjälä Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_color.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index ff910ed..dd179a8 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -518,14 +518,14 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of I915_WRITE(PREC_PAL_DATA(pipe), word); } - /* Program the max register to clamp values > 1.0. */ - i = lut_size - 1; - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), - drm_color_lut_extract(lut[i].red, 16)); - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), - drm_color_lut_extract(lut[i].green, 16)); - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), - drm_color_lut_extract(lut[i].blue, 16)); + /* + * Program the max register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 1.0 to 3.0 + */ + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); } else { for (i = 0; i < lut_size; i++) { u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -534,9 +534,9 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of (v << 20) | (v << 10) | v); } - I915_WRITE(PREC_PAL_GC_MAX(pipe, 0), (1 << 16) - 1); - I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1); - I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); } /* From patchwork Fri Mar 29 12:49:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Shankar, Uma" X-Patchwork-Id: 10876959 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B209214DE for ; Fri, 29 Mar 2019 12:24:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A008A28FD8 for ; Fri, 29 Mar 2019 12:24:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 94F1528FF0; Fri, 29 Mar 2019 12:24:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3B81528FD8 for ; Fri, 29 Mar 2019 12:24:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C199F6E8E6; Fri, 29 Mar 2019 12:23:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id B61786E8E3 for ; Fri, 29 Mar 2019 12:23:55 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Mar 2019 05:23:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,284,1549958400"; d="scan'208";a="135887797" Received: from linuxpresi1-desktop.iind.intel.com ([10.223.34.49]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2019 05:23:53 -0700 From: Uma Shankar To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Mar 2019 18:19:19 +0530 Message-Id: <1553863759-20436-3-git-send-email-uma.shankar@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1553863759-20436-1-git-send-email-uma.shankar@intel.com> References: <1553863759-20436-1-git-send-email-uma.shankar@intel.com> Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com, maarten.lankhorst@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP EXT2 GC MAX registers are introduced from Gen10+ to program values from 3.0 to 7.0. Enabled the same, but currently limiting it to 1.0 as userspace ABI is limited at that currently. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_color.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c866379..341f03e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10144,6 +10144,7 @@ enum skl_power_gate { #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B) #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4) #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4) +#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4) #define _PRE_CSC_GAMC_INDEX_A 0x4A484 #define _PRE_CSC_GAMC_INDEX_B 0x4AC84 diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index dd179a8..84aa5e7 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -526,6 +526,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); + + /* + * Program the gc max 2 register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 3.0 to 7.0 + */ + if (INTEL_GEN(dev_priv) >= 10) { + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), + (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), + (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), + (1 << 16) - 1); + } } else { for (i = 0; i < lut_size; i++) { u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -537,6 +551,20 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16) - 1); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16) - 1); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16) - 1); + + /* + * Program the gc max 2 register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 3.0 to 7.0 + */ + if (INTEL_GEN(dev_priv) >= 10) { + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), + (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), + (1 << 16) - 1); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), + (1 << 16) - 1); + } } /*