From patchwork Sat Mar 30 12:33:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: NOGUCHI Hiroshi X-Patchwork-Id: 10878457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E0A3139A for ; Sat, 30 Mar 2019 12:34:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E960428F8B for ; Sat, 30 Mar 2019 12:34:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DD62D28FB5; Sat, 30 Mar 2019 12:34:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5A19428F8B for ; Sat, 30 Mar 2019 12:34:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730733AbfC3MeI (ORCPT ); Sat, 30 Mar 2019 08:34:08 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:36426 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730698AbfC3MeI (ORCPT ); Sat, 30 Mar 2019 08:34:08 -0400 Received: by mail-pl1-f193.google.com with SMTP id ck15so1072187plb.3; Sat, 30 Mar 2019 05:34:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=isu5VQ34+sdjdJ+Eph/J4EP5uPnHlo+onoUCNRiEn+M=; b=EUwfST6EOS2I/8L/meeGkw9mRJOPzqpGnbyvX7r324QvL8DMcqmubox4dF8UbB0vd7 qPKJtqoXwh/wvN1aTUlVuUSTOfYojB3v5Q3kSwTMMpSgkXx5aiKGb8kS3HvTpLLfR+9F 452pWT9Hdvgd7pji00Y0pf8Kh7FvtAIytqAUlRQDm+ePvbTgmUHA1IaS7lzTKNbhElea Akjrye247/un2JW2cCvwyjBuqmdWaxShAASzpsnkZNymtAgfxnhEvIoFv7lZf4kGEhb0 h+GZbpT7k4xow++pgWe55sA5BzuDaKEZ6UbQAzcembTZwCWw5SmztU6wmETXL4ztey+Z 8dDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=isu5VQ34+sdjdJ+Eph/J4EP5uPnHlo+onoUCNRiEn+M=; b=C0s2ldu6NwMsyxjqNK02OW+uYDnRtmSAZplGbCixDOjsFVZcqtJLd8/JKKPog8IErK j3WcnXGouRUKmAhNm5HUfB9fwbOVQjmT3P3FlS2hqhWK/mlJ5Hp2zOX4jrrqJ4tsxzwT kUdNfQGjSkf2/Fdxj++34unfLe6dh4UTzZlI4l8uhBdx9RBfUJnMaNsJXYKdmY1rh++j jn0jhMJHrDvv5Oshd7wHPnlu6/+Kb/gT4BOdX4dNpAMr3v+UxcOSq4qbi6HJSDs6XFyr XxxZyL81sRLqo3OODHYSm/2Cpq5Tc+7RsC26J4vE1NbaisDE236jCMVu9+Zzqq2VicQG jaiw== X-Gm-Message-State: APjAAAV9JDTpXDRCuLc+OtlL+Ecy0Ztc6vTapfCXsIPgt+6hU3TXt+ye HT9y6rxlzhOL4uhV8jvkc/A= X-Google-Smtp-Source: APXvYqxtZSi0bjs2mY82SiGhV5xJGL4VnX/6GJXss1T9K2XlmOU8qs0uklR2aSosJ7feh83ismOqjw== X-Received: by 2002:a17:902:f01:: with SMTP id 1mr53647780ply.41.1553949247675; Sat, 30 Mar 2019 05:34:07 -0700 (PDT) Received: from localhost.localdomain ([2409:251:20c0:100:fe80:8e59:9ae1:e028]) by smtp.gmail.com with ESMTPSA id m23sm7864309pfa.117.2019.03.30.05.34.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 30 Mar 2019 05:34:07 -0700 (PDT) From: NOGUCHI Hiroshi To: John Crispin Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, NOGUCHI Hiroshi Subject: [RFC 1/5] mips: ralink: add rt2880-clock driver Date: Sat, 30 Mar 2019 21:33:13 +0900 Message-Id: <20190330123317.16821-2-drvlabo@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com> References: <20190330123317.16821-1-drvlabo@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds SoC peripheral clock gating driver. The driver loads gating clock table from of_device_id.data in individual SoC sources. Signed-off-by: NOGUCHI Hiroshi --- arch/mips/ralink/rt2880-clk_internal.h | 21 ++++ arch/mips/ralink/rt2880-clock.c | 134 +++++++++++++++++++++++++ 2 files changed, 155 insertions(+) create mode 100644 arch/mips/ralink/rt2880-clk_internal.h create mode 100644 arch/mips/ralink/rt2880-clock.c diff --git a/arch/mips/ralink/rt2880-clk_internal.h b/arch/mips/ralink/rt2880-clk_internal.h new file mode 100644 index 000000000000..9d5dded16a80 --- /dev/null +++ b/arch/mips/ralink/rt2880-clk_internal.h @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 NOGUCHI Hiroshi + */ + +#ifndef __RT2880_CLOCK_INTERNAL_H + + +#define GATE_CLK_NUM (32) + +struct gate_clk_desc { + const char *name; + const char *parent_name; +}; + +extern const struct of_device_id __initconst of_match_rt2880_clk[]; + + +#endif + + diff --git a/arch/mips/ralink/rt2880-clock.c b/arch/mips/ralink/rt2880-clock.c new file mode 100644 index 000000000000..46cc067225ab --- /dev/null +++ b/arch/mips/ralink/rt2880-clock.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 NOGUCHI Hiroshi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rt2880-clk_internal.h" + + +/* clock configuration 1 */ +#define SYSC_REG_CLKCFG1 0x30 + +struct rt2880_gate { + struct clk_hw hw; + u8 shift; +}; + +#define to_rt2880_gate(_hw) container_of(_hw, struct rt2880_gate, hw) + +static struct clk_onecell_data clk_data; +static struct clk *clks[GATE_CLK_NUM]; + +static struct regmap *syscon_regmap; + +static int rt2880_gate_enable(struct clk_hw *hw) +{ + struct rt2880_gate *clk_gate = to_rt2880_gate(hw); + u32 val = 0x01UL << clk_gate->shift; + + regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, val); + + return 0; +} + +static void rt2880_gate_disable(struct clk_hw *hw) +{ + struct rt2880_gate *clk_gate = to_rt2880_gate(hw); + u32 val = 0x01UL << clk_gate->shift; + + regmap_update_bits(syscon_regmap, SYSC_REG_CLKCFG1, val, 0); +} + +static int rt2880_gate_is_enabled(struct clk_hw *hw) +{ + struct rt2880_gate *clk_gate = to_rt2880_gate(hw); + unsigned int rdval; + + if (regmap_read(syscon_regmap, SYSC_REG_CLKCFG1, &rdval)) + return 0; + + return (!!(rdval & (0x01UL << clk_gate->shift))); +} + +static const struct clk_ops rt2880_gate_ops = { + .enable = rt2880_gate_enable, + .disable = rt2880_gate_disable, + .is_enabled = rt2880_gate_is_enabled, +}; + +static struct clk * __init +rt2880_register_gate(const char *name, const char *parent_name, u8 shift) +{ + struct rt2880_gate *clk_gate; + struct clk *clk; + struct clk_init_data init; + const char *_parent_names[1] = { parent_name }; + + clk_gate = kzalloc(sizeof(*clk_gate), GFP_KERNEL); + if (!clk_gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &rt2880_gate_ops; + init.flags = 0; + init.parent_names = parent_name ? _parent_names : NULL; + init.num_parents = parent_name ? 1 : 0; + + clk_gate->hw.init = &init; + clk_gate->shift = shift; + + clk = clk_register(NULL, &clk_gate->hw); + if (IS_ERR(clk)) + kfree(clk_gate); + + return clk; +} + +static void __init rt2880_clkctrl_init_dt(struct device_node *np) +{ + struct clk *clk; + int i; + const struct of_device_id *match; + struct gate_clk_desc *clk_tbl; + + match = of_match_node(of_match_rt2880_clk, np); + if (!match) { + pr_info("rt2880-clock: could not get compatible node"); + return; + } + clk_tbl = (struct gate_clk_desc *)match->data; + + syscon_regmap = syscon_regmap_lookup_by_phandle(np, "ralink,sysctl"); + if (IS_ERR(syscon_regmap)) { + pr_info("rt2880-clock: could not get syscon regmap"); + return; + } + + clk_data.clk_num = GATE_CLK_NUM; + clk_data.clks = clks; + + for (i = 0; i < GATE_CLK_NUM; i++) { + if (clk_tbl[i].name) { + clk = rt2880_register_gate( + clk_tbl[i].name, clk_tbl[i].parent_name, i); + if (IS_ERR_OR_NULL(clk)) + panic("rt2880-clock : could not register gate clock"); + clk_data.clks[i] = clk; + } + } + + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} +CLK_OF_DECLARE(rt2880, "ralink,rt2880-clock", rt2880_clkctrl_init_dt); From patchwork Sat Mar 30 12:33:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: NOGUCHI Hiroshi X-Patchwork-Id: 10878461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C2C4017E0 for ; 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Sat, 30 Mar 2019 05:34:12 -0700 (PDT) Received: from localhost.localdomain ([2409:251:20c0:100:fe80:8e59:9ae1:e028]) by smtp.gmail.com with ESMTPSA id m23sm7864309pfa.117.2019.03.30.05.34.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 30 Mar 2019 05:34:11 -0700 (PDT) From: NOGUCHI Hiroshi To: John Crispin Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, NOGUCHI Hiroshi Subject: [RFC 2/5] mips: ralink: add dt-binding document for rt2880-clock driver Date: Sat, 30 Mar 2019 21:33:14 +0900 Message-Id: <20190330123317.16821-3-drvlabo@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com> References: <20190330123317.16821-1-drvlabo@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: NOGUCHI Hiroshi --- .../bindings/clock/ralink,rt2880-clock.txt | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt diff --git a/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt new file mode 100644 index 000000000000..6f0757046df4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ralink,rt2880-clock.txt @@ -0,0 +1,20 @@ +* Clock bindings for Ralink/Mediatek MIPS based SoCs + +Required properties: + - compatible: must be "ralink,rt2880-clock" and + one of the following, to identify SoC series + "mediatek,mt7620-clock" for MT7620 + "mediatek,mt7628-clock" for MT7628/MT7688 + "mediatek,mt7621-clock" for MT7621 + - #clock-cells: must be 1 + - ralink,sysctl: a phandle to a ralink syscon register region + + +Example: + +clkctrl: clkctrl { + compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock"; + #clock-cells = <1>; + + ralink,sysctl = <&sysc>; +}; From patchwork Sat Mar 30 12:33:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: NOGUCHI Hiroshi X-Patchwork-Id: 10878465 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 64C4217E0 for ; Sat, 30 Mar 2019 12:34:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 49C0326E4A for ; Sat, 30 Mar 2019 12:34:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C6A1274D0; Sat, 30 Mar 2019 12:34:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5FC1F26E4A for ; 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Sat, 30 Mar 2019 05:34:15 -0700 (PDT) From: NOGUCHI Hiroshi To: John Crispin Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, NOGUCHI Hiroshi Subject: [RFC 3/5] mips: ralink: mt7620/76x8 use clk framework and rt2880-clock driver Date: Sat, 30 Mar 2019 21:33:15 +0900 Message-Id: <20190330123317.16821-4-drvlabo@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com> References: <20190330123317.16821-1-drvlabo@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP - add clock provider for reference clocks by PLL - add gating clock tables referred by rt2880-clock driver Signed-off-by: NOGUCHI Hiroshi --- arch/mips/ralink/Kconfig | 6 ++ arch/mips/ralink/Makefile | 2 + arch/mips/ralink/clk.c | 30 ++++++ arch/mips/ralink/common.h | 3 + arch/mips/ralink/mt7620.c | 132 ++++++++++++++++++++----- include/dt-bindings/clock/mt7620-clk.h | 17 ++++ 6 files changed, 168 insertions(+), 22 deletions(-) create mode 100644 include/dt-bindings/clock/mt7620-clk.h diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig index 49c22ddd9c41..13301de113bb 100644 --- a/arch/mips/ralink/Kconfig +++ b/arch/mips/ralink/Kconfig @@ -18,6 +18,10 @@ config IRQ_INTC default y depends on !SOC_MT7621 +config RT2880_CLK + bool + default n + choice prompt "Ralink SoC selection" default SOC_RT305X @@ -40,6 +44,8 @@ choice bool "MT7620/8" select CPU_MIPSR2_IRQ_VI select HAVE_PCI + select COMMON_CLK + select RT2880_CLK config SOC_MT7621 bool "MT7621" diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile index fe3471533820..af72c03ed544 100644 --- a/arch/mips/ralink/Makefile +++ b/arch/mips/ralink/Makefile @@ -25,6 +25,8 @@ obj-$(CONFIG_SOC_RT3883) += rt3883.o obj-$(CONFIG_SOC_MT7620) += mt7620.o obj-$(CONFIG_SOC_MT7621) += mt7621.o +obj-$(CONFIG_RT2880_CLK) += rt2880-clock.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_DEBUG_FS) += bootrom.o diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c index 1b7df115eb60..8715a44ebc4c 100644 --- a/arch/mips/ralink/clk.c +++ b/arch/mips/ralink/clk.c @@ -15,8 +15,15 @@ #include +#ifdef CONFIG_COMMON_CLK +#include +#endif + #include "common.h" + +#ifndef CONFIG_COMMON_CLK + struct clk { struct clk_lookup cl; unsigned long rate; @@ -72,6 +79,26 @@ long clk_round_rate(struct clk *clk, unsigned long rate) } EXPORT_SYMBOL_GPL(clk_round_rate); +#else /* CONFIG_COMMON_CLK */ + +struct clk * __init add_sys_clkdev(const char *id, unsigned long rate) +{ + struct clk *clk; + int err; + + clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); + if (IS_ERR(clk)) + panic("failed to allocate %s clock structure", id); + + err = clk_register_clkdev(clk, NULL, id); + if (err) + panic("unable to register %s clock device", id); + + return clk; +} + +#endif /* CONFIG_COMMON_CLK */ + void __init plat_time_init(void) { struct clk *clk; @@ -79,6 +106,9 @@ void __init plat_time_init(void) ralink_of_remap(); ralink_clk_init(); +#ifdef CONFIG_COMMON_CLK + of_clk_init(NULL); +#endif clk = clk_get_sys("cpu", NULL); if (IS_ERR(clk)) panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h index b8245d0940d6..9f26ca96c411 100644 --- a/arch/mips/ralink/common.h +++ b/arch/mips/ralink/common.h @@ -26,6 +26,9 @@ extern void ralink_of_remap(void); extern void ralink_clk_init(void); extern void ralink_clk_add(const char *dev, unsigned long rate); +#ifdef CONFIG_COMMON_CLK +extern struct clk *add_sys_clkdev(const char *id, unsigned long rate); +#endif extern void ralink_rst_init(void); diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index c1ce6f43642b..65dd8f7b7b9a 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -12,7 +12,13 @@ #include #include +#include +#include +#include +#include +#include #include +#include #include #include @@ -20,6 +26,7 @@ #include #include "common.h" +#include "rt2880-clk_internal.h" /* analog */ #define PMU0_CFG 0x88 @@ -504,6 +511,17 @@ mt7620_get_sys_rate(unsigned long cpu_rate) return cpu_rate / div; } +static struct clk *clks[MT7620_CLK_MAX]; + +static struct clk_onecell_data clk_data = { + .clks = clks, + .clk_num = ARRAY_SIZE(clks), +}; + +#define RFMT(label) label ":%lu.%03luMHz " +#define RINT(x) ((x) / 1000000) +#define RFRAC(x) (((x) / 1000) % 1000) + void __init ralink_clk_init(void) { unsigned long xtal_rate; @@ -517,10 +535,6 @@ void __init ralink_clk_init(void) xtal_rate = mt7620_get_xtal_rate(); -#define RFMT(label) label ":%lu.%03luMHz " -#define RINT(x) ((x) / 1000000) -#define RFRAC(x) (((x) / 1000) % 1000) - if (is_mt76x8()) { if (xtal_rate == MHZ(40)) cpu_rate = MHZ(580); @@ -529,9 +543,6 @@ void __init ralink_clk_init(void) dram_rate = sys_rate = cpu_rate / 3; periph_rate = MHZ(40); pcmi2s_rate = MHZ(480); - - ralink_clk_add("10000d00.uartlite", periph_rate); - ralink_clk_add("10000e00.uartlite", periph_rate); } else { cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate); pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); @@ -547,7 +558,6 @@ void __init ralink_clk_init(void) RINT(cpu_pll_rate), RFRAC(cpu_pll_rate), RINT(pll_rate), RFRAC(pll_rate)); - ralink_clk_add("10000500.uart", periph_rate); } pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"), @@ -555,21 +565,19 @@ void __init ralink_clk_init(void) RINT(dram_rate), RFRAC(dram_rate), RINT(sys_rate), RFRAC(sys_rate), RINT(periph_rate), RFRAC(periph_rate)); -#undef RFRAC -#undef RINT -#undef RFMT - ralink_clk_add("cpu", cpu_rate); - ralink_clk_add("10000100.timer", periph_rate); - ralink_clk_add("10000120.watchdog", periph_rate); - ralink_clk_add("10000900.i2c", periph_rate); - ralink_clk_add("10000a00.i2s", pcmi2s_rate); - ralink_clk_add("10000b00.spi", sys_rate); - ralink_clk_add("10000b40.spi", sys_rate); - ralink_clk_add("10000c00.uartlite", periph_rate); - ralink_clk_add("10000d00.uart1", periph_rate); - ralink_clk_add("10000e00.uart2", periph_rate); - ralink_clk_add("10180000.wmac", xtal_rate); + /* system global */ + clks[MT7620_CLK_CPU] = add_sys_clkdev("cpu", cpu_rate); + + /* parent reference clocks */ + clks[MT7620_CLK_SYS] = + clk_register_fixed_rate(NULL, "sys", NULL, 0, sys_rate); + clks[MT7620_CLK_PERIPH] = + clk_register_fixed_rate(NULL, "periph", NULL, 0, periph_rate); + clks[MT7620_CLK_PCMI2S] = + clk_register_fixed_rate(NULL, "pcmi2s", NULL, 0, pcmi2s_rate); + clks[MT7620_CLK_XTAL] = + clk_register_fixed_rate(NULL, "xtal", NULL, 0, xtal_rate); if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) { /* @@ -586,6 +594,86 @@ void __init ralink_clk_init(void) } } +#undef RFRAC +#undef RINT +#undef RFMT + +static void __init mt7620_clk_init_dt(struct device_node *np) +{ + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); +} +CLK_OF_DECLARE(mt7620, "mediatek,mt7620-pll", mt7620_clk_init_dt); + + +/* + * resources for rt2880-clock + */ + +static const struct gate_clk_desc clk_mt7620[GATE_CLK_NUM] __initconst = { + [12] = { .name = "uart", .parent_name = "periph" }, + [16] = { .name = "i2c", .parent_name = "periph" }, + [17] = { .name = "i2s", .parent_name = "pcmi2s" }, + [18] = { .name = "spi", .parent_name = "sys" }, + [19] = { .name = "uartl", .parent_name = "periph" }, + /* + * Now we exclude to avoid that clk framework disables no used clocks. + * After implementing clk API calls in peripheral drivers, + * we can activate their entries. + */ +#if 0 + [6] = { .name = "ge1" }, + [7] = { .name = "ge2" }, + [8] = { .name = "timer", .parent_name = "periph" }, + [9] = { .name = "intc" }, + [10] = { .name = "mc" }, + [11] = { .name = "pcm" }, + [13] = { .name = "pio" }, + [14] = { .name = "gdma" }, + [15] = { .name = "nand" }, + [21] = { .name = "fe" }, + [23] = { .name = "esw" }, + [25] = { .name = "uphy" }, + [26] = { .name = "pcie" }, + [28] = { .name = "aux" }, + [30] = { .name = "sdhc" }, +#endif +}; + +static const struct gate_clk_desc clk_mt76x8[GATE_CLK_NUM] __initconst = { + [12] = { .name = "uart0", .parent_name = "periph" }, + [16] = { .name = "i2c", .parent_name = "periph" }, + [17] = { .name = "i2s", .parent_name = "pcmi2s" }, + [18] = { .name = "spi", .parent_name = "sys" }, + [19] = { .name = "uart1", .parent_name = "periph" }, + [20] = { .name = "uart2", .parent_name = "periph" }, +#if 0 + [8] = { .name = "timer", .parent_name = "periph" }, + [9] = { .name = "intc" }, + [10] = { .name = "mc" }, + [11] = { .name = "pcm" }, + [13] = { .name = "pio" }, + [14] = { .name = "gdma" }, + [23] = { .name = "eth" }, + [25] = { .name = "uphy" }, + [26] = { .name = "pcie" }, + [28] = { .name = "mipsc" }, + [29] = { .name = "crypto" }, + [30] = { .name = "sdxc" }, + [31] = { .name = "pwm", .parent_name = "periph" }, +#endif +}; + +const struct of_device_id of_match_rt2880_clk[] __initconst = { + { + .compatible = "mediatek,mt7620-clock", + .data = clk_mt7620 }, + { + .compatible = "mediatek,mt7628-clock", + .data = clk_mt76x8 }, + { /* sentinel */ }, +}; + + void __init ralink_of_remap(void) { rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc"); diff --git a/include/dt-bindings/clock/mt7620-clk.h b/include/dt-bindings/clock/mt7620-clk.h new file mode 100644 index 000000000000..2e70e7df2ed2 --- /dev/null +++ b/include/dt-bindings/clock/mt7620-clk.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 NOGUCHI Hiroshi + */ + +#ifndef __DT_BINDINGS_MT7620_CLK_H +#define __DT_BINDINGS_MT7620_CLK_H + +#define MT7620_CLK_CPU 0 +#define MT7620_CLK_SYS 1 +#define MT7620_CLK_PERIPH 2 +#define MT7620_CLK_PCMI2S 3 +#define MT7620_CLK_XTAL 4 + +#define MT7620_CLK_MAX 5 + +#endif /* __DT_BINDINGS_MT7620_CLK_H */ From patchwork Sat Mar 30 12:33:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: NOGUCHI Hiroshi X-Patchwork-Id: 10878469 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 80C14139A for ; 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Sat, 30 Mar 2019 05:34:20 -0700 (PDT) Received: from localhost.localdomain ([2409:251:20c0:100:fe80:8e59:9ae1:e028]) by smtp.gmail.com with ESMTPSA id m23sm7864309pfa.117.2019.03.30.05.34.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 30 Mar 2019 05:34:19 -0700 (PDT) From: NOGUCHI Hiroshi To: John Crispin Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, NOGUCHI Hiroshi Subject: [RFC 4/5] mips: ralink: mt7628: add nodes for clock provider Date: Sat, 30 Mar 2019 21:33:16 +0900 Message-Id: <20190330123317.16821-5-drvlabo@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com> References: <20190330123317.16821-1-drvlabo@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: NOGUCHI Hiroshi --- arch/mips/boot/dts/ralink/mt7628a.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi index 9ff7e8faaecc..67ce939f6b2b 100644 --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi @@ -26,6 +26,18 @@ compatible = "mti,cpu-interrupt-controller"; }; + pll: pll { + compatible = "mediatek,mt7620-pll", "syscon"; + #clock-cells = <1>; + clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal"; + }; + + clkctrl: clkctrl { + compatible = "mediatek,mt7628-clock", "ralink,rt2880-clock"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + }; + palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; @@ -62,10 +74,29 @@ reg = <0x300 0x100>; }; + spi0: spi@b00 { + compatible = "ralink,mt7621-spi"; + reg = <0xb00 0x100>; + + clocks = <&clkctrl 18>; + clock-names = "spi"; + + resets = <&resetc 18>; + reset-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + uart0: uartlite@c00 { compatible = "ns16550a"; reg = <0xc00 0x100>; + clocks = <&clkctrl 12>; + clock-names = "uart0"; + resets = <&resetc 12>; reset-names = "uart0"; @@ -79,6 +110,9 @@ compatible = "ns16550a"; reg = <0xd00 0x100>; + clocks = <&clkctrl 19>; + clock-names = "uart1"; + resets = <&resetc 19>; reset-names = "uart1"; @@ -92,6 +126,9 @@ compatible = "ns16550a"; reg = <0xe00 0x100>; + clocks = <&clkctrl 20>; + clock-names = "uart2"; + resets = <&resetc 20>; reset-names = "uart2"; From patchwork Sat Mar 30 12:33:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: NOGUCHI Hiroshi X-Patchwork-Id: 10878473 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22BC0139A for ; Sat, 30 Mar 2019 12:34:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0F60226E4A for ; Sat, 30 Mar 2019 12:34:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0387528113; Sat, 30 Mar 2019 12:34:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A4D8226E4A for ; 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Sat, 30 Mar 2019 05:34:23 -0700 (PDT) From: NOGUCHI Hiroshi To: John Crispin Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, NOGUCHI Hiroshi Subject: [RFC 5/5] mips: ralink: mt7620: add nodes for clock provider Date: Sat, 30 Mar 2019 21:33:17 +0900 Message-Id: <20190330123317.16821-6-drvlabo@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190330123317.16821-1-drvlabo@gmail.com> References: <20190330123317.16821-1-drvlabo@gmail.com> MIME-Version: 1.0 Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: NOGUCHI Hiroshi --- arch/mips/boot/dts/ralink/mt7620a.dtsi | 34 +++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi index 1f6e5320f486..bc56b8f9a530 100644 --- a/arch/mips/boot/dts/ralink/mt7620a.dtsi +++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi @@ -5,11 +5,21 @@ compatible = "ralink,mtk7620a-soc"; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "mips,mips24KEc"; + device_type = "cpu"; + reg = <0>; }; }; + resetc: reset-controller { + compatible = "ralink,rt2880-reset"; + #reset-cells = <1>; + }; + cpuintc: cpuintc { #address-cells = <0>; #interrupt-cells = <1>; @@ -17,6 +27,18 @@ compatible = "mti,cpu-interrupt-controller"; }; + pll: pll { + compatible = "mediatek,mt7620-pll", "syscon"; + #clock-cells = <1>; + clock-output-names = "cpu", "sys", "periph", "pcmi2s", "xtal"; + }; + + clkctrl: clkctrl { + compatible = "mediatek,mt7620-clock", "ralink,rt2880-clock"; + #clock-cells = <1>; + ralink,sysctl = <&sysc>; + }; + palmbus@10000000 { compatible = "palmbus"; reg = <0x10000000 0x200000>; @@ -25,8 +47,8 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,mt7620a-sysc"; + sysc: sysc@0 { + compatible = "ralink,mt7620a-sysc", "syscon"; reg = <0x0 0x100>; }; @@ -46,10 +68,16 @@ reg = <0x300 0x100>; }; - uartlite@c00 { + uartlite: uartlite@c00 { compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&clkctrl 19>; + clock-names = "uartl"; + + resets = <&resetc 19>; + reset-names = "uartl"; + interrupt-parent = <&intc>; interrupts = <12>;