From patchwork Mon Apr 1 16:30:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kirankumar X-Patchwork-Id: 10880265 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77FDE139A for ; Mon, 1 Apr 2019 16:37:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6041D286BF for ; Mon, 1 Apr 2019 16:37:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 54944286D0; Mon, 1 Apr 2019 16:37:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D5F51286BF for ; Mon, 1 Apr 2019 16:37:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CF756E256; Mon, 1 Apr 2019 16:37:47 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 186366E256 for ; Mon, 1 Apr 2019 16:37:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 09:37:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,297,1549958400"; d="scan'208";a="145639989" Received: from kskumar.iind.intel.com ([10.66.247.75]) by FMSMGA003.fm.intel.com with ESMTP; 01 Apr 2019 09:37:44 -0700 From: kiran.s.kumar@intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 1 Apr 2019 22:00:02 +0530 Message-Id: <1554136202-9349-1-git-send-email-kiran.s.kumar@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915: FBC needs vblank before enable / disable. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Kiran Kumar S As per the display workaround #1200, FBC needs wait for vblank before enabling and before disabling FBC. In some cases, depending on whether FBC was compressing in that frame, several control signals in the compression engine also will fail to properly recognize the final segment of the frame as a result of the missing last pixel indication. As a result of this, we're seeing corrupted cache line/compression indicators after FBC re-enables which causes underruns or corruption when they're used to decompress. WA sequence as below: 1) Display enables plane 1A 2) Wait for 1 vblank 3) FBC gets enabled 4) Wait for 1 VBLANK 5) Turn off FBC In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen got corrupted. With the above WA, issue was resolved. Change-Id: I6c5cc8978bc23fb6fc1f5fedd9599c6281bd78e9 Signed-off-by: Kiran Kumar S --- drivers/gpu/drm/i915/intel_display.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index c2d8589a4150..fec06447ab72 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12246,6 +12246,8 @@ static void intel_update_crtc(struct drm_crtc *crtc, } if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { + /* Display WA #1200: GLK */ + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); intel_fbc_enable( intel_crtc, pipe_config, to_intel_plane_state(crtc->primary->state)); @@ -12419,6 +12421,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state) intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); intel_crtc->active = false; + /* Display WA #1200: GLK */ + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); intel_fbc_disable(intel_crtc); intel_disable_shared_dpll(intel_crtc);