| Message ID | 1411445498-20250-2-git-send-email-r65037@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
Am Dienstag, den 23.09.2014, 12:11 +0800 schrieb Richard Zhu: > - enable pcie on imx6qdl sabreauto boards. > > Signed-off-by: Richard Zhu <r65037@freescale.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > index 009abd6..d6040a5 100644 > --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > @@ -410,6 +410,10 @@ > }; > }; > > +&pcie { > + status = "okay"; > +}; > + > &pwm3 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pwm3>;
Hi Richard, On Tue, Sep 23, 2014 at 1:11 AM, Richard Zhu <r65037@freescale.com> wrote: > - enable pcie on imx6qdl sabreauto boards. > > Signed-off-by: Richard Zhu <r65037@freescale.com> > --- > arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > index 009abd6..d6040a5 100644 > --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > @@ -410,6 +410,10 @@ > }; > }; > > +&pcie { > + status = "okay"; > +}; It would be better if you could pass the PCI reset pin that comes from the GPIO expander. -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Fabio > -----Original Message----- > From: Fabio Estevam [mailto:festevam@gmail.com] > Sent: Tuesday, September 23, 2014 8:41 PM > To: Zhu Richard-R65037 > Cc: linux-pci-owner@vger.kernel.org; linux-pci@vger.kernel.org; Guo Shawn- > R65073; Lucas Stach; Tim Harvey > Subject: Re: [PATCH v2 1/5] PCI: imx6: enable pcie on imx6qdl sabreauto > > Hi Richard, > > On Tue, Sep 23, 2014 at 1:11 AM, Richard Zhu <r65037@freescale.com> wrote: > > - enable pcie on imx6qdl sabreauto boards. > > > > Signed-off-by: Richard Zhu <r65037@freescale.com> > > --- > > arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > > b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > > index 009abd6..d6040a5 100644 > > --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > > +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi > > @@ -410,6 +410,10 @@ > > }; > > }; > > > > +&pcie { > > + status = "okay"; > > +}; > > It would be better if you could pass the PCI reset pin that comes from the > GPIO expander. [Richard] 6qdl sabreauto boards don't have the pcie reset gpio in the board design at all. Best Regards Richard Zhu
Hi Richard,
On Tue, Sep 23, 2014 at 11:54 PM, Hong-Xing.Zhu@freescale.com
<Hong-Xing.Zhu@freescale.com> wrote:
> [Richard] 6qdl sabreauto boards don't have the pcie reset gpio in the board design at all.
I have just downloaded the mx6 sabreauto board schematics from
freescale.com and it matches the one I have seen before.
You can search for the CPU_PER_RST_B signal. It is connected via R785
0 ohm resistor to PCIE_RST_B.
CPU_PER_RST_B can be controlled via MAX7310 pin IO/2.
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Hi Fabio: > -----Original Message----- > From: Fabio Estevam [mailto:festevam@gmail.com] > Sent: Thursday, September 25, 2014 5:04 AM > To: Zhu Richard-R65037 > Cc: linux-pci-owner@vger.kernel.org; linux-pci@vger.kernel.org; Guo Shawn- > R65073; Lucas Stach; Tim Harvey > Subject: Re: [PATCH v2 1/5] PCI: imx6: enable pcie on imx6qdl sabreauto > > Hi Richard, > > On Tue, Sep 23, 2014 at 11:54 PM, Hong-Xing.Zhu@freescale.com <Hong- > Xing.Zhu@freescale.com> wrote: > > > [Richard] 6qdl sabreauto boards don't have the pcie reset gpio in the board > design at all. > > I have just downloaded the mx6 sabreauto board schematics from freescale.com > and it matches the one I have seen before. > > You can search for the CPU_PER_RST_B signal. It is connected via R785 > 0 ohm resistor to PCIE_RST_B. > > CPU_PER_RST_B can be controlled via MAX7310 pin IO/2. [Richard] Yes it is. On ARD board, the PCIE_RST_B is connected to CPU_PER_RST_B. But this is not one signal that can be controlled by PCIE module itself. It is kicked once at the moment when the board is powered up. Best Regards Richard Zhu
On Wed, Sep 24, 2014 at 10:21 PM, Hong-Xing.Zhu@freescale.com <Hong-Xing.Zhu@freescale.com> wrote: > [Richard] Yes it is. On ARD board, the PCIE_RST_B is connected to CPU_PER_RST_B. > But this is not one signal that can be controlled by PCIE module itself. Let's take imx6qdl-sabresd.dtsi for example: &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 0>; status = "okay"; }; It uses GPIO7_12 for PCI reset. For sabreauto we just need to change to something like this format: reset-gpio = <&max7310_b 2 0>; > It is kicked once at the moment when the board is powered up. Yes, the signal is connected to power-on and it can also be independently controlled via MAX7310. Anyway, no need to change this if you don't want. I can send a patch adding the reset later :-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 009abd6..d6040a5 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -410,6 +410,10 @@ }; }; +&pcie { + status = "okay"; +}; + &pwm3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>;
- enable pcie on imx6qdl sabreauto boards. Signed-off-by: Richard Zhu <r65037@freescale.com> --- arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 4 ++++ 1 file changed, 4 insertions(+)