| Message ID | 1417506327-18908-1-git-send-email-andy.yan@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Andy, Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan: [...] > +static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, > + void *data) > +{ > + struct platform_device *pdev = to_platform_device(dev); > + const struct dw_hdmi_plat_data *plat_data; > + const struct of_device_id *match; > + struct drm_device *drm = data; > + struct drm_encoder *encoder; > + struct rockchip_hdmi *hdmi; > + int ret; > + > + if (!pdev->dev.of_node) > + return -ENODEV; > + > + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); > + if (!hdmi) > + return -ENOMEM; > + > + match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node); > + plat_data = match->data; > + hdmi->dev = &pdev->dev; > + encoder = &hdmi->encoder; > + platform_set_drvdata(pdev, hdmi); > + > + ret = rockchip_hdmi_parse_dt(hdmi); > + if (ret) { > + dev_err(hdmi->dev, "Unable to parse OF data\n"); > + return ret; > + } > + > + ret = clk_prepare_enable(hdmi->clk); > + if (ret) { > + dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret); > + return ret; > + } > + > + ret = clk_prepare_enable(hdmi->hdcp_clk); > + if (ret) { > + dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret); > + return ret; > + } Could we have a look at the clocks again? Basically the Rockchip clock handling is exactly the same, except the clocks are called by other names. On i.MX6, according to the reference manual, the HDMI TX module has four clock inputs: "iahbclk" (bus clock), "icecclk" (32 kHz CEC clock), "ihclk" (module clock), and "isfrclk" (27 MHz internal SFR clock). The "iahbclk" and "ihclk" are both sourced from the SoC AHB root clock, the 32 kHz reference input can't be gated, and the "isfrclk" has its own gate. Does the HDMI TX implementation on Rockchip still have the separate external sfr bus and module clock inputs? I assume that your "clk" input is a single gate bit for bus and module clocks at the same time? If possible, I'd prefer to find a common binding for the clocks with some of the clocks being optional, but for that we need to know the actual clock inputs to the HDMI TX module. regards Philipp
Hi Philipp: On 2014?12?02? 18:24, Philipp Zabel wrote: > Hi Andy, > > Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan: > [...] >> +static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, >> + void *data) >> +{ >> + struct platform_device *pdev = to_platform_device(dev); >> + const struct dw_hdmi_plat_data *plat_data; >> + const struct of_device_id *match; >> + struct drm_device *drm = data; >> + struct drm_encoder *encoder; >> + struct rockchip_hdmi *hdmi; >> + int ret; >> + >> + if (!pdev->dev.of_node) >> + return -ENODEV; >> + >> + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); >> + if (!hdmi) >> + return -ENOMEM; >> + >> + match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node); >> + plat_data = match->data; >> + hdmi->dev = &pdev->dev; >> + encoder = &hdmi->encoder; >> + platform_set_drvdata(pdev, hdmi); >> + >> + ret = rockchip_hdmi_parse_dt(hdmi); >> + if (ret) { >> + dev_err(hdmi->dev, "Unable to parse OF data\n"); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(hdmi->clk); >> + if (ret) { >> + dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_prepare_enable(hdmi->hdcp_clk); >> + if (ret) { >> + dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret); >> + return ret; >> + } > Could we have a look at the clocks again? Basically the Rockchip clock > handling is exactly the same, except the clocks are called by other > names. > > On i.MX6, according to the reference manual, the HDMI TX module has four > clock inputs: "iahbclk" (bus clock), "icecclk" (32 kHz CEC clock), > "ihclk" (module clock), and "isfrclk" (27 MHz internal SFR clock). > The "iahbclk" and "ihclk" are both sourced from the SoC AHB root clock, > the 32 kHz reference input can't be gated, and the "isfrclk" has its own > gate. > > Does the HDMI TX implementation on Rockchip still have the separate > external sfr bus and module clock inputs? I assume that your "clk" input > is a single gate bit for bus and module clocks at the same time? > If possible, I'd prefer to find a common binding for the clocks with > some of the clocks being optional, but for that we need to know the > actual clock inputs to the HDMI TX module. > > regards > Philipp > There are three individual clock inputs on Rockchip RK3288 HDMI: "hdmi_ctrl_clk", "hdmi_cec_clk", "hdmi_hdcp_clk", the three clocks are responsible for different functions as their name described, and have their own private gate bit. That is to say, the cec_clk and hdcp_clk can all be disabled if we don't need hdcp and cec function. So I think it's better to make the clk control platform independent. Heiko, do you have any suggestions? > >
Hi Andy, Am Dienstag, den 02.12.2014, 20:34 +0800 schrieb Andy Yan: > Hi Philipp: > On 2014?12?02? 18:24, Philipp Zabel wrote: > > Hi Andy, > > > > Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan: > > [...] > >> +static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, > >> + void *data) > >> +{ > >> + struct platform_device *pdev = to_platform_device(dev); > >> + const struct dw_hdmi_plat_data *plat_data; > >> + const struct of_device_id *match; > >> + struct drm_device *drm = data; > >> + struct drm_encoder *encoder; > >> + struct rockchip_hdmi *hdmi; > >> + int ret; > >> + > >> + if (!pdev->dev.of_node) > >> + return -ENODEV; > >> + > >> + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); > >> + if (!hdmi) > >> + return -ENOMEM; > >> + > >> + match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node); > >> + plat_data = match->data; > >> + hdmi->dev = &pdev->dev; > >> + encoder = &hdmi->encoder; > >> + platform_set_drvdata(pdev, hdmi); > >> + > >> + ret = rockchip_hdmi_parse_dt(hdmi); > >> + if (ret) { > >> + dev_err(hdmi->dev, "Unable to parse OF data\n"); > >> + return ret; > >> + } > >> + > >> + ret = clk_prepare_enable(hdmi->clk); > >> + if (ret) { > >> + dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret); > >> + return ret; > >> + } > >> + > >> + ret = clk_prepare_enable(hdmi->hdcp_clk); > >> + if (ret) { > >> + dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret); > >> + return ret; > >> + } > > Could we have a look at the clocks again? Basically the Rockchip clock > > handling is exactly the same, except the clocks are called by other > > names. > > > > On i.MX6, according to the reference manual, the HDMI TX module has four > > clock inputs: "iahbclk" (bus clock), "icecclk" (32 kHz CEC clock), > > "ihclk" (module clock), and "isfrclk" (27 MHz internal SFR clock). > > The "iahbclk" and "ihclk" are both sourced from the SoC AHB root clock, > > the 32 kHz reference input can't be gated, and the "isfrclk" has its own > > gate. > > > > Does the HDMI TX implementation on Rockchip still have the separate > > external sfr bus and module clock inputs? I assume that your "clk" input > > is a single gate bit for bus and module clocks at the same time? > > If possible, I'd prefer to find a common binding for the clocks with > > some of the clocks being optional, but for that we need to know the > > actual clock inputs to the HDMI TX module. > > > > regards > > Philipp > > > There are three individual clock inputs on Rockchip RK3288 HDMI: > "hdmi_ctrl_clk", > "hdmi_cec_clk", "hdmi_hdcp_clk", the three clocks are responsible > for different > functions as their name described, and have their own private gate > bit. That is > to say, the cec_clk and hdcp_clk can all be disabled if we don't > need hdcp and cec > function. > So I think it's better to make the clk control platform independent. My question is not about the available gates at the SoC level, but about the actual clock inputs from point of view of the HDMI TX IP. It could be that the hdmi_ctrl_clk gates all inputs to the module and bus clocks together. If so, you could just reuse "isfr" and "iahb" and set it to the same clock. If not, we'd need to think of something else. Unfortunately I don't have any Synopsys documentation of the HDMI TX at that level. regards Philipp
Hi Philipp: On 2014?12?02? 21:00, Philipp Zabel wrote: > Hi Andy, > > Am Dienstag, den 02.12.2014, 20:34 +0800 schrieb Andy Yan: >> Hi Philipp: >> On 2014?12?02? 18:24, Philipp Zabel wrote: >>> Hi Andy, >>> >>> Am Dienstag, den 02.12.2014, 15:45 +0800 schrieb Andy Yan: >>> [...] >>>> +static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, >>>> + void *data) >>>> +{ >>>> + struct platform_device *pdev = to_platform_device(dev); >>>> + const struct dw_hdmi_plat_data *plat_data; >>>> + const struct of_device_id *match; >>>> + struct drm_device *drm = data; >>>> + struct drm_encoder *encoder; >>>> + struct rockchip_hdmi *hdmi; >>>> + int ret; >>>> + >>>> + if (!pdev->dev.of_node) >>>> + return -ENODEV; >>>> + >>>> + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); >>>> + if (!hdmi) >>>> + return -ENOMEM; >>>> + >>>> + match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node); >>>> + plat_data = match->data; >>>> + hdmi->dev = &pdev->dev; >>>> + encoder = &hdmi->encoder; >>>> + platform_set_drvdata(pdev, hdmi); >>>> + >>>> + ret = rockchip_hdmi_parse_dt(hdmi); >>>> + if (ret) { >>>> + dev_err(hdmi->dev, "Unable to parse OF data\n"); >>>> + return ret; >>>> + } >>>> + >>>> + ret = clk_prepare_enable(hdmi->clk); >>>> + if (ret) { >>>> + dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret); >>>> + return ret; >>>> + } >>>> + >>>> + ret = clk_prepare_enable(hdmi->hdcp_clk); >>>> + if (ret) { >>>> + dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret); >>>> + return ret; >>>> + } >>> Could we have a look at the clocks again? Basically the Rockchip clock >>> handling is exactly the same, except the clocks are called by other >>> names. >>> >>> On i.MX6, according to the reference manual, the HDMI TX module has four >>> clock inputs: "iahbclk" (bus clock), "icecclk" (32 kHz CEC clock), >>> "ihclk" (module clock), and "isfrclk" (27 MHz internal SFR clock). >>> The "iahbclk" and "ihclk" are both sourced from the SoC AHB root clock, >>> the 32 kHz reference input can't be gated, and the "isfrclk" has its own >>> gate. >>> >>> Does the HDMI TX implementation on Rockchip still have the separate >>> external sfr bus and module clock inputs? I assume that your "clk" input >>> is a single gate bit for bus and module clocks at the same time? >>> If possible, I'd prefer to find a common binding for the clocks with >>> some of the clocks being optional, but for that we need to know the >>> actual clock inputs to the HDMI TX module. >>> >>> regards >>> Philipp >>> >> There are three individual clock inputs on Rockchip RK3288 HDMI: >> "hdmi_ctrl_clk", >> "hdmi_cec_clk", "hdmi_hdcp_clk", the three clocks are responsible >> for different >> functions as their name described, and have their own private gate >> bit. That is >> to say, the cec_clk and hdcp_clk can all be disabled if we don't >> need hdcp and cec >> function. >> So I think it's better to make the clk control platform independent. > My question is not about the available gates at the SoC level, but about > the actual clock inputs from point of view of the HDMI TX IP. > > It could be that the hdmi_ctrl_clk gates all inputs to the module and > bus clocks together. If so, you could just reuse "isfr" and "iahb" and > set it to the same clock. If not, we'd need to think of something else. > Unfortunately I don't have any Synopsys documentation of the HDMI TX at > that level. After confirming with the IC designer, we finally make clear that Rockchip RK3288 almost use the same clock design with imx: clk-----iahbclk, used for hdmi module and bus hdcp_clk-----isfrclk, used for hdcp and i2cm cecclk -----cecclk, but this clk can be gated on rockchip, this is different with imx, but we don't handle the cec stuff now. So i will try to reuse the imx clk binds. do you think that is ok? > regards > Philipp > > > >
Hi Andy, Am Mittwoch, den 03.12.2014, 20:32 +0800 schrieb Andy Yan: > > My question is not about the available gates at the SoC level, but about > > the actual clock inputs from point of view of the HDMI TX IP. > > > > It could be that the hdmi_ctrl_clk gates all inputs to the module and > > bus clocks together. If so, you could just reuse "isfr" and "iahb" and > > set it to the same clock. If not, we'd need to think of something else. > > Unfortunately I don't have any Synopsys documentation of the HDMI TX at > > that level. > > After confirming with the IC designer, we finally make clear that > Rockchip RK3288 almost use the same clock design with imx: > clk-----iahbclk, used for hdmi module and bus > hdcp_clk-----isfrclk, used for hdcp and i2cm > cecclk -----cecclk, but this clk can be gated on rockchip, this is > different with imx, > but we don't handle the cec stuff now. So i will try to reuse the > imx clk binds. do you > think that is ok? Thank you for taking the time to verify this. So we should move the clock handling out of the soc specific parts into the common driver and reuse the existing clock bindings ("iahb", "isfr"). I'd suggest to add the "cec" clock now to the binding document as an optional clock, then you can already specify it in the rockchip dtsi. regards Philipp
Hi Philipp: On 2014?12?03? 21:09, Philipp Zabel wrote: > Hi Andy, > > Am Mittwoch, den 03.12.2014, 20:32 +0800 schrieb Andy Yan: >>> My question is not about the available gates at the SoC level, but about >>> the actual clock inputs from point of view of the HDMI TX IP. >>> >>> It could be that the hdmi_ctrl_clk gates all inputs to the module and >>> bus clocks together. If so, you could just reuse "isfr" and "iahb" and >>> set it to the same clock. If not, we'd need to think of something else. >>> Unfortunately I don't have any Synopsys documentation of the HDMI TX at >>> that level. >> After confirming with the IC designer, we finally make clear that >> Rockchip RK3288 almost use the same clock design with imx: >> clk-----iahbclk, used for hdmi module and bus >> hdcp_clk-----isfrclk, used for hdcp and i2cm >> cecclk -----cecclk, but this clk can be gated on rockchip, this is >> different with imx, >> but we don't handle the cec stuff now. So i will try to reuse the >> imx clk binds. do you >> think that is ok? > Thank you for taking the time to verify this. So we should move the > clock handling out of the soc specific parts into the common driver and > reuse the existing clock bindings ("iahb", "isfr"). > I'd suggest to add the "cec" clock now to the binding document as an > optional clock, then you can already specify it in the rockchip dtsi. ok > > regards > Philipp > > >
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 961693a..8772abd 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -849,6 +849,9 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, dw_hdmi_phy_gen2_txpwron(hdmi, 1); dw_hdmi_phy_gen2_pddq(hdmi, 0); + if (hdmi->dev_type == RK3288_HDMI) + dw_hdmi_phy_enable_spare(hdmi, 1); + /*Wait for PHY PLL lock */ msec = 5; do { diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 0ff6682..06371ae 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -15,3 +15,13 @@ config DRM_ROCKCHIP management to userspace. This driver does not provide 2D or 3D acceleration; acceleration is performed by other IP found on the SoC. + +config ROCKCHIP_DW_HDMI + bool "Rockchip specific extensions for Synopsys DW HDMI" + depends on DRM_ROCKCHIP + select DRM_DW_HDMI + help + This selects support for Rockchip SoC specific extensions + for the Synopsys DesignWare HDMI driver. If you want to + enable HDMI on RK3288 based SoC, you should selet this + option. diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile index b3a5193..347e65c 100644 --- a/drivers/gpu/drm/rockchip/Makefile +++ b/drivers/gpu/drm/rockchip/Makefile @@ -4,5 +4,5 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \ rockchip_drm_gem.o rockchip_drm_vop.o - +rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c new file mode 100644 index 0000000..99144f8 --- /dev/null +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> +#include <linux/clk.h> +#include <drm/drm_of.h> +#include <drm/drmP.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_edid.h> +#include <drm/drm_encoder_slave.h> +#include <drm/bridge/dw_hdmi.h> + +#include "rockchip_drm_drv.h" +#include "rockchip_drm_vop.h" + +#define GRF_SOC_CON6 0x025c +#define HDMI_SEL_VOP_LIT (1 << 4) + +struct rockchip_hdmi { + struct device *dev; + struct clk *clk; + struct clk *hdcp_clk; + struct regmap *regmap; + struct drm_encoder encoder; +}; + +#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) + +static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { + { + 27000000, { + { 0x00b3, 0x0000}, + { 0x2153, 0x0000}, + { 0x40f3, 0x0000} + }, + }, { + 36000000, { + { 0x00b3, 0x0000}, + { 0x2153, 0x0000}, + { 0x40f3, 0x0000} + }, + }, { + 40000000, { + { 0x00b3, 0x0000}, + { 0x2153, 0x0000}, + { 0x40f3, 0x0000} + }, + }, { + 54000000, { + { 0x0072, 0x0001}, + { 0x2142, 0x0001}, + { 0x40a2, 0x0001}, + }, + }, { + 65000000, { + { 0x0072, 0x0001}, + { 0x2142, 0x0001}, + { 0x40a2, 0x0001}, + }, + }, { + 66000000, { + { 0x013e, 0x0003}, + { 0x217e, 0x0002}, + { 0x4061, 0x0002} + }, + }, { + 74250000, { + { 0x0072, 0x0001}, + { 0x2145, 0x0002}, + { 0x4061, 0x0002} + }, + }, { + 83500000, { + { 0x0072, 0x0001}, + }, + }, { + 108000000, { + { 0x0051, 0x0002}, + { 0x2145, 0x0002}, + { 0x4061, 0x0002} + }, + }, { + 106500000, { + { 0x0051, 0x0002}, + { 0x2145, 0x0002}, + { 0x4061, 0x0002} + }, + }, { + 146250000, { + { 0x0051, 0x0002}, + { 0x2145, 0x0002}, + { 0x4061, 0x0002} + }, + }, { + 148500000, { + { 0x0051, 0x0003}, + { 0x214c, 0x0003}, + { 0x4064, 0x0003} + }, + }, { + ~0UL, { + { 0x00a0, 0x000a }, + { 0x2001, 0x000f }, + { 0x4002, 0x000f }, + }, + } +}; + +static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { + /* pixelclk bpp8 bpp10 bpp12 */ + { + 40000000, { 0x0018, 0x0018, 0x0018 }, + }, { + 65000000, { 0x0028, 0x0028, 0x0028 }, + }, { + 66000000, { 0x0038, 0x0038, 0x0038 }, + }, { + 74250000, { 0x0028, 0x0038, 0x0038 }, + }, { + 83500000, { 0x0028, 0x0038, 0x0038 }, + }, { + 146250000, { 0x0038, 0x0038, 0x0038 }, + }, { + 148500000, { 0x0000, 0x0038, 0x0038 }, + }, { + ~0UL, { 0x0000, 0x0000, 0x0000}, + } +}; + +static const struct dw_hdmi_sym_term rockchip_sym_term[] = { + /*pixelclk symbol term*/ + { 74250000, 0x8009, 0x0004 }, + { 148500000, 0x8029, 0x0004 }, + { 297000000, 0x8039, 0x0005 }, + { ~0UL, 0x0000, 0x0000 } +}; + +static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) +{ + struct device_node *np = hdmi->dev->of_node; + + hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); + if (IS_ERR(hdmi->regmap)) { + dev_err(hdmi->dev, "Unable to get rockchip,grf\n"); + return PTR_ERR(hdmi->regmap); + } + + hdmi->clk = devm_clk_get(hdmi->dev, "clk"); + if (IS_ERR(hdmi->clk)) { + dev_err(hdmi->dev, "Unable to get HDMI clk\n"); + return PTR_ERR(hdmi->clk); + } + + hdmi->hdcp_clk = devm_clk_get(hdmi->dev, "hdcp_clk"); + if (IS_ERR(hdmi->hdcp_clk)) { + dev_err(hdmi->dev, "Unable to get HDMI hdcp clk\n"); + return PTR_ERR(hdmi->hdcp_clk); + } + + return 0; +} + +static enum drm_mode_status +dw_hdmi_rockchip_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; + int pclk = mode->clock * 1000; + bool valid = false; + int i; + + for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { + if (pclk == mpll_cfg[i].mpixelclock) { + valid = true; + break; + } + } + + return (valid) ? MODE_OK : MODE_BAD; +} + +static struct drm_encoder_funcs dw_hdmi_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static void dw_hdmi_rockchip_disable(struct drm_encoder *encoder) +{ +} + +static bool dw_hdmi_rockchip_mode_fixup(struct drm_encoder *encoder, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static void dw_hdmi_rockchip_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ +} + +static void dw_hdmi_rockchip_commit(struct drm_encoder *encoder) +{ + struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder); + u32 val; + int mux; + + mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); + if (mux) + val = HDMI_SEL_VOP_LIT | (HDMI_SEL_VOP_LIT << 16); + else + val = HDMI_SEL_VOP_LIT << 16; + + regmap_write(hdmi->regmap, GRF_SOC_CON6, val); + dev_dbg(hdmi->dev, "vop %s output to hdmi\n", + (mux) ? "LIT" : "BIG"); +} + +static void dw_hdmi_rockchip_prepare(struct drm_encoder *encoder) +{ + rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA, + ROCKCHIP_OUT_MODE_AAAA); +} + +static struct drm_encoder_helper_funcs dw_hdmi_encoder_helper_funcs = { + .mode_fixup = dw_hdmi_rockchip_mode_fixup, + .mode_set = dw_hdmi_rockchip_mode_set, + .prepare = dw_hdmi_rockchip_prepare, + .commit = dw_hdmi_rockchip_commit, + .disable = dw_hdmi_rockchip_disable, +}; + +static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .sym_term = rockchip_sym_term, + .dev_type = RK3288_HDMI, +}; + +static const struct of_device_id dw_hdmi_rockchip_ids[] = { + { .compatible = "rockchip,rk3288-dw-hdmi", + .data = &rockchip_hdmi_drv_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids); + +static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + const struct dw_hdmi_plat_data *plat_data; + const struct of_device_id *match; + struct drm_device *drm = data; + struct drm_encoder *encoder; + struct rockchip_hdmi *hdmi; + int ret; + + if (!pdev->dev.of_node) + return -ENODEV; + + hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + match = of_match_node(dw_hdmi_rockchip_ids, pdev->dev.of_node); + plat_data = match->data; + hdmi->dev = &pdev->dev; + encoder = &hdmi->encoder; + platform_set_drvdata(pdev, hdmi); + + ret = rockchip_hdmi_parse_dt(hdmi); + if (ret) { + dev_err(hdmi->dev, "Unable to parse OF data\n"); + return ret; + } + + ret = clk_prepare_enable(hdmi->clk); + if (ret) { + dev_err(hdmi->dev, "Cannot enable HDMI clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(hdmi->hdcp_clk); + if (ret) { + dev_err(hdmi->dev, "Cannot enable HDMI hdcp clock: %d\n", ret); + return ret; + } + + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); + + drm_encoder_helper_add(encoder, &dw_hdmi_encoder_helper_funcs); + drm_encoder_init(drm, encoder, &dw_hdmi_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + + return dw_hdmi_bind(dev, master, data, encoder, plat_data); +} + +static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct rockchip_hdmi *hdmi = platform_get_drvdata(pdev); + + clk_disable_unprepare(hdmi->clk); + clk_disable_unprepare(hdmi->hdcp_clk); + + return dw_hdmi_unbind(dev, master, data); +} + +static const struct component_ops dw_hdmi_rockchip_ops = { + .bind = dw_hdmi_rockchip_bind, + .unbind = dw_hdmi_rockchip_unbind, +}; + +static int dw_hdmi_rockchip_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); +} + +static int dw_hdmi_rockchip_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dw_hdmi_rockchip_ops); + + return 0; +} + +static struct platform_driver dw_hdmi_rockchip_pltfm_driver = { + .probe = dw_hdmi_rockchip_probe, + .remove = dw_hdmi_rockchip_remove, + .driver = { + .name = "dwhdmi-rockchip", + .of_match_table = dw_hdmi_rockchip_ids, + }, +}; + +module_platform_driver(dw_hdmi_rockchip_pltfm_driver); + +MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); +MODULE_DESCRIPTION("Rockchip Specific DW-HDMI Driver Extension"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:dwhdmi-rockchip"); diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index fff6ae6..ca98ee0 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -22,6 +22,7 @@ enum { enum dw_hdmi_devtype { IMX6Q_HDMI, IMX6DL_HDMI, + RK3288_HDMI, }; struct dw_hdmi_mpll_config {
Rockchip RK3288 hdmi is compatible with dw_hdmi this patch is depend on patch by Mark Yao Add drm driver for Rockchip Socs see https://lkml.org/lkml/2014/11/19/1153 Signed-off-by: Andy Yan <andy.yan@rock-chips.com> --- Changes in v15: - remove THIS_MODULE in platform driver Changes in v14: None Changes in v13: None Changes in v12: - add comment for the depend on patch Changes in v11: None Changes in v10: - add more display mode support mpll configuration for rk3288 Changes in v9: - move some phy configuration to platform driver Changes in v8: None Changes in v7: None Changes in v6: None Changes in v5: None Changes in v4: None Changes in v3: None drivers/gpu/drm/bridge/dw_hdmi.c | 3 + drivers/gpu/drm/rockchip/Kconfig | 10 + drivers/gpu/drm/rockchip/Makefile | 2 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 354 ++++++++++++++++++++++++++++ include/drm/bridge/dw_hdmi.h | 1 + 5 files changed, 369 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c