| Message ID | 1421756480-7055-4-git-send-email-zidan.wang@freescale.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 20, 2015 at 08:21:20PM +0800, Zidan Wang wrote: > Add Right-J mode and set TCR5 FBT bit to let data right justify. > > Signed-off-by: Zidan Wang <zidan.wang@freescale.com> > - if (sai->is_lsb_first) > + if (sai->is_lsb_first && sai->is_right_j_mode) > val_cr5 |= FSL_SAI_CR5_FBT(0); Are you sure that FBT(0) is correct for right justified mode? Because the original code is using FBT(0) for the lsb_first situation and it shouldn't be right justified mode as default. Nicolin
On Wed, Jan 21, 2015 at 10:53:20AM -0800, Nicolin Chen wrote: > On Tue, Jan 20, 2015 at 08:21:20PM +0800, Zidan Wang wrote: > > Add Right-J mode and set TCR5 FBT bit to let data right justify. > > > > Signed-off-by: Zidan Wang <zidan.wang@freescale.com> > > > - if (sai->is_lsb_first) > > + if (sai->is_lsb_first && sai->is_right_j_mode) > > val_cr5 |= FSL_SAI_CR5_FBT(0); > > Are you sure that FBT(0) is correct for right justified mode? > Because the original code is using FBT(0) for the lsb_first > situation and it shouldn't be right justified mode as default. > I am not sure about that. I assume lsb_first as big endian data. For 16 bit data format, the 2 bytes data will in high address of 4 bytes fifo. So the FBT is 16 for left-j and 0 for right-j. But big endian is bytes convert not bits convert. It makes me confuse. And send to community for help. > Nicolin
On Thu, Jan 22, 2015 at 01:13:46PM +0800, Zidan Wang wrote: > On Wed, Jan 21, 2015 at 10:53:20AM -0800, Nicolin Chen wrote: > > On Tue, Jan 20, 2015 at 08:21:20PM +0800, Zidan Wang wrote: > > > Add Right-J mode and set TCR5 FBT bit to let data right justify. > > > > > > Signed-off-by: Zidan Wang <zidan.wang@freescale.com> > > > > > - if (sai->is_lsb_first) > > > + if (sai->is_lsb_first && sai->is_right_j_mode) > > > val_cr5 |= FSL_SAI_CR5_FBT(0); > > > > Are you sure that FBT(0) is correct for right justified mode? > > Because the original code is using FBT(0) for the lsb_first > > situation and it shouldn't be right justified mode as default. > > > I am not sure about that. > > I assume lsb_first as big endian data. Correct. > For 16 bit data format, the 2 bytes data will in high address of 4 bytes > fifo. So the FBT is 16 for left-j and 0 for right-j. But big endian is > bytes convert not bits convert. It makes me confuse. And send to > community for help. Either waiting for Xiubo to test it or asking IC owner for help. Nicolin
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 4c5040d..19cd6f3 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -228,7 +228,11 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai, sai->is_dsp_mode = true; break; case SND_SOC_DAIFMT_RIGHT_J: - /* To be done */ + /* Frame high, one word length for frame sync */ + val_cr2 |= FSL_SAI_CR2_BCP; + sai->is_right_j_mode = true; + break; + default: return -EINVAL; } @@ -418,9 +422,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, val_cr5 |= FSL_SAI_CR5_WNW(sai->slot_width); val_cr5 |= FSL_SAI_CR5_W0W(sai->slot_width); - if (sai->is_lsb_first) + if (sai->is_lsb_first && sai->is_right_j_mode) val_cr5 |= FSL_SAI_CR5_FBT(0); - else + else if (sai->is_lsb_first && !sai->is_right_j_mode) + val_cr5 |= FSL_SAI_CR5_FBT(sai->slot_width - word_width); + else if (!sai->is_lsb_first && sai->is_right_j_mode) + val_cr5 |= FSL_SAI_CR5_FBT(sai->slot_width - 1); + else if (!sai->is_lsb_first && !sai->is_right_j_mode) val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1); val_cr4 |= FSL_SAI_CR4_FRSZ(sai->slots * channels); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 111dfce..e220940 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -137,6 +137,7 @@ struct fsl_sai { bool is_lsb_first; bool is_slave_mode; bool is_dsp_mode; + bool is_right_j_mode; bool sai_on_imx; bool synchronous[2];
Add Right-J mode and set TCR5 FBT bit to let data right justify. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> --- sound/soc/fsl/fsl_sai.c | 14 +++++++++++--- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-)