diff mbox

[1/5] ath9k: Add PCIE powersave macros

Message ID 1425891010-21522-2-git-send-email-sujith@msujith.org (mailing list archive)
State Accepted
Delegated to: Kalle Valo
Headers show

Commit Message

Sujith Manoharan March 9, 2015, 8:50 a.m. UTC 
From: Sujith Manoharan <c_manoha@qca.qualcomm.com>

These will be used to handle chip-specific
power save configuration.

Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
 drivers/net/wireless/ath/ath9k/hw.h | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Kalle Valo March 13, 2015, 1:20 p.m. UTC | #1 
> From: Sujith Manoharan <c_manoha@qca.qualcomm.com>
> 
> These will be used to handle chip-specific
> power save configuration.
> 
> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>

Thanks, 5 patches applied to wireless-drivers-next.git:

e519f78f1191 ath9k: Add PCIE powersave macros
afa7e6dbd91d ath9k: Fix PLL powersave for AR9485
656cd75c3873 ath9k: Initialize pll_pwrsave for AR9462/AR9565
93f7d6f3d5aa ath9k: Check allowed PCIE powersave configuration
dd2951124838 ath9k: Fix RTT chainmask usage

Kalle Valo
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diff mbox

Patch

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 29a25d9..2bb3b33 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -309,6 +309,12 @@  enum ath9k_hw_hang_checks {
 	HW_MAC_HANG               = BIT(5),
 };
 
+#define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
+#define AR_PCIE_PLL_PWRSAVE_ON_D3   BIT(1)
+#define AR_PCIE_PLL_PWRSAVE_ON_D0   BIT(2)
+#define AR_PCIE_CDR_PWRSAVE_ON_D3   BIT(3)
+#define AR_PCIE_CDR_PWRSAVE_ON_D0   BIT(4)
+
 struct ath9k_ops_config {
 	int dma_beacon_response_time;
 	int sw_beacon_response_time;