diff mbox

[1/4] drm/i915/dsi: abstract dsi bpp derivation from pixel format

Message ID f273aeaf1ac1f1d372bedb8c007f57ab0268c3e3.1431440230.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula May 12, 2015, 2:20 p.m. UTC 
Nuke three copies of the same switch case.

Hopefully we can switch to a drm generic function later on, but that
will require us to swich to enum mipi_dsi_pixel_format first.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c | 67 +++++++++++++-----------------------
 1 file changed, 24 insertions(+), 43 deletions(-)

Comments

Ville Syrjälä May 12, 2015, 2:45 p.m. UTC | #1 
On Tue, May 12, 2015 at 05:20:38PM +0300, Jani Nikula wrote:
> Nuke three copies of the same switch case.
> 
> Hopefully we can switch to a drm generic function later on, but that
> will require us to swich to enum mipi_dsi_pixel_format first.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 67 +++++++++++++-----------------------
>  1 file changed, 24 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index cfd527765156..9ada06ec88e5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -38,6 +38,27 @@
>  #define DSI_HFP_PACKET_EXTRA_SIZE	6
>  #define DSI_EOTP_PACKET_SIZE		4
>  
> +static int dsi_pixel_format_bpp(int pixel_format)
> +{
> +	int bpp;
> +
> +	switch (pixel_format) {
> +	default:
> +	case VID_MODE_FORMAT_RGB888:
> +	case VID_MODE_FORMAT_RGB666_LOOSE:
> +		bpp = 24;
> +		break;
> +	case VID_MODE_FORMAT_RGB666:
> +		bpp = 18;
> +		break;
> +	case VID_MODE_FORMAT_RGB565:
> +		bpp = 16;
> +		break;
> +	}
> +
> +	return bpp;
> +}

Optional bikeshed: Could return directly from the switch cases and avoid
the local variable.

But anyway:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +
>  struct dsi_mnp {
>  	u32 dsi_pll_ctrl;
>  	u32 dsi_pll_div;
> @@ -65,19 +86,7 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>  	u32 dsi_bit_clock_hz;
>  	u32 dsi_clk;
>  
> -	switch (pixel_format) {
> -	default:
> -	case VID_MODE_FORMAT_RGB888:
> -	case VID_MODE_FORMAT_RGB666_LOOSE:
> -		bpp = 24;
> -		break;
> -	case VID_MODE_FORMAT_RGB666:
> -		bpp = 18;
> -		break;
> -	case VID_MODE_FORMAT_RGB565:
> -		bpp = 16;
> -		break;
> -	}
> +	bpp = dsi_pixel_format_bpp(pixel_format);
>  
>  	hactive = mode->hdisplay;
>  	vactive = mode->vdisplay;
> @@ -137,21 +146,7 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>  static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>  {
>  	u32 dsi_clk_khz;
> -	u32 bpp;
> -
> -	switch (pixel_format) {
> -	default:
> -	case VID_MODE_FORMAT_RGB888:
> -	case VID_MODE_FORMAT_RGB666_LOOSE:
> -		bpp = 24;
> -		break;
> -	case VID_MODE_FORMAT_RGB666:
> -		bpp = 18;
> -		break;
> -	case VID_MODE_FORMAT_RGB565:
> -		bpp = 16;
> -		break;
> -	}
> +	u32 bpp = dsi_pixel_format_bpp(pixel_format);
>  
>  	/* DSI data rate = pixel clock * bits per pixel / lane count
>  	   pixel clock is converted from KHz to Hz */
> @@ -285,21 +280,7 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>  
>  static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
>  {
> -	int bpp;
> -
> -	switch (pixel_format) {
> -	default:
> -	case VID_MODE_FORMAT_RGB888:
> -	case VID_MODE_FORMAT_RGB666_LOOSE:
> -		bpp = 24;
> -		break;
> -	case VID_MODE_FORMAT_RGB666:
> -		bpp = 18;
> -		break;
> -	case VID_MODE_FORMAT_RGB565:
> -		bpp = 16;
> -		break;
> -	}
> +	int bpp = dsi_pixel_format_bpp(pixel_format);
>  
>  	WARN(bpp != pipe_bpp,
>  	     "bpp match assertion failure (expected %d, current %d)\n",
> -- 
> 2.1.4
Jani Nikula May 13, 2015, 7:28 a.m. UTC | #2 
On Tue, 12 May 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, May 12, 2015 at 05:20:38PM +0300, Jani Nikula wrote:
>> Nuke three copies of the same switch case.
>> 
>> Hopefully we can switch to a drm generic function later on, but that
>> will require us to swich to enum mipi_dsi_pixel_format first.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi_pll.c | 67 +++++++++++++-----------------------
>>  1 file changed, 24 insertions(+), 43 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> index cfd527765156..9ada06ec88e5 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
>> @@ -38,6 +38,27 @@
>>  #define DSI_HFP_PACKET_EXTRA_SIZE	6
>>  #define DSI_EOTP_PACKET_SIZE		4
>>  
>> +static int dsi_pixel_format_bpp(int pixel_format)
>> +{
>> +	int bpp;
>> +
>> +	switch (pixel_format) {
>> +	default:
>> +	case VID_MODE_FORMAT_RGB888:
>> +	case VID_MODE_FORMAT_RGB666_LOOSE:
>> +		bpp = 24;
>> +		break;
>> +	case VID_MODE_FORMAT_RGB666:
>> +		bpp = 18;
>> +		break;
>> +	case VID_MODE_FORMAT_RGB565:
>> +		bpp = 16;
>> +		break;
>> +	}
>> +
>> +	return bpp;
>> +}
>
> Optional bikeshed: Could return directly from the switch cases and avoid
> the local variable.

The compiler appears to automatically inline the function (*and* two
functions it is called from), so does not make a difference.

Thanks for the review.

BR,
Jani.

>
> But anyway:
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>> +
>>  struct dsi_mnp {
>>  	u32 dsi_pll_ctrl;
>>  	u32 dsi_pll_div;
>> @@ -65,19 +86,7 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>>  	u32 dsi_bit_clock_hz;
>>  	u32 dsi_clk;
>>  
>> -	switch (pixel_format) {
>> -	default:
>> -	case VID_MODE_FORMAT_RGB888:
>> -	case VID_MODE_FORMAT_RGB666_LOOSE:
>> -		bpp = 24;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB666:
>> -		bpp = 18;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB565:
>> -		bpp = 16;
>> -		break;
>> -	}
>> +	bpp = dsi_pixel_format_bpp(pixel_format);
>>  
>>  	hactive = mode->hdisplay;
>>  	vactive = mode->vdisplay;
>> @@ -137,21 +146,7 @@ static u32 dsi_rr_formula(const struct drm_display_mode *mode,
>>  static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
>>  {
>>  	u32 dsi_clk_khz;
>> -	u32 bpp;
>> -
>> -	switch (pixel_format) {
>> -	default:
>> -	case VID_MODE_FORMAT_RGB888:
>> -	case VID_MODE_FORMAT_RGB666_LOOSE:
>> -		bpp = 24;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB666:
>> -		bpp = 18;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB565:
>> -		bpp = 16;
>> -		break;
>> -	}
>> +	u32 bpp = dsi_pixel_format_bpp(pixel_format);
>>  
>>  	/* DSI data rate = pixel clock * bits per pixel / lane count
>>  	   pixel clock is converted from KHz to Hz */
>> @@ -285,21 +280,7 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>>  
>>  static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
>>  {
>> -	int bpp;
>> -
>> -	switch (pixel_format) {
>> -	default:
>> -	case VID_MODE_FORMAT_RGB888:
>> -	case VID_MODE_FORMAT_RGB666_LOOSE:
>> -		bpp = 24;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB666:
>> -		bpp = 18;
>> -		break;
>> -	case VID_MODE_FORMAT_RGB565:
>> -		bpp = 16;
>> -		break;
>> -	}
>> +	int bpp = dsi_pixel_format_bpp(pixel_format);
>>  
>>  	WARN(bpp != pipe_bpp,
>>  	     "bpp match assertion failure (expected %d, current %d)\n",
>> -- 
>> 2.1.4
>
> -- 
> Ville Syrjälä
> Intel OTC
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cfd527765156..9ada06ec88e5 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -38,6 +38,27 @@ 
 #define DSI_HFP_PACKET_EXTRA_SIZE	6
 #define DSI_EOTP_PACKET_SIZE		4
 
+static int dsi_pixel_format_bpp(int pixel_format)
+{
+	int bpp;
+
+	switch (pixel_format) {
+	default:
+	case VID_MODE_FORMAT_RGB888:
+	case VID_MODE_FORMAT_RGB666_LOOSE:
+		bpp = 24;
+		break;
+	case VID_MODE_FORMAT_RGB666:
+		bpp = 18;
+		break;
+	case VID_MODE_FORMAT_RGB565:
+		bpp = 16;
+		break;
+	}
+
+	return bpp;
+}
+
 struct dsi_mnp {
 	u32 dsi_pll_ctrl;
 	u32 dsi_pll_div;
@@ -65,19 +86,7 @@  static u32 dsi_rr_formula(const struct drm_display_mode *mode,
 	u32 dsi_bit_clock_hz;
 	u32 dsi_clk;
 
-	switch (pixel_format) {
-	default:
-	case VID_MODE_FORMAT_RGB888:
-	case VID_MODE_FORMAT_RGB666_LOOSE:
-		bpp = 24;
-		break;
-	case VID_MODE_FORMAT_RGB666:
-		bpp = 18;
-		break;
-	case VID_MODE_FORMAT_RGB565:
-		bpp = 16;
-		break;
-	}
+	bpp = dsi_pixel_format_bpp(pixel_format);
 
 	hactive = mode->hdisplay;
 	vactive = mode->vdisplay;
@@ -137,21 +146,7 @@  static u32 dsi_rr_formula(const struct drm_display_mode *mode,
 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count)
 {
 	u32 dsi_clk_khz;
-	u32 bpp;
-
-	switch (pixel_format) {
-	default:
-	case VID_MODE_FORMAT_RGB888:
-	case VID_MODE_FORMAT_RGB666_LOOSE:
-		bpp = 24;
-		break;
-	case VID_MODE_FORMAT_RGB666:
-		bpp = 18;
-		break;
-	case VID_MODE_FORMAT_RGB565:
-		bpp = 16;
-		break;
-	}
+	u32 bpp = dsi_pixel_format_bpp(pixel_format);
 
 	/* DSI data rate = pixel clock * bits per pixel / lane count
 	   pixel clock is converted from KHz to Hz */
@@ -285,21 +280,7 @@  void vlv_disable_dsi_pll(struct intel_encoder *encoder)
 
 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
 {
-	int bpp;
-
-	switch (pixel_format) {
-	default:
-	case VID_MODE_FORMAT_RGB888:
-	case VID_MODE_FORMAT_RGB666_LOOSE:
-		bpp = 24;
-		break;
-	case VID_MODE_FORMAT_RGB666:
-		bpp = 18;
-		break;
-	case VID_MODE_FORMAT_RGB565:
-		bpp = 16;
-		break;
-	}
+	int bpp = dsi_pixel_format_bpp(pixel_format);
 
 	WARN(bpp != pipe_bpp,
 	     "bpp match assertion failure (expected %d, current %d)\n",