| Message ID | 1431607112-28875-1-git-send-email-tvrtko.ursulin@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, May 14, 2015 at 01:38:31PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > v2: Split strings to 80 char, add ddi_pll_sel and fixed typo. (Damien Lespiau) > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 52f9cbc..3ed8e2f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11418,6 +11418,39 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, > DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); > DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); > > + if (IS_BROXTON(dev)) { > + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " > + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " > + "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", > + pipe_config->ddi_pll_sel, > + pipe_config->dpll_hw_state.ebb0, > + pipe_config->dpll_hw_state.pll0, > + pipe_config->dpll_hw_state.pll1, > + pipe_config->dpll_hw_state.pll2, > + pipe_config->dpll_hw_state.pll3, > + pipe_config->dpll_hw_state.pll6, > + pipe_config->dpll_hw_state.pll8, > + pipe_config->dpll_hw_state.pcsdw12); > + } else if (IS_SKYLAKE(dev)) { > + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " > + "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", > + pipe_config->ddi_pll_sel, > + pipe_config->dpll_hw_state.ctrl1, > + pipe_config->dpll_hw_state.cfgcr1, > + pipe_config->dpll_hw_state.cfgcr2); > + } else if (HAS_DDI(dev)) { > + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", > + pipe_config->ddi_pll_sel, > + pipe_config->dpll_hw_state.wrpll); > + } else { > + DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " > + "fp0: 0x%x, fp1: 0x%x\n", > + pipe_config->dpll_hw_state.dpll, > + pipe_config->dpll_hw_state.dpll_md, > + pipe_config->dpll_hw_state.fp0, > + pipe_config->dpll_hw_state.fp1); > + } > + > DRM_DEBUG_KMS("planes on this crtc\n"); > list_for_each_entry(plane, &dev->mode_config.plane_list, head) { > intel_plane = to_intel_plane(plane); > -- > 2.4.0 >
On Thu, May 14, 2015 at 01:58:40PM +0100, Damien Lespiau wrote: > On Thu, May 14, 2015 at 01:38:31PM +0100, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > v2: Split strings to 80 char, add ddi_pll_sel and fixed typo. (Damien Lespiau) > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Cc: Damien Lespiau <damien.lespiau@intel.com> > > Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Queued for -next, thanks for the patch. -Daniel
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 52f9cbc..3ed8e2f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11418,6 +11418,39 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); + if (IS_BROXTON(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, " + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " + "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.ebb0, + pipe_config->dpll_hw_state.pll0, + pipe_config->dpll_hw_state.pll1, + pipe_config->dpll_hw_state.pll2, + pipe_config->dpll_hw_state.pll3, + pipe_config->dpll_hw_state.pll6, + pipe_config->dpll_hw_state.pll8, + pipe_config->dpll_hw_state.pcsdw12); + } else if (IS_SKYLAKE(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " + "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.ctrl1, + pipe_config->dpll_hw_state.cfgcr1, + pipe_config->dpll_hw_state.cfgcr2); + } else if (HAS_DDI(dev)) { + DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", + pipe_config->ddi_pll_sel, + pipe_config->dpll_hw_state.wrpll); + } else { + DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + pipe_config->dpll_hw_state.dpll, + pipe_config->dpll_hw_state.dpll_md, + pipe_config->dpll_hw_state.fp0, + pipe_config->dpll_hw_state.fp1); + } + DRM_DEBUG_KMS("planes on this crtc\n"); list_for_each_entry(plane, &dev->mode_config.plane_list, head) { intel_plane = to_intel_plane(plane);