| Message ID | 1432310765-2218-11-git-send-email-uma.shankar@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 22 May 2015, Uma Shankar <uma.shankar@intel.com> wrote: > From: Shashank Sharma <shashank.sharma@intel.com> > > BXT's DSI PLL is different from that of VLV. So this patch > adds a new function to get the current DSI pixel clock based > on the PLL divider ratio and lane count. > > This function is required for intel_dsi_get_config() function. > > Signed-off-by: Shashank Sharma <shashank.sharma@intel.com> > Signed-off-by: Uma Shankar <uma.shankar@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 10 ++++++++-- > drivers/gpu/drm/i915/intel_dsi.h | 1 + > drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++++++++++++++++++++++++++++++++++ > 3 files changed, 44 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index 2663cdd..5fbcebe 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -714,7 +714,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > static void intel_dsi_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > - u32 pclk; > + u32 pclk = 0; Unnecessary initialization. > DRM_DEBUG_KMS("\n"); > > /* > @@ -723,7 +723,13 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, > */ > pipe_config->dpll_hw_state.dpll_md = 0; > > - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); > + if (IS_BROXTON(encoder->base.dev)) > + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); > + else if (IS_VALLEYVIEW(encoder->base.dev)) > + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); > + else > + DRM_ERROR("Invalid DSI device to get config\n"); Please drop the else branch. > + > if (!pclk) > return; > > diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h > index 8bc8d94..01e08e7 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.h > +++ b/drivers/gpu/drm/i915/intel_dsi.h > @@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) > extern void intel_enable_dsi_pll(struct intel_encoder *encoder); > extern void intel_disable_dsi_pll(struct intel_encoder *encoder); > extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); > +extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); > extern void bxt_dsi_program_clocks(struct drm_device *dev, int pipe); > extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, > enum port port); > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c > index 49330b0..073bd1f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -369,6 +369,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) > return pclk; > } > > +u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) > +{ > + u32 pclk; > + u32 dsi_clk; > + u32 dsi_ratio; > + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); > + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; > + > + /* Divide by zero */ > + if (!pipe_bpp) { > + DRM_ERROR("Invalid BPP(0)\n"); > + return 0; > + } > + > + dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & > + BXT_DSI_MASK_PLL_RATIO; > + > + /* Invalid DSI ratio ? */ > + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || > + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { > + DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); > + return 0; > + } > + > + dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; > + > + /* pixel_format and pipe_bpp should agree */ > + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); > + > + pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); > + > + DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); > + return pclk; > +} > + > void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) > { > u32 temp; > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 2663cdd..5fbcebe 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -714,7 +714,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, static void intel_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - u32 pclk; + u32 pclk = 0; DRM_DEBUG_KMS("\n"); /* @@ -723,7 +723,13 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, */ pipe_config->dpll_hw_state.dpll_md = 0; - pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + if (IS_BROXTON(encoder->base.dev)) + pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + else if (IS_VALLEYVIEW(encoder->base.dev)) + pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); + else + DRM_ERROR("Invalid DSI device to get config\n"); + if (!pclk) return; diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 8bc8d94..01e08e7 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder) extern void intel_enable_dsi_pll(struct intel_encoder *encoder); extern void intel_disable_dsi_pll(struct intel_encoder *encoder); extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); +extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp); extern void bxt_dsi_program_clocks(struct drm_device *dev, int pipe); extern void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port); diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 49330b0..073bd1f 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -369,6 +369,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) return pclk; } +u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) +{ + u32 pclk; + u32 dsi_clk; + u32 dsi_ratio; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; + + /* Divide by zero */ + if (!pipe_bpp) { + DRM_ERROR("Invalid BPP(0)\n"); + return 0; + } + + dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & + BXT_DSI_MASK_PLL_RATIO; + + /* Invalid DSI ratio ? */ + if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || + dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { + DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); + return 0; + } + + dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; + + /* pixel_format and pipe_bpp should agree */ + assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); + + pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); + + DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); + return pclk; +} + void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) { u32 temp;