diff mbox

drm/i915: Add the ddi get cdclk code for BXT.

Message ID 1433967508-23108-1-git-send-email-bob.j.paauwe@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paauwe, Bob J June 10, 2015, 8:18 p.m. UTC 
The registers and process differ from other platforms.

Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Shuang He June 14, 2015, 11:45 a.m. UTC | #1 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6564
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  287/287              287/287
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
Ville Syrjälä June 15, 2015, 8:59 a.m. UTC | #2 
On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> The registers and process differ from other platforms.
> 
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c38c297..41464a5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
>  	return 24000;
>  }
>  
> +static int broxton_get_display_clock_speed(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	uint32_t cdctl = I915_READ(CDCLK_CTL);
> +	uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> +

You should return 19.2MHz if the DE PLL isn't enabled.

> +	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> +		if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> +			return 576000;
> +		else /* PLL freq = 1248MHz */
> +			return 624000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> +		return 384000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> +		return 288000;
> +	case BXT_CDCLK_CD2X_DIV_SEL_4:
> +		return 144000;
> +	}
> +
> +	/* error case, assume higer PLL freq. */
> +	return 624000;
> +}
> +
>  static int broadwell_get_display_clock_speed(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
>  	if (IS_SKYLAKE(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			skylake_get_display_clock_speed;
> +	else if (IS_BROXTON(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			broxton_get_display_clock_speed;
>  	else if (IS_BROADWELL(dev))
>  		dev_priv->display.get_display_clock_speed =
>  			broadwell_get_display_clock_speed;
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Imre Deak June 17, 2015, 2:43 p.m. UTC | #3 
On ma, 2015-06-15 at 11:59 +0300, Ville Syrjälä wrote:
> On Wed, Jun 10, 2015 at 01:18:28PM -0700, Bob Paauwe wrote:
> > The registers and process differ from other platforms.
> > 
> > Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 27 +++++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c38c297..41464a5 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6687,6 +6687,30 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
> >  	return 24000;
> >  }
> >  
> > +static int broxton_get_display_clock_speed(struct drm_device *dev)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	uint32_t cdctl = I915_READ(CDCLK_CTL);
> > +	uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
> > +
> 
> You should return 19.2MHz if the DE PLL isn't enabled.

Agreed with Ville, Bob could you resend the patch with this fixed?

> > +	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
> > +	case BXT_CDCLK_CD2X_DIV_SEL_1:
> > +		if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
> > +			return 576000;
> > +		else /* PLL freq = 1248MHz */
> > +			return 624000;
> > +	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
> > +		return 384000;
> > +	case BXT_CDCLK_CD2X_DIV_SEL_2:
> > +		return 288000;
> > +	case BXT_CDCLK_CD2X_DIV_SEL_4:
> > +		return 144000;
> > +	}
> > +
> > +	/* error case, assume higer PLL freq. */
> > +	return 624000;
> > +}
> > +
> >  static int broadwell_get_display_clock_speed(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -14649,6 +14673,9 @@ static void intel_init_display(struct drm_device *dev)
> >  	if (IS_SKYLAKE(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			skylake_get_display_clock_speed;
> > +	else if (IS_BROXTON(dev))
> > +		dev_priv->display.get_display_clock_speed =
> > +			broxton_get_display_clock_speed;
> >  	else if (IS_BROADWELL(dev))
> >  		dev_priv->display.get_display_clock_speed =
> >  			broadwell_get_display_clock_speed;
> > -- 
> > 2.1.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c38c297..41464a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6687,6 +6687,30 @@  static int skylake_get_display_clock_speed(struct drm_device *dev)
 	return 24000;
 }
 
+static int broxton_get_display_clock_speed(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	uint32_t cdctl = I915_READ(CDCLK_CTL);
+	uint32_t pll_freq = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
+
+	switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
+	case BXT_CDCLK_CD2X_DIV_SEL_1:
+		if (pll_freq == BXT_DE_PLL_RATIO(60)) /* PLL freq = 1152MHz */
+			return 576000;
+		else /* PLL freq = 1248MHz */
+			return 624000;
+	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
+		return 384000;
+	case BXT_CDCLK_CD2X_DIV_SEL_2:
+		return 288000;
+	case BXT_CDCLK_CD2X_DIV_SEL_4:
+		return 144000;
+	}
+
+	/* error case, assume higer PLL freq. */
+	return 624000;
+}
+
 static int broadwell_get_display_clock_speed(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -14649,6 +14673,9 @@  static void intel_init_display(struct drm_device *dev)
 	if (IS_SKYLAKE(dev))
 		dev_priv->display.get_display_clock_speed =
 			skylake_get_display_clock_speed;
+	else if (IS_BROXTON(dev))
+		dev_priv->display.get_display_clock_speed =
+			broxton_get_display_clock_speed;
 	else if (IS_BROADWELL(dev))
 		dev_priv->display.get_display_clock_speed =
 			broadwell_get_display_clock_speed;