| Message ID | 1434451184-4518-3-git-send-email-abdiel.janulgue@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 16/06/2015 11:39, Abdiel Janulgue wrote: > GEN8 and above uses Execlists by default instead of the legacy > ringbuffer for batch execution. This patch enables the resource > streamer bits when required. > > Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com> > This version also adds the required bits to enable GEN8 Resource > Streamer context save and restore for Execlists. > > Cc: ville.syrjala@linux.intel.com > Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++-- > drivers/gpu/drm/i915/intel_lrc.h | 1 + > 2 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index fcb074b..b015e96 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1172,7 +1172,10 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, > return ret; > > /* FIXME(BDW): Address space and security selectors. */ > - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); > + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | > + (ppgtt<<8) | > + (dispatch_flags & I915_DISPATCH_RS ? > + MI_BATCH_RESOURCE_STREAMER : 0)); > intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); > intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); > intel_logical_ring_emit(ringbuf, MI_NOOP); > @@ -1726,7 +1729,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o > reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); > reg_state[CTX_CONTEXT_CONTROL+1] = > _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | > - CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); > + CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | > + CTX_CTRL_RS_CTX_ENABLE); > reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); > reg_state[CTX_RING_HEAD+1] = 0; > reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); > diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h > index adb731e4..de6087a 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.h > +++ b/drivers/gpu/drm/i915/intel_lrc.h > @@ -32,6 +32,7 @@ > #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) > #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) > #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) > +#define CTX_CTRL_RS_CTX_ENABLE (1 << 1) > #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370) > #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0) > > looks good to me, Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com> regards Arun
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fcb074b..b015e96 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1172,7 +1172,10 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, return ret; /* FIXME(BDW): Address space and security selectors. */ - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | + (ppgtt<<8) | + (dispatch_flags & I915_DISPATCH_RS ? + MI_BATCH_RESOURCE_STREAMER : 0)); intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); intel_logical_ring_emit(ringbuf, MI_NOOP); @@ -1726,7 +1729,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); reg_state[CTX_CONTEXT_CONTROL+1] = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | - CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); + CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | + CTX_CTRL_RS_CTX_ENABLE); reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); reg_state[CTX_RING_HEAD+1] = 0; reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index adb731e4..de6087a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -32,6 +32,7 @@ #define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244) #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) +#define CTX_CTRL_RS_CTX_ENABLE (1 << 1) #define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370) #define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
GEN8 and above uses Execlists by default instead of the legacy ringbuffer for batch execution. This patch enables the resource streamer bits when required. Patch is based on the initial work by Minu Mathai <minu.mathai@intel.com> This version also adds the required bits to enable GEN8 Resource Streamer context save and restore for Execlists. Cc: ville.syrjala@linux.intel.com Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com> --- drivers/gpu/drm/i915/intel_lrc.c | 8 ++++++-- drivers/gpu/drm/i915/intel_lrc.h | 1 + 2 files changed, 7 insertions(+), 2 deletions(-)