diff mbox

[10/43] drm/i915: Parametrize CSR_PROGRAM registers

Message ID 1442595836-23981-11-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä Sept. 18, 2015, 5:03 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_csr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

Comments

Mika Kuoppala Sept. 23, 2015, 2:15 p.m. UTC | #1 
ville.syrjala@linux.intel.com writes:

> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_csr.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index b69264d..8174335 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
>  /*
>  * SKL CSR registers for DC5 and DC6
>  */
> -#define CSR_PROGRAM_BASE		0x80000
> +#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
>  #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
>  #define CSR_HTP_ADDR_SKL		0x00500034
>  #define CSR_SSP_BASE			0x8F074
> @@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
>  	mutex_lock(&dev_priv->csr_lock);
>  	fw_size = dev_priv->csr.dmc_fw_size;
>  	for (i = 0; i < fw_size; i++)
> -		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> -			payload[i]);
> +		I915_WRITE(CSR_PROGRAM(i), payload[i]);
>  
>  	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
>  		I915_WRITE(dev_priv->csr.mmioaddr[i],
> @@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
>  {
>  	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
>  		  "CSR is not loaded.\n");
> -	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
> +	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
>  		  "CSR program storage start is NULL\n");
>  	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
>  	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
> -- 
> 2.4.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Daniel Vetter Sept. 23, 2015, 3:17 p.m. UTC | #2 
On Wed, Sep 23, 2015 at 05:15:55PM +0300, Mika Kuoppala wrote:
> ville.syrjala@linux.intel.com writes:
> 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

Merged the reviewed patches up to this one to dinq, thanks.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_csr.c | 7 +++----
> >  1 file changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> > index b69264d..8174335 100644
> > --- a/drivers/gpu/drm/i915/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/intel_csr.c
> > @@ -48,7 +48,7 @@ MODULE_FIRMWARE(I915_CSR_SKL);
> >  /*
> >  * SKL CSR registers for DC5 and DC6
> >  */
> > -#define CSR_PROGRAM_BASE		0x80000
> > +#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
> >  #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
> >  #define CSR_HTP_ADDR_SKL		0x00500034
> >  #define CSR_SSP_BASE			0x8F074
> > @@ -255,8 +255,7 @@ void intel_csr_load_program(struct drm_device *dev)
> >  	mutex_lock(&dev_priv->csr_lock);
> >  	fw_size = dev_priv->csr.dmc_fw_size;
> >  	for (i = 0; i < fw_size; i++)
> > -		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
> > -			payload[i]);
> > +		I915_WRITE(CSR_PROGRAM(i), payload[i]);
> >  
> >  	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
> >  		I915_WRITE(dev_priv->csr.mmioaddr[i],
> > @@ -456,7 +455,7 @@ void assert_csr_loaded(struct drm_i915_private *dev_priv)
> >  {
> >  	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
> >  		  "CSR is not loaded.\n");
> > -	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
> > +	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
> >  		  "CSR program storage start is NULL\n");
> >  	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
> >  	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
> > -- 
> > 2.4.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index b69264d..8174335 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -48,7 +48,7 @@  MODULE_FIRMWARE(I915_CSR_SKL);
 /*
 * SKL CSR registers for DC5 and DC6
 */
-#define CSR_PROGRAM_BASE		0x80000
+#define CSR_PROGRAM(i)			(0x80000 + (i) * 4)
 #define CSR_SSP_BASE_ADDR_GEN9		0x00002FC0
 #define CSR_HTP_ADDR_SKL		0x00500034
 #define CSR_SSP_BASE			0x8F074
@@ -255,8 +255,7 @@  void intel_csr_load_program(struct drm_device *dev)
 	mutex_lock(&dev_priv->csr_lock);
 	fw_size = dev_priv->csr.dmc_fw_size;
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM_BASE + i * 4,
-			payload[i]);
+		I915_WRITE(CSR_PROGRAM(i), payload[i]);
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
@@ -456,7 +455,7 @@  void assert_csr_loaded(struct drm_i915_private *dev_priv)
 {
 	WARN_ONCE(intel_csr_load_status_get(dev_priv) != FW_LOADED,
 		  "CSR is not loaded.\n");
-	WARN_ONCE(!I915_READ(CSR_PROGRAM_BASE),
+	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 		  "CSR program storage start is NULL\n");
 	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");