diff mbox

[v2,31/43] drm/i915: Throw out some useless variables

Message ID 1442940601-17011-1-git-send-email-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjala Sept. 22, 2015, 4:50 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop some useless 'reg' variables when we only use them once.

v2: A few more, including a few variable moves

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c      |  3 +-
 drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++-------------------------
 drivers/gpu/drm/i915/intel_dp.c      | 10 ++---
 3 files changed, 28 insertions(+), 60 deletions(-)

Comments

Jesse Barnes Oct. 12, 2015, 4:09 p.m. UTC | #1 
On 09/22/2015 09:50 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Drop some useless 'reg' variables when we only use them once.
> 
> v2: A few more, including a few variable moves
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c      |  3 +-
>  drivers/gpu/drm/i915/intel_display.c | 75 +++++++++++-------------------------
>  drivers/gpu/drm/i915/intel_dp.c      | 10 ++---
>  3 files changed, 28 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 4b61a42..d181dab 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -674,9 +674,8 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
>  static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int reg = PIPE_FRMCOUNT_G4X(pipe);
>  
> -	return I915_READ(reg);
> +	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
>  }
>  
>  /* raw reads, only for fast reads of display block, no need for forcewake etc. */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6f538d5..dc24e22 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1110,12 +1110,10 @@ static const char *state_string(bool enabled)
>  void assert_pll(struct drm_i915_private *dev_priv,
>  		enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = DPLL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(DPLL(pipe));
>  	cur_state = !!(val & DPLL_VCO_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "PLL state assertion failure (expected %s, current %s)\n",
> @@ -1172,20 +1170,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>  static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, bool state)
>  {
> -	int reg;
> -	u32 val;
>  	bool cur_state;
>  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
>  								      pipe);
>  
>  	if (HAS_DDI(dev_priv->dev)) {
>  		/* DDI does not have a specific FDI_TX register */
> -		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
>  		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
>  	} else {
> -		reg = FDI_TX_CTL(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(FDI_TX_CTL(pipe));
>  		cur_state = !!(val & FDI_TX_ENABLE);
>  	}
>  	I915_STATE_WARN(cur_state != state,
> @@ -1198,12 +1192,10 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>  static void assert_fdi_rx(struct drm_i915_private *dev_priv,
>  			  enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = FDI_RX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_RX_CTL(pipe));
>  	cur_state = !!(val & FDI_RX_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "FDI RX state assertion failure (expected %s, current %s)\n",
> @@ -1215,7 +1207,6 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
>  static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  				      enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  
>  	/* ILK FDI PLL is always enabled */
> @@ -1226,20 +1217,17 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>  	if (HAS_DDI(dev_priv->dev))
>  		return;
>  
> -	reg = FDI_TX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_TX_CTL(pipe));
>  	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
>  }
>  
>  void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
>  		       enum pipe pipe, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = FDI_RX_CTL(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(FDI_RX_CTL(pipe));
>  	cur_state = !!(val & FDI_RX_PLL_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
> @@ -1309,8 +1297,6 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
>  void assert_pipe(struct drm_i915_private *dev_priv,
>  		 enum pipe pipe, bool state)
>  {
> -	int reg;
> -	u32 val;
>  	bool cur_state;
>  	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
>  								      pipe);
> @@ -1324,8 +1310,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>  				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
>  		cur_state = false;
>  	} else {
> -		reg = PIPECONF(cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(PIPECONF(cpu_transcoder));
>  		cur_state = !!(val & PIPECONF_ENABLE);
>  	}
>  
> @@ -1337,12 +1322,10 @@ void assert_pipe(struct drm_i915_private *dev_priv,
>  static void assert_plane(struct drm_i915_private *dev_priv,
>  			 enum plane plane, bool state)
>  {
> -	int reg;
>  	u32 val;
>  	bool cur_state;
>  
> -	reg = DSPCNTR(plane);
> -	val = I915_READ(reg);
> +	val = I915_READ(DSPCNTR(plane));
>  	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
>  	I915_STATE_WARN(cur_state != state,
>  	     "plane %c assertion failure (expected %s, current %s)\n",
> @@ -1356,14 +1339,11 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
>  				   enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	int reg, i;
> -	u32 val;
> -	int cur_pipe;
> +	int i;
>  
>  	/* Primary planes are fixed to pipes on gen4+ */
>  	if (INTEL_INFO(dev)->gen >= 4) {
> -		reg = DSPCNTR(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(DSPCNTR(pipe));
>  		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
>  		     "plane %c assertion failure, should be disabled but not\n",
>  		     plane_name(pipe));
> @@ -1372,9 +1352,8 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
>  
>  	/* Need to check both planes against the pipe */
>  	for_each_pipe(dev_priv, i) {
> -		reg = DSPCNTR(i);
> -		val = I915_READ(reg);
> -		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> +		u32 val = I915_READ(DSPCNTR(i));
> +		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
>  			DISPPLANE_SEL_PIPE_SHIFT;
>  		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
>  		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
> @@ -1386,33 +1365,29 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>  				    enum pipe pipe)
>  {
>  	struct drm_device *dev = dev_priv->dev;
> -	int reg, sprite;
> -	u32 val;
> +	int sprite;
>  
>  	if (INTEL_INFO(dev)->gen >= 9) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
> -			val = I915_READ(PLANE_CTL(pipe, sprite));
> +			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
>  			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
>  			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite, pipe_name(pipe));
>  		}
>  	} else if (IS_VALLEYVIEW(dev)) {
>  		for_each_sprite(dev_priv, pipe, sprite) {
> -			reg = SPCNTR(pipe, sprite);
> -			val = I915_READ(reg);
> +			u32 val = I915_READ(SPCNTR(pipe, sprite));
>  			I915_STATE_WARN(val & SP_ENABLE,
>  			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  			     sprite_name(pipe, sprite), pipe_name(pipe));
>  		}
>  	} else if (INTEL_INFO(dev)->gen >= 7) {
> -		reg = SPRCTL(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(SPRCTL(pipe));
>  		I915_STATE_WARN(val & SPRITE_ENABLE,
>  		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  		     plane_name(pipe), pipe_name(pipe));
>  	} else if (INTEL_INFO(dev)->gen >= 5) {
> -		reg = DVSCNTR(pipe);
> -		val = I915_READ(reg);
> +		u32 val = I915_READ(DVSCNTR(pipe));
>  		I915_STATE_WARN(val & DVS_ENABLE,
>  		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
>  		     plane_name(pipe), pipe_name(pipe));
> @@ -1441,12 +1416,10 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
>  static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
>  					   enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  	bool enabled;
>  
> -	reg = PCH_TRANSCONF(pipe);
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_TRANSCONF(pipe));
>  	enabled = !!(val & TRANS_ENABLE);
>  	I915_STATE_WARN(enabled,
>  	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
> @@ -1553,21 +1526,18 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
>  static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  				      enum pipe pipe)
>  {
> -	int reg;
>  	u32 val;
>  
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
>  
> -	reg = PCH_ADPA;
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_ADPA);
>  	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
>  	     "PCH VGA enabled on transcoder %c, should be disabled\n",
>  	     pipe_name(pipe));
>  
> -	reg = PCH_LVDS;
> -	val = I915_READ(reg);
> +	val = I915_READ(PCH_LVDS);
>  	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
>  	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
>  	     pipe_name(pipe));
> @@ -14864,13 +14834,12 @@ intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 reg, val;
> +	u32 val;
>  
>  	if (INTEL_INFO(dev)->num_pipes == 1)
>  		return true;
>  
> -	reg = DSPCNTR(!crtc->plane);
> -	val = I915_READ(reg);
> +	val = I915_READ(DSPCNTR(!crtc->plane));
>  
>  	if ((val & DISPLAY_PLANE_ENABLE) &&
>  	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 7e64555..0b9f973 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -574,8 +574,6 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  						 edp_notifier);
>  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 pp_div;
> -	u32 pp_ctrl_reg, pp_div_reg;
>  
>  	if (!is_edp(intel_dp) || code != SYS_RESTART)
>  		return 0;
> @@ -584,6 +582,8 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code,
>  
>  	if (IS_VALLEYVIEW(dev)) {
>  		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
> +		u32 pp_ctrl_reg, pp_div_reg;
> +		u32 pp_div;
>  
>  		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
>  		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
> @@ -5526,7 +5526,6 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  	struct intel_dp *intel_dp = dev_priv->drrs.dp;
>  	struct intel_crtc_state *config = NULL;
>  	struct intel_crtc *intel_crtc = NULL;
> -	u32 reg, val;
>  	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
>  
>  	if (refresh_rate <= 0) {
> @@ -5588,9 +5587,10 @@ static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
>  			DRM_ERROR("Unsupported refreshrate type\n");
>  		}
>  	} else if (INTEL_INFO(dev)->gen > 6) {
> -		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> -		val = I915_READ(reg);
> +		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
> +		u32 val;
>  
> +		val = I915_READ(reg);
>  		if (index > DRRS_HIGH_RR) {
>  			if (IS_VALLEYVIEW(dev))
>  				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4b61a42..d181dab 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -674,9 +674,8 @@  static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int reg = PIPE_FRMCOUNT_G4X(pipe);
 
-	return I915_READ(reg);
+	return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 }
 
 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6f538d5..dc24e22 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1110,12 +1110,10 @@  static const char *state_string(bool enabled)
 void assert_pll(struct drm_i915_private *dev_priv,
 		enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DPLL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(DPLL(pipe));
 	cur_state = !!(val & DPLL_VCO_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "PLL state assertion failure (expected %s, current %s)\n",
@@ -1172,20 +1170,16 @@  void assert_shared_dpll(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
 
 	if (HAS_DDI(dev_priv->dev)) {
 		/* DDI does not have a specific FDI_TX register */
-		reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
 		cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
 	} else {
-		reg = FDI_TX_CTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(FDI_TX_CTL(pipe));
 		cur_state = !!(val & FDI_TX_ENABLE);
 	}
 	I915_STATE_WARN(cur_state != state,
@@ -1198,12 +1192,10 @@  static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
@@ -1215,7 +1207,6 @@  static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	/* ILK FDI PLL is always enabled */
@@ -1226,20 +1217,17 @@  static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (HAS_DDI(dev_priv->dev))
 		return;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_TX_CTL(pipe));
 	I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(FDI_RX_CTL(pipe));
 	cur_state = !!(val & FDI_RX_PLL_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "FDI RX PLL assertion failure (expected %s, current %s)\n",
@@ -1309,8 +1297,6 @@  static void assert_cursor(struct drm_i915_private *dev_priv,
 void assert_pipe(struct drm_i915_private *dev_priv,
 		 enum pipe pipe, bool state)
 {
-	int reg;
-	u32 val;
 	bool cur_state;
 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 								      pipe);
@@ -1324,8 +1310,7 @@  void assert_pipe(struct drm_i915_private *dev_priv,
 				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
 		cur_state = false;
 	} else {
-		reg = PIPECONF(cpu_transcoder);
-		val = I915_READ(reg);
+		u32 val = I915_READ(PIPECONF(cpu_transcoder));
 		cur_state = !!(val & PIPECONF_ENABLE);
 	}
 
@@ -1337,12 +1322,10 @@  void assert_pipe(struct drm_i915_private *dev_priv,
 static void assert_plane(struct drm_i915_private *dev_priv,
 			 enum plane plane, bool state)
 {
-	int reg;
 	u32 val;
 	bool cur_state;
 
-	reg = DSPCNTR(plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(plane));
 	cur_state = !!(val & DISPLAY_PLANE_ENABLE);
 	I915_STATE_WARN(cur_state != state,
 	     "plane %c assertion failure (expected %s, current %s)\n",
@@ -1356,14 +1339,11 @@  static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, i;
-	u32 val;
-	int cur_pipe;
+	int i;
 
 	/* Primary planes are fixed to pipes on gen4+ */
 	if (INTEL_INFO(dev)->gen >= 4) {
-		reg = DSPCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DSPCNTR(pipe));
 		I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
 		     "plane %c assertion failure, should be disabled but not\n",
 		     plane_name(pipe));
@@ -1372,9 +1352,8 @@  static void assert_planes_disabled(struct drm_i915_private *dev_priv,
 
 	/* Need to check both planes against the pipe */
 	for_each_pipe(dev_priv, i) {
-		reg = DSPCNTR(i);
-		val = I915_READ(reg);
-		cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
+		u32 val = I915_READ(DSPCNTR(i));
+		enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
 			DISPPLANE_SEL_PIPE_SHIFT;
 		I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
 		     "plane %c assertion failure, should be off on pipe %c but is still active\n",
@@ -1386,33 +1365,29 @@  static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
 				    enum pipe pipe)
 {
 	struct drm_device *dev = dev_priv->dev;
-	int reg, sprite;
-	u32 val;
+	int sprite;
 
 	if (INTEL_INFO(dev)->gen >= 9) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			val = I915_READ(PLANE_CTL(pipe, sprite));
+			u32 val = I915_READ(PLANE_CTL(pipe, sprite));
 			I915_STATE_WARN(val & PLANE_CTL_ENABLE,
 			     "plane %d assertion failure, should be off on pipe %c but is still active\n",
 			     sprite, pipe_name(pipe));
 		}
 	} else if (IS_VALLEYVIEW(dev)) {
 		for_each_sprite(dev_priv, pipe, sprite) {
-			reg = SPCNTR(pipe, sprite);
-			val = I915_READ(reg);
+			u32 val = I915_READ(SPCNTR(pipe, sprite));
 			I915_STATE_WARN(val & SP_ENABLE,
 			     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 			     sprite_name(pipe, sprite), pipe_name(pipe));
 		}
 	} else if (INTEL_INFO(dev)->gen >= 7) {
-		reg = SPRCTL(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(SPRCTL(pipe));
 		I915_STATE_WARN(val & SPRITE_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
 	} else if (INTEL_INFO(dev)->gen >= 5) {
-		reg = DVSCNTR(pipe);
-		val = I915_READ(reg);
+		u32 val = I915_READ(DVSCNTR(pipe));
 		I915_STATE_WARN(val & DVS_ENABLE,
 		     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
 		     plane_name(pipe), pipe_name(pipe));
@@ -1441,12 +1416,10 @@  static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
 					   enum pipe pipe)
 {
-	int reg;
 	u32 val;
 	bool enabled;
 
-	reg = PCH_TRANSCONF(pipe);
-	val = I915_READ(reg);
+	val = I915_READ(PCH_TRANSCONF(pipe));
 	enabled = !!(val & TRANS_ENABLE);
 	I915_STATE_WARN(enabled,
 	     "transcoder assertion failed, should be off on pipe %c but is still active\n",
@@ -1553,21 +1526,18 @@  static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
-	int reg;
 	u32 val;
 
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
-	reg = PCH_ADPA;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_ADPA);
 	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
 	     "PCH VGA enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
 
-	reg = PCH_LVDS;
-	val = I915_READ(reg);
+	val = I915_READ(PCH_LVDS);
 	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
 	     "PCH LVDS enabled on transcoder %c, should be disabled\n",
 	     pipe_name(pipe));
@@ -14864,13 +14834,12 @@  intel_check_plane_mapping(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 reg, val;
+	u32 val;
 
 	if (INTEL_INFO(dev)->num_pipes == 1)
 		return true;
 
-	reg = DSPCNTR(!crtc->plane);
-	val = I915_READ(reg);
+	val = I915_READ(DSPCNTR(!crtc->plane));
 
 	if ((val & DISPLAY_PLANE_ENABLE) &&
 	    (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7e64555..0b9f973 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -574,8 +574,6 @@  static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 						 edp_notifier);
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 pp_div;
-	u32 pp_ctrl_reg, pp_div_reg;
 
 	if (!is_edp(intel_dp) || code != SYS_RESTART)
 		return 0;
@@ -584,6 +582,8 @@  static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 
 	if (IS_VALLEYVIEW(dev)) {
 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+		u32 pp_ctrl_reg, pp_div_reg;
+		u32 pp_div;
 
 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
@@ -5526,7 +5526,6 @@  static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 	struct intel_dp *intel_dp = dev_priv->drrs.dp;
 	struct intel_crtc_state *config = NULL;
 	struct intel_crtc *intel_crtc = NULL;
-	u32 reg, val;
 	enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
 
 	if (refresh_rate <= 0) {
@@ -5588,9 +5587,10 @@  static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
 			DRM_ERROR("Unsupported refreshrate type\n");
 		}
 	} else if (INTEL_INFO(dev)->gen > 6) {
-		reg = PIPECONF(intel_crtc->config->cpu_transcoder);
-		val = I915_READ(reg);
+		u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
+		u32 val;
 
+		val = I915_READ(reg);
 		if (index > DRRS_HIGH_RR) {
 			if (IS_VALLEYVIEW(dev))
 				val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;