diff mbox

[v8,08/20] KVM: ARM64: Add access handler for event typer register

Message ID 1450771695-11948-9-git-send-email-zhaoshenglong@huawei.com (mailing list archive)
State New, archived
Headers show

Commit Message

Shannon Zhao Dec. 22, 2015, 8:08 a.m. UTC 
From: Shannon Zhao <shannon.zhao@linaro.org>

These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.

The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.

When writing to these registers, create a perf_event for the selected
event type.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 154 insertions(+), 2 deletions(-)

Comments

Marc Zyngier Jan. 7, 2016, 11:03 a.m. UTC | #1 
On 22/12/15 08:08, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
> 
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
> 
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoid taking care
> of big endian.
> 
> When writing to these registers, create a perf_event for the selected
> event type.
> 
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 154 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2552db1..ed2939b 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>  	return true;
>  }
>  
> +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
> +{
> +	u64 pmcr, val;
> +
> +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
> +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
> +		return false;
> +
> +	return true;
> +}
> +
> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> +			       const struct sys_reg_desc *r)
> +{
> +	u64 idx, reg;
> +
> +	if (r->CRn == 9) {
> +		/* PMXEVTYPER_EL0 */
> +		reg = 0;

Is there any particular reason why you're not setting reg to PMSELR_EL0,
since this is what you're using?

> +	} else {
> +		if (!p->is_aarch32) {
> +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
> +			reg = r->reg;
> +		} else {
> +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
> +				reg = PMCCFILTR_EL0;
> +			} else {
> +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> +				reg += PMEVTYPER0_EL0;
> +			}
> +		}
> +	}
> +
> +	switch (reg) {
> +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
> +		idx = reg - PMEVTYPER0_EL0;
> +		if (!pmu_counter_idx_valid(vcpu, idx))
> +			return true;
> +		break;
> +	case PMCCFILTR_EL0:
> +		idx = ARMV8_CYCLE_IDX;
> +		break;
> +	default:

This would allow this case to be more precise, and we could have the
default case as a bug handler.

> +		/* PMXEVTYPER_EL0 */
> +		idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
> +		if (!pmu_counter_idx_valid(vcpu, idx))
> +			return true;
> +
> +		reg = (idx == ARMV8_CYCLE_IDX) ? PMCCFILTR_EL0
> +						 : PMEVTYPER0_EL0 + idx;
> +		break;
> +	}
> +
> +	if (p->is_write) {
> +		kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
> +		vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
> +	} else {
> +		p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
> +	}
> +
> +	return true;
> +}
> +
>  /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
>  #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
>  	/* DBGBVRn_EL1 */						\
> @@ -520,6 +584,13 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>  	{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),	\
>  	  trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
>  
> +/* Macro to expand the PMEVTYPERn_EL0 register */
> +#define PMU_PMEVTYPER_EL0(n)						\
> +	/* PMEVTYPERn_EL0 */						\
> +	{ Op0(0b11), Op1(0b011), CRn(0b1110),				\
> +	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
> +	  access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
> +
>  /*
>   * Architected system registers.
>   * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
> @@ -716,7 +787,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	  trap_raz_wi },
>  	/* PMXEVTYPER_EL0 */
>  	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
> -	  trap_raz_wi },
> +	  access_pmu_evtyper },
>  	/* PMXEVCNTR_EL0 */
>  	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
>  	  trap_raz_wi },
> @@ -734,6 +805,45 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
>  	  NULL, reset_unknown, TPIDRRO_EL0 },
>  
> +	/* PMEVTYPERn_EL0 */
> +	PMU_PMEVTYPER_EL0(0),
> +	PMU_PMEVTYPER_EL0(1),
> +	PMU_PMEVTYPER_EL0(2),
> +	PMU_PMEVTYPER_EL0(3),
> +	PMU_PMEVTYPER_EL0(4),
> +	PMU_PMEVTYPER_EL0(5),
> +	PMU_PMEVTYPER_EL0(6),
> +	PMU_PMEVTYPER_EL0(7),
> +	PMU_PMEVTYPER_EL0(8),
> +	PMU_PMEVTYPER_EL0(9),
> +	PMU_PMEVTYPER_EL0(10),
> +	PMU_PMEVTYPER_EL0(11),
> +	PMU_PMEVTYPER_EL0(12),
> +	PMU_PMEVTYPER_EL0(13),
> +	PMU_PMEVTYPER_EL0(14),
> +	PMU_PMEVTYPER_EL0(15),
> +	PMU_PMEVTYPER_EL0(16),
> +	PMU_PMEVTYPER_EL0(17),
> +	PMU_PMEVTYPER_EL0(18),
> +	PMU_PMEVTYPER_EL0(19),
> +	PMU_PMEVTYPER_EL0(20),
> +	PMU_PMEVTYPER_EL0(21),
> +	PMU_PMEVTYPER_EL0(22),
> +	PMU_PMEVTYPER_EL0(23),
> +	PMU_PMEVTYPER_EL0(24),
> +	PMU_PMEVTYPER_EL0(25),
> +	PMU_PMEVTYPER_EL0(26),
> +	PMU_PMEVTYPER_EL0(27),
> +	PMU_PMEVTYPER_EL0(28),
> +	PMU_PMEVTYPER_EL0(29),
> +	PMU_PMEVTYPER_EL0(30),
> +	/* PMCCFILTR_EL0
> +	 * This register resets as unknown in 64bit mode while it resets as zero
> +	 * in 32bit mode. Here we choose to reset it as zero for consistency.
> +	 */
> +	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
> +	  access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
> +
>  	/* DACR32_EL2 */
>  	{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
>  	  NULL, reset_unknown, DACR32_EL2 },
> @@ -923,6 +1033,13 @@ static const struct sys_reg_desc cp14_64_regs[] = {
>  	{ Op1( 0), CRm( 2), .access = trap_raz_wi },
>  };
>  
> +/* Macro to expand the PMEVTYPERn register */
> +#define PMU_PMEVTYPER(n)						\
> +	/* PMEVTYPERn */						\
> +	{ Op1(0), CRn(0b1110),						\
> +	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
> +	  access_pmu_evtyper }
> +
>  /*
>   * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
>   * depending on the way they are accessed (as a 32bit or a 64bit
> @@ -959,7 +1076,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>  	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
>  	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
>  	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
> -	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
> +	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
>  	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
>  	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
>  	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
> @@ -974,6 +1091,41 @@ static const struct sys_reg_desc cp15_regs[] = {
>  	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
>  
>  	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
> +
> +	/* PMEVTYPERn */
> +	PMU_PMEVTYPER(0),
> +	PMU_PMEVTYPER(1),
> +	PMU_PMEVTYPER(2),
> +	PMU_PMEVTYPER(3),
> +	PMU_PMEVTYPER(4),
> +	PMU_PMEVTYPER(5),
> +	PMU_PMEVTYPER(6),
> +	PMU_PMEVTYPER(7),
> +	PMU_PMEVTYPER(8),
> +	PMU_PMEVTYPER(9),
> +	PMU_PMEVTYPER(10),
> +	PMU_PMEVTYPER(11),
> +	PMU_PMEVTYPER(12),
> +	PMU_PMEVTYPER(13),
> +	PMU_PMEVTYPER(14),
> +	PMU_PMEVTYPER(15),
> +	PMU_PMEVTYPER(16),
> +	PMU_PMEVTYPER(17),
> +	PMU_PMEVTYPER(18),
> +	PMU_PMEVTYPER(19),
> +	PMU_PMEVTYPER(20),
> +	PMU_PMEVTYPER(21),
> +	PMU_PMEVTYPER(22),
> +	PMU_PMEVTYPER(23),
> +	PMU_PMEVTYPER(24),
> +	PMU_PMEVTYPER(25),
> +	PMU_PMEVTYPER(26),
> +	PMU_PMEVTYPER(27),
> +	PMU_PMEVTYPER(28),
> +	PMU_PMEVTYPER(29),
> +	PMU_PMEVTYPER(30),
> +	/* PMCCFILTR */
> +	{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
>  };
>  
>  static const struct sys_reg_desc cp15_64_regs[] = {
> 

Thanks,

	M.
Shannon Zhao Jan. 7, 2016, 11:11 a.m. UTC | #2 
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> > 
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> > 
>> > The access handler translates all aarch32 register offsets to aarch64
>> > ones and uses vcpu_sys_reg() to access their values to avoid taking care
>> > of big endian.
>> > 
>> > When writing to these registers, create a perf_event for the selected
>> > event type.
>> > 
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> >  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>> >  1 file changed, 154 insertions(+), 2 deletions(-)
>> > 
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index 2552db1..ed2939b 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> >  	return true;
>> >  }
>> >  
>> > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
>> > +{
>> > +	u64 pmcr, val;
>> > +
>> > +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
>> > +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
>> > +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
>> > +		return false;
>> > +
>> > +	return true;
>> > +}
>> > +
>> > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> > +			       const struct sys_reg_desc *r)
>> > +{
>> > +	u64 idx, reg;
>> > +
>> > +	if (r->CRn == 9) {
>> > +		/* PMXEVTYPER_EL0 */
>> > +		reg = 0;
> Is there any particular reason why you're not setting reg to PMSELR_EL0,
> since this is what you're using?
> 
>> > +	} else {
>> > +		if (!p->is_aarch32) {
>> > +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
>> > +			reg = r->reg;
>> > +		} else {
>> > +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
>> > +				reg = PMCCFILTR_EL0;
>> > +			} else {
>> > +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
>> > +				reg += PMEVTYPER0_EL0;
>> > +			}
>> > +		}
>> > +	}
>> > +
>> > +	switch (reg) {
>> > +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
>> > +		idx = reg - PMEVTYPER0_EL0;
>> > +		if (!pmu_counter_idx_valid(vcpu, idx))
>> > +			return true;
>> > +		break;
>> > +	case PMCCFILTR_EL0:
>> > +		idx = ARMV8_CYCLE_IDX;
>> > +		break;
>> > +	default:
> This would allow this case to be more precise, and we could have the
> default case as a bug handler.
> 
Ah, you're right. Will fix this.

Thanks,
Shannon Zhao Jan. 7, 2016, 12:09 p.m. UTC | #3 
On 2015/12/22 16:08, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
> 
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
> 
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoid taking care
> of big endian.
> 
> When writing to these registers, create a perf_event for the selected
> event type.
> 
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 154 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2552db1..ed2939b 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>  	return true;
>  }
>  
> +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
> +{
> +	u64 pmcr, val;
> +
> +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
> +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
> +		return false;
> +
> +	return true;
> +}
> +
> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> +			       const struct sys_reg_desc *r)
> +{
> +	u64 idx, reg;
> +
> +	if (r->CRn == 9) {
> +		/* PMXEVTYPER_EL0 */
> +		reg = 0;
> +	} else {
> +		if (!p->is_aarch32) {
> +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
> +			reg = r->reg;
> +		} else {
> +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
> +				reg = PMCCFILTR_EL0;
> +			} else {
> +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> +				reg += PMEVTYPER0_EL0;
> +			}
> +		}
> +	}
> +
> +	switch (reg) {
> +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
> +		idx = reg - PMEVTYPER0_EL0;
> +		if (!pmu_counter_idx_valid(vcpu, idx))
> +			return true;
Hi Marc,

Here should we return false to inject an UND since there is no
PMEVTYPER(idx)_EL0? The ARMv8 spec says it should.

Thanks,
Shannon Zhao Jan. 7, 2016, 12:36 p.m. UTC | #4 
On 2016/1/7 19:03, Marc Zyngier wrote:
> On 22/12/15 08:08, Shannon Zhao wrote:
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> > 
>> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> > which is mapped to PMEVTYPERn or PMCCFILTR.
>> > 
>> > The access handler translates all aarch32 register offsets to aarch64
>> > ones and uses vcpu_sys_reg() to access their values to avoid taking care
>> > of big endian.
>> > 
>> > When writing to these registers, create a perf_event for the selected
>> > event type.
>> > 
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> >  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>> >  1 file changed, 154 insertions(+), 2 deletions(-)
>> > 
>> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> > index 2552db1..ed2939b 100644
>> > --- a/arch/arm64/kvm/sys_regs.c
>> > +++ b/arch/arm64/kvm/sys_regs.c
>> > @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> >  	return true;
>> >  }
>> >  
>> > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
>> > +{
>> > +	u64 pmcr, val;
>> > +
>> > +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
>> > +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
>> > +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
>> > +		return false;
>> > +
>> > +	return true;
>> > +}
>> > +
>> > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> > +			       const struct sys_reg_desc *r)
>> > +{
>> > +	u64 idx, reg;
>> > +
>> > +	if (r->CRn == 9) {
>> > +		/* PMXEVTYPER_EL0 */
>> > +		reg = 0;
> Is there any particular reason why you're not setting reg to PMSELR_EL0,
> since this is what you're using?
> 
>> > +	} else {
>> > +		if (!p->is_aarch32) {
>> > +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
>> > +			reg = r->reg;
>> > +		} else {
>> > +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
>> > +				reg = PMCCFILTR_EL0;
>> > +			} else {
>> > +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
>> > +				reg += PMEVTYPER0_EL0;
>> > +			}
>> > +		}
>> > +	}
>> > +
>> > +	switch (reg) {
>> > +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
>> > +		idx = reg - PMEVTYPER0_EL0;
>> > +		if (!pmu_counter_idx_valid(vcpu, idx))
>> > +			return true;
>> > +		break;
>> > +	case PMCCFILTR_EL0:
>> > +		idx = ARMV8_CYCLE_IDX;
>> > +		break;
>> > +	default:
> This would allow this case to be more precise, and we could have the
> default case as a bug handler.
> 

It turns out that I refactor this function like below:

+static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct
sys_reg_params *p,
+                              const struct sys_reg_desc *r)
+{
+       u64 idx, reg = 0;
+
+       if (r->CRn == 9) {
+               /* PMXEVTYPER_EL0 */
+               idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+               reg = PMEVTYPER0_EL0 + idx;
+       } else {
+               if (r->CRm == 15 && r->Op2 == 7) {
+                       idx = ARMV8_CYCLE_IDX;
+                       reg = PMCCFILTR_EL0;
+               } else {
+                       /* PMEVTYPERn_EL0 */
+                       idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+                       reg = PMEVTYPER0_EL0 + idx;
+               }
+       }
+
+       BUG_ON(reg == 0);
+
+       if (!pmu_counter_idx_valid(vcpu, idx))
+               return false;
+
+       if (p->is_write) {
+               kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+               vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
+       } else {
+               p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
+       }
+
+       return true;
+}

How about this?

Thanks,
Marc Zyngier Jan. 7, 2016, 1:01 p.m. UTC | #5 
On 07/01/16 12:09, Shannon Zhao wrote:
> 
> 
> On 2015/12/22 16:08, Shannon Zhao wrote:
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
>> which is mapped to PMEVTYPERn or PMCCFILTR.
>>
>> The access handler translates all aarch32 register offsets to aarch64
>> ones and uses vcpu_sys_reg() to access their values to avoid taking care
>> of big endian.
>>
>> When writing to these registers, create a perf_event for the selected
>> event type.
>>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>>  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 154 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 2552db1..ed2939b 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>>  	return true;
>>  }
>>  
>> +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
>> +{
>> +	u64 pmcr, val;
>> +
>> +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
>> +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
>> +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
>> +		return false;
>> +
>> +	return true;
>> +}
>> +
>> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>> +			       const struct sys_reg_desc *r)
>> +{
>> +	u64 idx, reg;
>> +
>> +	if (r->CRn == 9) {
>> +		/* PMXEVTYPER_EL0 */
>> +		reg = 0;
>> +	} else {
>> +		if (!p->is_aarch32) {
>> +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
>> +			reg = r->reg;
>> +		} else {
>> +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
>> +				reg = PMCCFILTR_EL0;
>> +			} else {
>> +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
>> +				reg += PMEVTYPER0_EL0;
>> +			}
>> +		}
>> +	}
>> +
>> +	switch (reg) {
>> +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
>> +		idx = reg - PMEVTYPER0_EL0;
>> +		if (!pmu_counter_idx_valid(vcpu, idx))
>> +			return true;
> Hi Marc,
> 
> Here should we return false to inject an UND since there is no
> PMEVTYPER(idx)_EL0? The ARMv8 spec says it should.

The spec says that the following behaviours are valid:
- Accesses to the register are UNDEFINED .
- Accesses to the register behave as RAZ/WI.
- Accesses to the register execute as a NOP .

Same for the counters. So you can either return true (act as a NOP), or
return false (UNDEF), and even zero r->regval on read and return true
(RAZ/WI).

This is entirely up to you. My personal preference is indeed to UNDEF,
but your current implementation is valid.

Thanks,

	M.
Marc Zyngier Jan. 7, 2016, 1:15 p.m. UTC | #6 
On Thu, 7 Jan 2016 20:36:45 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:

> 
> 
> On 2016/1/7 19:03, Marc Zyngier wrote:
> > On 22/12/15 08:08, Shannon Zhao wrote:
> >> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >> > 
> >> > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> >> > which is mapped to PMEVTYPERn or PMCCFILTR.
> >> > 
> >> > The access handler translates all aarch32 register offsets to aarch64
> >> > ones and uses vcpu_sys_reg() to access their values to avoid taking care
> >> > of big endian.
> >> > 
> >> > When writing to these registers, create a perf_event for the selected
> >> > event type.
> >> > 
> >> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> > ---
> >> >  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
> >> >  1 file changed, 154 insertions(+), 2 deletions(-)
> >> > 
> >> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> >> > index 2552db1..ed2939b 100644
> >> > --- a/arch/arm64/kvm/sys_regs.c
> >> > +++ b/arch/arm64/kvm/sys_regs.c
> >> > @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> >> >  	return true;
> >> >  }
> >> >  
> >> > +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
> >> > +{
> >> > +	u64 pmcr, val;
> >> > +
> >> > +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
> >> > +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> >> > +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
> >> > +		return false;
> >> > +
> >> > +	return true;
> >> > +}
> >> > +
> >> > +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> >> > +			       const struct sys_reg_desc *r)
> >> > +{
> >> > +	u64 idx, reg;
> >> > +
> >> > +	if (r->CRn == 9) {
> >> > +		/* PMXEVTYPER_EL0 */
> >> > +		reg = 0;
> > Is there any particular reason why you're not setting reg to PMSELR_EL0,
> > since this is what you're using?
> > 
> >> > +	} else {
> >> > +		if (!p->is_aarch32) {
> >> > +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
> >> > +			reg = r->reg;
> >> > +		} else {
> >> > +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
> >> > +				reg = PMCCFILTR_EL0;
> >> > +			} else {
> >> > +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> >> > +				reg += PMEVTYPER0_EL0;
> >> > +			}
> >> > +		}
> >> > +	}
> >> > +
> >> > +	switch (reg) {
> >> > +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
> >> > +		idx = reg - PMEVTYPER0_EL0;
> >> > +		if (!pmu_counter_idx_valid(vcpu, idx))
> >> > +			return true;
> >> > +		break;
> >> > +	case PMCCFILTR_EL0:
> >> > +		idx = ARMV8_CYCLE_IDX;
> >> > +		break;
> >> > +	default:
> > This would allow this case to be more precise, and we could have the
> > default case as a bug handler.
> > 
> 
> It turns out that I refactor this function like below:
> 
> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct
> sys_reg_params *p,
> +                              const struct sys_reg_desc *r)
> +{
> +       u64 idx, reg = 0;
> +
> +       if (r->CRn == 9) {
> +               /* PMXEVTYPER_EL0 */
> +               idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
> +               reg = PMEVTYPER0_EL0 + idx;
> +       } else {
> +               if (r->CRm == 15 && r->Op2 == 7) {
> +                       idx = ARMV8_CYCLE_IDX;
> +                       reg = PMCCFILTR_EL0;
> +               } else {
> +                       /* PMEVTYPERn_EL0 */
> +                       idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> +                       reg = PMEVTYPER0_EL0 + idx;
> +               }
> +       }
> +
> +       BUG_ON(reg == 0);
> +
> +       if (!pmu_counter_idx_valid(vcpu, idx))
> +               return false;
> +
> +       if (p->is_write) {
> +               kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
> +               vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
> +       } else {
> +               p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
> +       }
> +
> +       return true;
> +}
> 
> How about this?

Yup, looks good to me.

	M.
Andrew Jones Jan. 7, 2016, 7:17 p.m. UTC | #7 
patch summary nit: s/typer/type/

Thanks,
drew

On Tue, Dec 22, 2015 at 04:08:03PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
> 
> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
> which is mapped to PMEVTYPERn or PMCCFILTR.
> 
> The access handler translates all aarch32 register offsets to aarch64
> ones and uses vcpu_sys_reg() to access their values to avoid taking care
> of big endian.
> 
> When writing to these registers, create a perf_event for the selected
> event type.
> 
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  arch/arm64/kvm/sys_regs.c | 156 +++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 154 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 2552db1..ed2939b 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -505,6 +505,70 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>  	return true;
>  }
>  
> +static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
> +{
> +	u64 pmcr, val;
> +
> +	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
> +	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
> +	if (idx >= val && idx != ARMV8_CYCLE_IDX)
> +		return false;
> +
> +	return true;
> +}
> +
> +static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> +			       const struct sys_reg_desc *r)
> +{
> +	u64 idx, reg;
> +
> +	if (r->CRn == 9) {
> +		/* PMXEVTYPER_EL0 */
> +		reg = 0;
> +	} else {
> +		if (!p->is_aarch32) {
> +			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
> +			reg = r->reg;
> +		} else {
> +			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
> +				reg = PMCCFILTR_EL0;
> +			} else {
> +				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
> +				reg += PMEVTYPER0_EL0;
> +			}
> +		}
> +	}
> +
> +	switch (reg) {
> +	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
> +		idx = reg - PMEVTYPER0_EL0;
> +		if (!pmu_counter_idx_valid(vcpu, idx))
> +			return true;
> +		break;
> +	case PMCCFILTR_EL0:
> +		idx = ARMV8_CYCLE_IDX;
> +		break;
> +	default:
> +		/* PMXEVTYPER_EL0 */
> +		idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
> +		if (!pmu_counter_idx_valid(vcpu, idx))
> +			return true;
> +
> +		reg = (idx == ARMV8_CYCLE_IDX) ? PMCCFILTR_EL0
> +						 : PMEVTYPER0_EL0 + idx;
> +		break;
> +	}
> +
> +	if (p->is_write) {
> +		kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
> +		vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
> +	} else {
> +		p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
> +	}
> +
> +	return true;
> +}
> +
>  /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
>  #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
>  	/* DBGBVRn_EL1 */						\
> @@ -520,6 +584,13 @@ static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
>  	{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),	\
>  	  trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
>  
> +/* Macro to expand the PMEVTYPERn_EL0 register */
> +#define PMU_PMEVTYPER_EL0(n)						\
> +	/* PMEVTYPERn_EL0 */						\
> +	{ Op0(0b11), Op1(0b011), CRn(0b1110),				\
> +	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
> +	  access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
> +
>  /*
>   * Architected system registers.
>   * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
> @@ -716,7 +787,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	  trap_raz_wi },
>  	/* PMXEVTYPER_EL0 */
>  	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
> -	  trap_raz_wi },
> +	  access_pmu_evtyper },
>  	/* PMXEVCNTR_EL0 */
>  	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
>  	  trap_raz_wi },
> @@ -734,6 +805,45 @@ static const struct sys_reg_desc sys_reg_descs[] = {
>  	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
>  	  NULL, reset_unknown, TPIDRRO_EL0 },
>  
> +	/* PMEVTYPERn_EL0 */
> +	PMU_PMEVTYPER_EL0(0),
> +	PMU_PMEVTYPER_EL0(1),
> +	PMU_PMEVTYPER_EL0(2),
> +	PMU_PMEVTYPER_EL0(3),
> +	PMU_PMEVTYPER_EL0(4),
> +	PMU_PMEVTYPER_EL0(5),
> +	PMU_PMEVTYPER_EL0(6),
> +	PMU_PMEVTYPER_EL0(7),
> +	PMU_PMEVTYPER_EL0(8),
> +	PMU_PMEVTYPER_EL0(9),
> +	PMU_PMEVTYPER_EL0(10),
> +	PMU_PMEVTYPER_EL0(11),
> +	PMU_PMEVTYPER_EL0(12),
> +	PMU_PMEVTYPER_EL0(13),
> +	PMU_PMEVTYPER_EL0(14),
> +	PMU_PMEVTYPER_EL0(15),
> +	PMU_PMEVTYPER_EL0(16),
> +	PMU_PMEVTYPER_EL0(17),
> +	PMU_PMEVTYPER_EL0(18),
> +	PMU_PMEVTYPER_EL0(19),
> +	PMU_PMEVTYPER_EL0(20),
> +	PMU_PMEVTYPER_EL0(21),
> +	PMU_PMEVTYPER_EL0(22),
> +	PMU_PMEVTYPER_EL0(23),
> +	PMU_PMEVTYPER_EL0(24),
> +	PMU_PMEVTYPER_EL0(25),
> +	PMU_PMEVTYPER_EL0(26),
> +	PMU_PMEVTYPER_EL0(27),
> +	PMU_PMEVTYPER_EL0(28),
> +	PMU_PMEVTYPER_EL0(29),
> +	PMU_PMEVTYPER_EL0(30),
> +	/* PMCCFILTR_EL0
> +	 * This register resets as unknown in 64bit mode while it resets as zero
> +	 * in 32bit mode. Here we choose to reset it as zero for consistency.
> +	 */
> +	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
> +	  access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
> +
>  	/* DACR32_EL2 */
>  	{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
>  	  NULL, reset_unknown, DACR32_EL2 },
> @@ -923,6 +1033,13 @@ static const struct sys_reg_desc cp14_64_regs[] = {
>  	{ Op1( 0), CRm( 2), .access = trap_raz_wi },
>  };
>  
> +/* Macro to expand the PMEVTYPERn register */
> +#define PMU_PMEVTYPER(n)						\
> +	/* PMEVTYPERn */						\
> +	{ Op1(0), CRn(0b1110),						\
> +	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
> +	  access_pmu_evtyper }
> +
>  /*
>   * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
>   * depending on the way they are accessed (as a 32bit or a 64bit
> @@ -959,7 +1076,7 @@ static const struct sys_reg_desc cp15_regs[] = {
>  	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
>  	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
>  	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
> -	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
> +	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
>  	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
>  	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
>  	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
> @@ -974,6 +1091,41 @@ static const struct sys_reg_desc cp15_regs[] = {
>  	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
>  
>  	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
> +
> +	/* PMEVTYPERn */
> +	PMU_PMEVTYPER(0),
> +	PMU_PMEVTYPER(1),
> +	PMU_PMEVTYPER(2),
> +	PMU_PMEVTYPER(3),
> +	PMU_PMEVTYPER(4),
> +	PMU_PMEVTYPER(5),
> +	PMU_PMEVTYPER(6),
> +	PMU_PMEVTYPER(7),
> +	PMU_PMEVTYPER(8),
> +	PMU_PMEVTYPER(9),
> +	PMU_PMEVTYPER(10),
> +	PMU_PMEVTYPER(11),
> +	PMU_PMEVTYPER(12),
> +	PMU_PMEVTYPER(13),
> +	PMU_PMEVTYPER(14),
> +	PMU_PMEVTYPER(15),
> +	PMU_PMEVTYPER(16),
> +	PMU_PMEVTYPER(17),
> +	PMU_PMEVTYPER(18),
> +	PMU_PMEVTYPER(19),
> +	PMU_PMEVTYPER(20),
> +	PMU_PMEVTYPER(21),
> +	PMU_PMEVTYPER(22),
> +	PMU_PMEVTYPER(23),
> +	PMU_PMEVTYPER(24),
> +	PMU_PMEVTYPER(25),
> +	PMU_PMEVTYPER(26),
> +	PMU_PMEVTYPER(27),
> +	PMU_PMEVTYPER(28),
> +	PMU_PMEVTYPER(29),
> +	PMU_PMEVTYPER(30),
> +	/* PMCCFILTR */
> +	{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
>  };
>  
>  static const struct sys_reg_desc cp15_64_regs[] = {
> -- 
> 2.0.4
> 
> 
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diff mbox

Patch

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2552db1..ed2939b 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -505,6 +505,70 @@  static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	return true;
 }
 
+static inline bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
+{
+	u64 pmcr, val;
+
+	pmcr = vcpu_sys_reg(vcpu, PMCR_EL0);
+	val = (pmcr >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
+	if (idx >= val && idx != ARMV8_CYCLE_IDX)
+		return false;
+
+	return true;
+}
+
+static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
+			       const struct sys_reg_desc *r)
+{
+	u64 idx, reg;
+
+	if (r->CRn == 9) {
+		/* PMXEVTYPER_EL0 */
+		reg = 0;
+	} else {
+		if (!p->is_aarch32) {
+			/* PMEVTYPERn_EL0 or PMCCFILTR_EL0 */
+			reg = r->reg;
+		} else {
+			if (r->CRn == 14 && r->CRm == 15 && r->Op2 == 7) {
+				reg = PMCCFILTR_EL0;
+			} else {
+				reg = ((r->CRm & 3) << 3) | (r->Op2 & 7);
+				reg += PMEVTYPER0_EL0;
+			}
+		}
+	}
+
+	switch (reg) {
+	case PMEVTYPER0_EL0 ... PMEVTYPER30_EL0:
+		idx = reg - PMEVTYPER0_EL0;
+		if (!pmu_counter_idx_valid(vcpu, idx))
+			return true;
+		break;
+	case PMCCFILTR_EL0:
+		idx = ARMV8_CYCLE_IDX;
+		break;
+	default:
+		/* PMXEVTYPER_EL0 */
+		idx = vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_COUNTER_MASK;
+		if (!pmu_counter_idx_valid(vcpu, idx))
+			return true;
+
+		reg = (idx == ARMV8_CYCLE_IDX) ? PMCCFILTR_EL0
+						 : PMEVTYPER0_EL0 + idx;
+		break;
+	}
+
+	if (p->is_write) {
+		kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
+		vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_EVTYPE_MASK;
+	} else {
+		p->regval = vcpu_sys_reg(vcpu, reg) & ARMV8_EVTYPE_MASK;
+	}
+
+	return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n)					\
 	/* DBGBVRn_EL1 */						\
@@ -520,6 +584,13 @@  static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 	{ Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111),	\
 	  trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n)						\
+	/* PMEVTYPERn_EL0 */						\
+	{ Op0(0b11), Op1(0b011), CRn(0b1110),				\
+	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
+	  access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
 /*
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -716,7 +787,7 @@  static const struct sys_reg_desc sys_reg_descs[] = {
 	  trap_raz_wi },
 	/* PMXEVTYPER_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
-	  trap_raz_wi },
+	  access_pmu_evtyper },
 	/* PMXEVCNTR_EL0 */
 	{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
 	  trap_raz_wi },
@@ -734,6 +805,45 @@  static const struct sys_reg_desc sys_reg_descs[] = {
 	{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
 	  NULL, reset_unknown, TPIDRRO_EL0 },
 
+	/* PMEVTYPERn_EL0 */
+	PMU_PMEVTYPER_EL0(0),
+	PMU_PMEVTYPER_EL0(1),
+	PMU_PMEVTYPER_EL0(2),
+	PMU_PMEVTYPER_EL0(3),
+	PMU_PMEVTYPER_EL0(4),
+	PMU_PMEVTYPER_EL0(5),
+	PMU_PMEVTYPER_EL0(6),
+	PMU_PMEVTYPER_EL0(7),
+	PMU_PMEVTYPER_EL0(8),
+	PMU_PMEVTYPER_EL0(9),
+	PMU_PMEVTYPER_EL0(10),
+	PMU_PMEVTYPER_EL0(11),
+	PMU_PMEVTYPER_EL0(12),
+	PMU_PMEVTYPER_EL0(13),
+	PMU_PMEVTYPER_EL0(14),
+	PMU_PMEVTYPER_EL0(15),
+	PMU_PMEVTYPER_EL0(16),
+	PMU_PMEVTYPER_EL0(17),
+	PMU_PMEVTYPER_EL0(18),
+	PMU_PMEVTYPER_EL0(19),
+	PMU_PMEVTYPER_EL0(20),
+	PMU_PMEVTYPER_EL0(21),
+	PMU_PMEVTYPER_EL0(22),
+	PMU_PMEVTYPER_EL0(23),
+	PMU_PMEVTYPER_EL0(24),
+	PMU_PMEVTYPER_EL0(25),
+	PMU_PMEVTYPER_EL0(26),
+	PMU_PMEVTYPER_EL0(27),
+	PMU_PMEVTYPER_EL0(28),
+	PMU_PMEVTYPER_EL0(29),
+	PMU_PMEVTYPER_EL0(30),
+	/* PMCCFILTR_EL0
+	 * This register resets as unknown in 64bit mode while it resets as zero
+	 * in 32bit mode. Here we choose to reset it as zero for consistency.
+	 */
+	{ Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
+	  access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
+
 	/* DACR32_EL2 */
 	{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
 	  NULL, reset_unknown, DACR32_EL2 },
@@ -923,6 +1033,13 @@  static const struct sys_reg_desc cp14_64_regs[] = {
 	{ Op1( 0), CRm( 2), .access = trap_raz_wi },
 };
 
+/* Macro to expand the PMEVTYPERn register */
+#define PMU_PMEVTYPER(n)						\
+	/* PMEVTYPERn */						\
+	{ Op1(0), CRn(0b1110),						\
+	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
+	  access_pmu_evtyper }
+
 /*
  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
  * depending on the way they are accessed (as a 32bit or a 64bit
@@ -959,7 +1076,7 @@  static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
 	{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
-	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
+	{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
 	{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
 	{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
@@ -974,6 +1091,41 @@  static const struct sys_reg_desc cp15_regs[] = {
 	{ Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
 
 	{ Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
+
+	/* PMEVTYPERn */
+	PMU_PMEVTYPER(0),
+	PMU_PMEVTYPER(1),
+	PMU_PMEVTYPER(2),
+	PMU_PMEVTYPER(3),
+	PMU_PMEVTYPER(4),
+	PMU_PMEVTYPER(5),
+	PMU_PMEVTYPER(6),
+	PMU_PMEVTYPER(7),
+	PMU_PMEVTYPER(8),
+	PMU_PMEVTYPER(9),
+	PMU_PMEVTYPER(10),
+	PMU_PMEVTYPER(11),
+	PMU_PMEVTYPER(12),
+	PMU_PMEVTYPER(13),
+	PMU_PMEVTYPER(14),
+	PMU_PMEVTYPER(15),
+	PMU_PMEVTYPER(16),
+	PMU_PMEVTYPER(17),
+	PMU_PMEVTYPER(18),
+	PMU_PMEVTYPER(19),
+	PMU_PMEVTYPER(20),
+	PMU_PMEVTYPER(21),
+	PMU_PMEVTYPER(22),
+	PMU_PMEVTYPER(23),
+	PMU_PMEVTYPER(24),
+	PMU_PMEVTYPER(25),
+	PMU_PMEVTYPER(26),
+	PMU_PMEVTYPER(27),
+	PMU_PMEVTYPER(28),
+	PMU_PMEVTYPER(29),
+	PMU_PMEVTYPER(30),
+	/* PMCCFILTR */
+	{ Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
 };
 
 static const struct sys_reg_desc cp15_64_regs[] = {