drm/i915: More use of the cached LRC state

Commit Message

Tvrtko Ursulin Jan. 22, 2016, 12:42 p.m. UTC

From: Tvrtko Ursulin <[e-mail]>

Since:

commit 82352e908acd36d7244c75a008c9f27a2ced44d5
Author: Tvrtko Ursulin <[e-mail]>
Date:   Fri Jan 15 17:12:45 2016 +0000

    drm/i915: Cache LRC state page in the context

and:

commit 0eb973d31d0aadb6bc801fd6d796afecbbfc3d5b
Author: Tvrtko Ursulin <[e-mail]>
Date:   Fri Jan 15 15:10:28 2016 +0000

    drm/i915: Cache ringbuffer GTT VMA

We can also remove the ring buffer start updates on every
context update since the address will not change for the
duration of the LRC pin.

For GuC we can remove the update altogether because it
only cares about the ring buffer start.

Signed-off-by: Tvrtko Ursulin <[e-mail]>
Cc: Alex Dai <[e-mail]>
Cc: Dave Gordon <[e-mail]>
Cc: Chris Wilson <[e-mail]>
---
 drivers/gpu/drm/i915/i915_guc_submission.c | 27 ---------------------------
 drivers/gpu/drm/i915/intel_lrc.c           |  6 ++++--
 2 files changed, 4 insertions(+), 29 deletions(-)

Comments

Chris Wilson Jan. 22, 2016, 1:10 p.m. UTC | #1

On Fri, Jan 22, 2016 at 12:42:47PM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <[e-mail]>
> 
> Since:
> 
> commit 82352e908acd36d7244c75a008c9f27a2ced44d5
> Author: Tvrtko Ursulin <[e-mail]>
> Date:   Fri Jan 15 17:12:45 2016 +0000
> 
>     drm/i915: Cache LRC state page in the context
> 
> and:
> 
> commit 0eb973d31d0aadb6bc801fd6d796afecbbfc3d5b
> Author: Tvrtko Ursulin <[e-mail]>
> Date:   Fri Jan 15 15:10:28 2016 +0000
> 
>     drm/i915: Cache ringbuffer GTT VMA
> 
> We can also remove the ring buffer start updates on every
> context update since the address will not change for the
> duration of the LRC pin.
> 
> For GuC we can remove the update altogether because it
> only cares about the ring buffer start.
> 
> Signed-off-by: Tvrtko Ursulin <[e-mail]>
> Cc: Alex Dai <[e-mail]>
> Cc: Dave Gordon <[e-mail]>
> Cc: Chris Wilson <[e-mail]>

Finally starting to reduce my delta at last :-p
Reviewed-by: Chris Wilson <[e-mail]>
-Chris

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 068315fc7404..ea15e2d9285e 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -560,29 +560,6 @@  static int guc_add_workqueue_item(struct i915_guc_client *gc,
 	return 0;
 }
 
-#define CTX_RING_BUFFER_START		0x08
-
-/* Update the ringbuffer pointer in a saved context image */
-static void lr_context_update(struct drm_i915_gem_request *rq)
-{
-	enum intel_ring_id ring_id = rq->ring->id;
-	struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring_id].state;
-	struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
-	struct page *page;
-	uint32_t *reg_state;
-
-	BUG_ON(!ctx_obj);
-	WARN_ON(!i915_gem_obj_is_pinned(ctx_obj));
-	WARN_ON(!i915_gem_obj_is_pinned(rb_obj));
-
-	page = i915_gem_object_get_dirty_page(ctx_obj, LRC_STATE_PN);
-	reg_state = kmap_atomic(page);
-
-	reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
-
-	kunmap_atomic(reg_state);
-}
-
 /**
  * i915_guc_submit() - Submit commands through GuC
  * @client:	the guc client where commands will go through
@@ -597,10 +574,6 @@  int i915_guc_submit(struct i915_guc_client *client,
 	enum intel_ring_id ring_id = rq->ring->id;
 	int q_ret, b_ret;
 
-	/* Need this because of the deferred pin ctx and ring */
-	/* Shall we move this right after ring is pinned? */
-	lr_context_update(rq);
-
 	q_ret = guc_add_workqueue_item(client, rq);
 	if (q_ret == 0)
 		b_ret = guc_ring_doorbell(client);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7f47948d5c40..43c94af4b81c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -393,7 +393,6 @@  static int execlists_update_context(struct drm_i915_gem_request *rq)
 	uint32_t *reg_state = rq->ctx->engine[ring->id].lrc_reg_state;
 
 	reg_state[CTX_RING_TAIL+1] = rq->tail;
-	reg_state[CTX_RING_BUFFER_START+1] = rq->ringbuf->vma->node.start;
 
 	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
 		/* True 32b PPGTT with dynamic page allocation: update PDP
@@ -1067,6 +1066,7 @@  static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
 	struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
 	struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf;
 	struct page *lrc_state_page;
+	uint32_t *lrc_reg_state;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
@@ -1088,7 +1088,9 @@  static int intel_lr_context_do_pin(struct intel_engine_cs *ring,
 
 	ctx->engine[ring->id].lrc_vma = i915_gem_obj_to_ggtt(ctx_obj);
 	intel_lr_context_descriptor_update(ctx, ring);
-	ctx->engine[ring->id].lrc_reg_state = kmap(lrc_state_page);
+	lrc_reg_state = kmap(lrc_state_page);
+	lrc_reg_state[CTX_RING_BUFFER_START+1] = ringbuf->vma->node.start;
+	ctx->engine[ring->id].lrc_reg_state = lrc_reg_state;
 	ctx_obj->dirty = true;
 
 	/* Invalidate GuC TLB. */