| Message ID | 20170506111431.12548-11-aurelien@aurel32.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Lovely! What about a Coccinelle meta-script to catch similar (ab)uses? Phil. On 05/06/2017 08:14 AM, Aurelien Jarno wrote: > This doesn't change the generated code on x86, but optimizes it on most > RISC architectures and makes the code simpler to read. > > Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/sh4/translate.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/target/sh4/translate.c b/target/sh4/translate.c > index b4e5606098..8c766eed2a 100644 > --- a/target/sh4/translate.c > +++ b/target/sh4/translate.c > @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) > { > tcg_gen_andi_i32(cpu_sr, src, > ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); > - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); > - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); > - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); > - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); > - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); > - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); > + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); > + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); > + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); > } > > static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc) >
On 05/06/2017 04:14 AM, Aurelien Jarno wrote: > This doesn't change the generated code on x86, but optimizes it on most > RISC architectures and makes the code simpler to read. > > Signed-off-by: Aurelien Jarno<aurelien@aurel32.net> > --- > target/sh4/translate.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index b4e5606098..8c766eed2a 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -204,12 +204,9 @@ static void gen_write_sr(TCGv src) { tcg_gen_andi_i32(cpu_sr, src, ~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T))); - tcg_gen_shri_i32(cpu_sr_q, src, SR_Q); - tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1); - tcg_gen_shri_i32(cpu_sr_m, src, SR_M); - tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1); - tcg_gen_shri_i32(cpu_sr_t, src, SR_T); - tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1); + tcg_gen_extract_i32(cpu_sr_q, src, SR_Q, 1); + tcg_gen_extract_i32(cpu_sr_m, src, SR_M, 1); + tcg_gen_extract_i32(cpu_sr_t, src, SR_T, 1); } static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
This doesn't change the generated code on x86, but optimizes it on most RISC architectures and makes the code simpler to read. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target/sh4/translate.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)