diff mbox

[v3,09/15] target/sh4: optimize gen_store_fpr64

Message ID 20170510182636.17791-10-aurelien@aurel32.net (mailing list archive)
State New, archived
Headers show

Commit Message

Aurelien Jarno May 10, 2017, 6:26 p.m. UTC 
Using extr and avoiding intermediate temps.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/sh4/translate.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

Comments

Philippe Mathieu-Daudé May 10, 2017, 11:55 p.m. UTC | #1 
On 05/10/2017 03:26 PM, Aurelien Jarno wrote:
> Using extr and avoiding intermediate temps.
>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> ---
>  target/sh4/translate.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
>
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index a4c7a0895b..fe8bff54a6 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -305,13 +305,7 @@ static inline void gen_load_fpr64(TCGv_i64 t, int reg)
>
>  static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
>  {
> -    TCGv_i32 tmp = tcg_temp_new_i32();
> -    tcg_gen_extrl_i64_i32(tmp, t);
> -    tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
> -    tcg_gen_shri_i64(t, t, 32);
> -    tcg_gen_extrl_i64_i32(tmp, t);
> -    tcg_gen_mov_i32(cpu_fregs[reg], tmp);
> -    tcg_temp_free_i32(tmp);
> +    tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
>  }
>
>  #define B3_0 (ctx->opcode & 0xf)
>
Richard Henderson May 12, 2017, 10:23 p.m. UTC | #2 
On 05/10/2017 11:26 AM, Aurelien Jarno wrote:
> Using extr and avoiding intermediate temps.
> 
> Signed-off-by: Aurelien Jarno<aurelien@aurel32.net>
> ---
>   target/sh4/translate.c | 8 +-------
>   1 file changed, 1 insertion(+), 7 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~
diff mbox

Patch

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4c7a0895b..fe8bff54a6 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -305,13 +305,7 @@  static inline void gen_load_fpr64(TCGv_i64 t, int reg)
 
 static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 {
-    TCGv_i32 tmp = tcg_temp_new_i32();
-    tcg_gen_extrl_i64_i32(tmp, t);
-    tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
-    tcg_gen_shri_i64(t, t, 32);
-    tcg_gen_extrl_i64_i32(tmp, t);
-    tcg_gen_mov_i32(cpu_fregs[reg], tmp);
-    tcg_temp_free_i32(tmp);
+    tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t);
 }
 
 #define B3_0 (ctx->opcode & 0xf)