| Message ID | 1498802721-32455-6-git-send-email-zhi.mao@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 30, 2017 at 02:05:20PM +0800, Zhi Mao wrote: > 1. Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config() > to improve the code readablity. > 2. add pwm clk disable in function:mtk_pwm_config() > for error parameter checking case. > > Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> > --- > drivers/pwm/pwm-mediatek.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) Same comment as before. You've got two logical, unrelated changes in this one commit. In this case you're mixing a cosmetic change with an actual bug fix. And to make things worse, the commit subject mentions only the cosmetic change, while the more important changes is only described in a drive-by fashion. You get another free pass this time, but please be more conscious about these things in the future. I've applied this to for-4.14/drivers with the following commit message: --- >8 --- pwm: mediatek: Disable clock on PWM configuration failure Make sure to disable the PWM clock if the PWM cannot be configured due to the clock divider exceeding the maximum value. While at it, replace the hardcoded maximum clock divider with a defined constant to improve code readability. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> Acked-by: John Crispin <john@phrozen.org> Signed-off-by: Thierry Reding <thierry.reding@gmail.com> --- 8< --- Thierry
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 554a042..1d78ab1 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -30,6 +30,8 @@ #define PWMDWIDTH 0x2c #define PWMTHRES 0x30 +#define PWM_CLK_DIV_MAX 7 + enum { MTK_CLK_MAIN = 0, MTK_CLK_TOP, @@ -130,8 +132,11 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, clkdiv++; } - if (clkdiv > 7) + if (clkdiv > PWM_CLK_DIV_MAX) { + mtk_pwm_clk_disable(chip, pwm); + dev_err(chip->dev, "period %d not supported\n", period_ns); return -EINVAL; + } mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
1. Replace "7" with "PWM_CLK_DIV_MAX" in function:mtk_pwm_config() to improve the code readablity. 2. add pwm clk disable in function:mtk_pwm_config() for error parameter checking case. Signed-off-by: Zhi Mao <zhi.mao@mediatek.com> --- drivers/pwm/pwm-mediatek.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)