| Message ID | 1516203716-4606-3-git-send-email-ulrich.hecht+renesas@gmail.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
Hi Uli, On Wed, Jan 17, 2018 at 4:41 PM, Ulrich Hecht <ulrich.hecht+renesas@gmail.com> wrote: > This patch adds ZG clock divider support for R-Car Gen3 SoC. > > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Thanks for your patch! > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -76,6 +76,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, > #define CPG_FRQCRC 0x000000e0 > #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) > #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) > +#define CPG_FRQCRC_ZGFC_MASK GENMASK(28, 24) According to the BSP, these bits are in FRQCRB, not FRQCRC? Note that the R-Car Gen3 Hardware User's Manual does not document these bits, and declares them read-only, always zero... > @@ -563,6 +564,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, > return cpg_z_clk_register(core->name, __clk_get_name(parent), > base, CPG_FRQCRC_Z2FC_MASK); > > + case CLK_TYPE_GEN3_ZG: > + return cpg_z_clk_register(core->name, __clk_get_name(parent), > + base, CPG_FRQCRC_ZGFC_MASK); I don't think you can do it like that. ZG uses FRQCRB instead of FRQCRC, and uses a fixed divider of 4 instead of 2. While the rest of the handling is similar, both differences need to be taken into account. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a7d68ce..cfbefcc 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -76,6 +76,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) +#define CPG_FRQCRC_ZGFC_MASK GENMASK(28, 24) struct cpg_z_clk { struct clk_hw hw; @@ -563,6 +564,10 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK); + case CLK_TYPE_GEN3_ZG: + return cpg_z_clk_register(core->name, __clk_get_name(parent), + base, CPG_FRQCRC_ZGFC_MASK); + default: return ERR_PTR(-EINVAL); } diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index ea4f8fc..3ae9fe6d 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -23,6 +23,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PE, CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_Z2, + CLK_TYPE_GEN3_ZG, }; #define DEF_GEN3_SD(_name, _id, _parent, _offset) \