[27/36] drm/i915: Split control of rps and rc6

Message ID	20180314093748.8541-27-chris@chris-wilson.co.uk (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Chris Wilson <chris@chris-wilson.co.uk> To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Mar 2018 09:37:39 +0000 Message-Id: <20180314093748.8541-27-chris@chris-wilson.co.uk> In-Reply-To: <20180314093748.8541-1-chris@chris-wilson.co.uk> References: <20180314093748.8541-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6 Precedence: list Cc: praveen.paneri@intel.com MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Message ID

20180314093748.8541-27-chris@chris-wilson.co.uk (mailing list archive)

State

New, archived

Headers

From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Date: Wed, 14 Mar 2018 09:37:39 +0000
Message-Id: <20180314093748.8541-27-chris@chris-wilson.co.uk>
In-Reply-To: <20180314093748.8541-1-chris@chris-wilson.co.uk>
References: <20180314093748.8541-1-chris@chris-wilson.co.uk>
Subject: [Intel-gfx] [PATCH 27/36] drm/i915: Split control of rps and rc6
Precedence: list
Cc: praveen.paneri@intel.com
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Content-Transfer-Encoding: base64
Errors-To: intel-gfx-bounces@lists.freedesktop.org
Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>

Commit Message

Chris Wilson March 14, 2018, 9:37 a.m. UTC

Allow ourselves to individually toggle rps or rc6. This will be used
later when we want to enable rps/rc6 at different phases during the
device bring up.

Whilst here, convert the intel_$verb_gt_powersave over to
intel_gt_pm_$verb scheme.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.c      |  6 +--
 drivers/gpu/drm/i915/i915_drv.h      |  5 ---
 drivers/gpu/drm/i915/i915_gem.c      | 23 +++++------
 drivers/gpu/drm/i915/i915_request.c  |  4 +-
 drivers/gpu/drm/i915/intel_display.c |  5 ++-
 drivers/gpu/drm/i915/intel_gt_pm.c   | 75 +++++++++++++++---------------------
 drivers/gpu/drm/i915/intel_gt_pm.h   | 14 ++++---
 7 files changed, 60 insertions(+), 72 deletions(-)

Comments

sagar.a.kamble@intel.com March 16, 2018, 8:52 a.m. UTC | #1

On 3/14/2018 3:07 PM, Chris Wilson wrote:
> Allow ourselves to individually toggle rps or rc6. This will be used
> later when we want to enable rps/rc6 at different phases during the
> device bring up.
>
> Whilst here, convert the intel_$verb_gt_powersave over to
> intel_gt_pm_$verb scheme.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
<snip>
> +void intel_gt_pm_init(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>   
> @@ -2475,22 +2477,13 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>   	/* Finally allow us to boost to max by default */
>   	rps->boost_freq = rps->max_freq;
>   
> -	mutex_unlock(&rps->lock);
> -}
> -
> -static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
> -{
> -	lockdep_assert_held(&i915->gt_pm.rps.lock);
> -
> -	if (i915->gt_pm.llc_pstate.enabled)
> -		return;
> -
> -	gen6_update_ring_freq(i915);
> +	if (HAS_LLC(dev_priv))
> +		gen6_update_ring_freq(dev_priv);
Ring frequency table update has to be done on resuming from sleep or 
reset as well hence we will
need to possibly move it either __enable_rps or gt_pm_sanitize(provided 
we guard against "rps initialized")
Verified on my SKL system. Otherwise, patch looks good to me.

Thanks,
Sagar
>   
> -	i915->gt_pm.llc_pstate.enabled = true;
> +	mutex_unlock(&rps->lock);
>   }
>   
> -static void intel_enable_rc6(struct drm_i915_private *dev_priv)
> +static void __enable_rc6(struct drm_i915_private *dev_priv)
>   {
>   	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>   
> @@ -2511,7 +2504,7 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv)
>   	dev_priv->gt_pm.rc6.enabled = true;
>   }
>   
> -static void intel_enable_rps(struct drm_i915_private *dev_priv)
> +static void __enable_rps(struct drm_i915_private *dev_priv)
>   {
>   	struct intel_rps *rps = &dev_priv->gt_pm.rps;
>   
> @@ -2546,37 +2539,27 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>   	rps->enabled = true;
>   }
>   
> -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> +void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
>   {
> -	/* Powersaving is controlled by the host when inside a VM */
> -	if (intel_vgpu_active(dev_priv))
> +	if (!HAS_RC6(dev_priv))
>   		return;
>   
>   	mutex_lock(&dev_priv->gt_pm.rps.lock);
> -
> -	if (HAS_RC6(dev_priv))
> -		intel_enable_rc6(dev_priv);
> -	if (HAS_RPS(dev_priv))
> -		intel_enable_rps(dev_priv);
> -	if (HAS_LLC(dev_priv))
> -		intel_enable_llc_pstate(dev_priv);
> -
> +	__enable_rc6(dev_priv);
>   	mutex_unlock(&dev_priv->gt_pm.rps.lock);
>   }
>   
> -static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> +void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
>   {
> -	lockdep_assert_held(&i915->gt_pm.rps.lock);
> -
> -	if (!i915->gt_pm.llc_pstate.enabled)
> +	if (!HAS_RPS(dev_priv))
>   		return;
>   
> -	/* Currently there is no HW configuration to be done to disable. */
> -
> -	i915->gt_pm.llc_pstate.enabled = false;
> +	mutex_lock(&dev_priv->gt_pm.rps.lock);
> +	__enable_rps(dev_priv);
> +	mutex_unlock(&dev_priv->gt_pm.rps.lock);
>   }
>   
> -static void intel_disable_rc6(struct drm_i915_private *dev_priv)
> +static void __disable_rc6(struct drm_i915_private *dev_priv)
>   {
>   	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>   
> @@ -2595,7 +2578,14 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>   	dev_priv->gt_pm.rc6.enabled = false;
>   }
>   
> -static void intel_disable_rps(struct drm_i915_private *dev_priv)
> +void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
> +{
> +	mutex_lock(&dev_priv->gt_pm.rps.lock);
> +	__disable_rc6(dev_priv);
> +	mutex_unlock(&dev_priv->gt_pm.rps.lock);
> +}
> +
> +static void __disable_rps(struct drm_i915_private *dev_priv)
>   {
>   	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>   
> @@ -2616,19 +2606,14 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
>   	dev_priv->gt_pm.rps.enabled = false;
>   }
>   
> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
> +void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
>   {
>   	mutex_lock(&dev_priv->gt_pm.rps.lock);
> -
> -	intel_disable_rc6(dev_priv);
> -	intel_disable_rps(dev_priv);
> -	if (HAS_LLC(dev_priv))
> -		intel_disable_llc_pstate(dev_priv);
> -
> +	__disable_rps(dev_priv);
>   	mutex_unlock(&dev_priv->gt_pm.rps.lock);
>   }
>   
> -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
> +void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
>   {
>   	if (IS_VALLEYVIEW(dev_priv))
>   		valleyview_cleanup_gt_powersave(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
> index 722325bbb6cc..5975c63f46bf 100644
> --- a/drivers/gpu/drm/i915/intel_gt_pm.h
> +++ b/drivers/gpu/drm/i915/intel_gt_pm.h
> @@ -31,12 +31,16 @@ struct intel_rps_client;
>   void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
>   void intel_gpu_ips_teardown(void);
>   
> -void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
> +void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv);
>   
> -void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
> -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
> -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
> +void intel_gt_pm_init(struct drm_i915_private *dev_priv);
> +void intel_gt_pm_fini(struct drm_i915_private *dev_priv);
> +
> +void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv);
> +void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv);
> +
> +void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv);
> +void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv);
>   
>   void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
>

sagar.a.kamble@intel.com March 16, 2018, 1:03 p.m. UTC | #2

On 3/16/2018 2:22 PM, Sagar Arun Kamble wrote:
>
>
> On 3/14/2018 3:07 PM, Chris Wilson wrote:
>> Allow ourselves to individually toggle rps or rc6. This will be used
>> later when we want to enable rps/rc6 at different phases during the
>> device bring up.
>>
>> Whilst here, convert the intel_$verb_gt_powersave over to
>> intel_gt_pm_$verb scheme.
>>
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> <snip>
>> +void intel_gt_pm_init(struct drm_i915_private *dev_priv)
>>   {
>>       struct intel_rps *rps = &dev_priv->gt_pm.rps;
>>   @@ -2475,22 +2477,13 @@ void intel_init_gt_powersave(struct 
>> drm_i915_private *dev_priv)
>>       /* Finally allow us to boost to max by default */
>>       rps->boost_freq = rps->max_freq;
>>   -    mutex_unlock(&rps->lock);
>> -}
>> -
>> -static inline void intel_enable_llc_pstate(struct drm_i915_private 
>> *i915)
>> -{
>> -    lockdep_assert_held(&i915->gt_pm.rps.lock);
>> -
>> -    if (i915->gt_pm.llc_pstate.enabled)
>> -        return;
>> -
>> -    gen6_update_ring_freq(i915);
>> +    if (HAS_LLC(dev_priv))
>> +        gen6_update_ring_freq(dev_priv);
> Ring frequency table update has to be done on resuming from sleep or 
> reset as well hence we will
not required on resume from reset :)
> need to possibly move it either __enable_rps or 
> gt_pm_sanitize(provided we guard against "rps initialized")
> Verified on my SKL system. Otherwise, patch looks good to me.
>
> Thanks,
> Sagar
>>   -    i915->gt_pm.llc_pstate.enabled = true;
>> +    mutex_unlock(&rps->lock);
>>   }
>>   -static void intel_enable_rc6(struct drm_i915_private *dev_priv)
>> +static void __enable_rc6(struct drm_i915_private *dev_priv)
>>   {
>>       lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>>   @@ -2511,7 +2504,7 @@ static void intel_enable_rc6(struct 
>> drm_i915_private *dev_priv)
>>       dev_priv->gt_pm.rc6.enabled = true;
>>   }
>>   -static void intel_enable_rps(struct drm_i915_private *dev_priv)
>> +static void __enable_rps(struct drm_i915_private *dev_priv)
>>   {
>>       struct intel_rps *rps = &dev_priv->gt_pm.rps;
>>   @@ -2546,37 +2539,27 @@ static void intel_enable_rps(struct 
>> drm_i915_private *dev_priv)
>>       rps->enabled = true;
>>   }
>>   -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>> +void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
>>   {
>> -    /* Powersaving is controlled by the host when inside a VM */
>> -    if (intel_vgpu_active(dev_priv))
>> +    if (!HAS_RC6(dev_priv))
>>           return;
>>         mutex_lock(&dev_priv->gt_pm.rps.lock);
>> -
>> -    if (HAS_RC6(dev_priv))
>> -        intel_enable_rc6(dev_priv);
>> -    if (HAS_RPS(dev_priv))
>> -        intel_enable_rps(dev_priv);
>> -    if (HAS_LLC(dev_priv))
>> -        intel_enable_llc_pstate(dev_priv);
>> -
>> +    __enable_rc6(dev_priv);
>>       mutex_unlock(&dev_priv->gt_pm.rps.lock);
>>   }
>>   -static inline void intel_disable_llc_pstate(struct 
>> drm_i915_private *i915)
>> +void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
>>   {
>> -    lockdep_assert_held(&i915->gt_pm.rps.lock);
>> -
>> -    if (!i915->gt_pm.llc_pstate.enabled)
>> +    if (!HAS_RPS(dev_priv))
>>           return;
>>   -    /* Currently there is no HW configuration to be done to 
>> disable. */
>> -
>> -    i915->gt_pm.llc_pstate.enabled = false;
>> +    mutex_lock(&dev_priv->gt_pm.rps.lock);
>> +    __enable_rps(dev_priv);
>> +    mutex_unlock(&dev_priv->gt_pm.rps.lock);
>>   }
>>   -static void intel_disable_rc6(struct drm_i915_private *dev_priv)
>> +static void __disable_rc6(struct drm_i915_private *dev_priv)
>>   {
>>       lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>>   @@ -2595,7 +2578,14 @@ static void intel_disable_rc6(struct 
>> drm_i915_private *dev_priv)
>>       dev_priv->gt_pm.rc6.enabled = false;
>>   }
>>   -static void intel_disable_rps(struct drm_i915_private *dev_priv)
>> +void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
>> +{
>> +    mutex_lock(&dev_priv->gt_pm.rps.lock);
>> +    __disable_rc6(dev_priv);
>> +    mutex_unlock(&dev_priv->gt_pm.rps.lock);
>> +}
>> +
>> +static void __disable_rps(struct drm_i915_private *dev_priv)
>>   {
>>       lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
>>   @@ -2616,19 +2606,14 @@ static void intel_disable_rps(struct 
>> drm_i915_private *dev_priv)
>>       dev_priv->gt_pm.rps.enabled = false;
>>   }
>>   -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
>> +void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
>>   {
>>       mutex_lock(&dev_priv->gt_pm.rps.lock);
>> -
>> -    intel_disable_rc6(dev_priv);
>> -    intel_disable_rps(dev_priv);
>> -    if (HAS_LLC(dev_priv))
>> -        intel_disable_llc_pstate(dev_priv);
>> -
>> +    __disable_rps(dev_priv);
>>       mutex_unlock(&dev_priv->gt_pm.rps.lock);
>>   }
>>   -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
>> +void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
>>   {
>>       if (IS_VALLEYVIEW(dev_priv))
>>           valleyview_cleanup_gt_powersave(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h 
>> b/drivers/gpu/drm/i915/intel_gt_pm.h
>> index 722325bbb6cc..5975c63f46bf 100644
>> --- a/drivers/gpu/drm/i915/intel_gt_pm.h
>> +++ b/drivers/gpu/drm/i915/intel_gt_pm.h
>> @@ -31,12 +31,16 @@ struct intel_rps_client;
>>   void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
>>   void intel_gpu_ips_teardown(void);
>>   -void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
>> +void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv);
>>   -void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
>> -void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
>> -void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
>> -void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
>> +void intel_gt_pm_init(struct drm_i915_private *dev_priv);
>> +void intel_gt_pm_fini(struct drm_i915_private *dev_priv);
>> +
>> +void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv);
>> +void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv);
>> +
>> +void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv);
>> +void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv);
>>     void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, 
>> u32 pm_iir);
>

Chris Wilson April 10, 2018, 12:36 p.m. UTC | #3

Quoting Sagar Arun Kamble (2018-03-16 13:03:03)
> 
> 
> On 3/16/2018 2:22 PM, Sagar Arun Kamble wrote:
> >
> >
> > On 3/14/2018 3:07 PM, Chris Wilson wrote:
> >> Allow ourselves to individually toggle rps or rc6. This will be used
> >> later when we want to enable rps/rc6 at different phases during the
> >> device bring up.
> >>
> >> Whilst here, convert the intel_$verb_gt_powersave over to
> >> intel_gt_pm_$verb scheme.
> >>
> >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > <snip>
> >> +void intel_gt_pm_init(struct drm_i915_private *dev_priv)
> >>   {
> >>       struct intel_rps *rps = &dev_priv->gt_pm.rps;
> >>   @@ -2475,22 +2477,13 @@ void intel_init_gt_powersave(struct 
> >> drm_i915_private *dev_priv)
> >>       /* Finally allow us to boost to max by default */
> >>       rps->boost_freq = rps->max_freq;
> >>   -    mutex_unlock(&rps->lock);
> >> -}
> >> -
> >> -static inline void intel_enable_llc_pstate(struct drm_i915_private 
> >> *i915)
> >> -{
> >> -    lockdep_assert_held(&i915->gt_pm.rps.lock);
> >> -
> >> -    if (i915->gt_pm.llc_pstate.enabled)
> >> -        return;
> >> -
> >> -    gen6_update_ring_freq(i915);
> >> +    if (HAS_LLC(dev_priv))
> >> +        gen6_update_ring_freq(dev_priv);
> > Ring frequency table update has to be done on resuming from sleep or 
> > reset as well hence we will
> not required on resume from reset :)

Good. Then it should be covered by the code that enables the powersaving
on init/resume; and we are good to remove the gunk from reset.
-Chris

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f47d1706ac02..db88b8c3c4ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1063,7 +1063,7 @@  static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
  */
 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 {
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 	intel_uncore_fini(dev_priv);
 	i915_mmio_cleanup(dev_priv);
 	pci_dev_put(dev_priv->bridge_dev);
@@ -1170,7 +1170,7 @@  static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 	intel_uncore_sanitize(dev_priv);
 
 	/* BIOS often leaves RC6 enabled, but disable it for hw init */
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 
 	intel_opregion_setup(dev_priv);
 
@@ -1714,7 +1714,7 @@  static int i915_drm_resume(struct drm_device *dev)
 	int ret;
 
 	disable_rpm_wakeref_asserts(dev_priv);
-	intel_sanitize_gt_powersave(dev_priv);
+	intel_gt_pm_sanitize(dev_priv);
 
 	ret = i915_ggtt_enable_hw(dev_priv);
 	if (ret)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 825a6fd8423b..0acabfd1e3e7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -788,14 +788,9 @@  struct intel_rc6 {
 	u64 cur_residency[4];
 };
 
-struct intel_llc_pstate {
-	bool enabled;
-};
-
 struct intel_gen6_power_mgmt {
 	struct intel_rps rps;
 	struct intel_rc6 rc6;
-	struct intel_llc_pstate llc_pstate;
 
 	u32 imr;
 	u32 ier;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8112cbd6e0af..b9c7b21e5cc8 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3166,8 +3166,9 @@  void i915_gem_reset(struct drm_i915_private *dev_priv)
 	i915_gem_restore_fences(dev_priv);
 
 	if (dev_priv->gt.awake) {
-		intel_sanitize_gt_powersave(dev_priv);
-		intel_enable_gt_powersave(dev_priv);
+		intel_gt_pm_sanitize(dev_priv);
+		intel_gt_pm_enable_rps(dev_priv);
+		intel_gt_pm_enable_rc6(dev_priv);
 		if (INTEL_GEN(dev_priv) >= 6)
 			gen6_rps_busy(dev_priv);
 	}
@@ -5315,10 +5316,12 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 		goto err_unlock;
 	}
 
+	intel_gt_pm_init(dev_priv);
+
 	ret = i915_gem_contexts_init(dev_priv);
 	if (ret) {
 		GEM_BUG_ON(ret == -EIO);
-		goto err_ggtt;
+		goto err_pm;
 	}
 
 	ret = intel_engines_init(dev_priv);
@@ -5327,11 +5330,9 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 		goto err_context;
 	}
 
-	intel_init_gt_powersave(dev_priv);
-
 	ret = intel_uc_init(dev_priv);
 	if (ret)
-		goto err_pm;
+		goto err_engines;
 
 	ret = i915_gem_init_hw(dev_priv);
 	if (ret)
@@ -5379,15 +5380,15 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 	intel_uc_fini_hw(dev_priv);
 err_uc_init:
 	intel_uc_fini(dev_priv);
-err_pm:
-	if (ret != -EIO) {
-		intel_cleanup_gt_powersave(dev_priv);
+err_engines:
+	if (ret != -EIO)
 		i915_gem_cleanup_engines(dev_priv);
-	}
 err_context:
 	if (ret != -EIO)
 		i915_gem_contexts_fini(dev_priv);
-err_ggtt:
+err_pm:
+	if (ret != -EIO)
+		intel_gt_pm_fini(dev_priv);
 err_unlock:
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 	mutex_unlock(&dev_priv->drm.struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 3605d5f1a226..624c7cd207d2 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -274,7 +274,9 @@  static void mark_busy(struct drm_i915_private *i915)
 	if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */
 		i915->gt.epoch = 1;
 
-	intel_enable_gt_powersave(i915);
+	intel_gt_pm_enable_rps(i915);
+	intel_gt_pm_enable_rc6(i915);
+
 	i915_update_gfx_val(i915);
 	if (INTEL_GEN(i915) >= 6)
 		gen6_rps_busy(i915);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ba9aa8385204..892c274eb47b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15426,7 +15426,8 @@  void intel_modeset_cleanup(struct drm_device *dev)
 	flush_work(&dev_priv->atomic_helper.free_work);
 	WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
 
-	intel_disable_gt_powersave(dev_priv);
+	intel_gt_pm_disable_rps(dev_priv);
+	intel_gt_pm_disable_rc6(dev_priv);
 
 	/*
 	 * Interrupts and polling as the first thing to avoid creating havoc.
@@ -15455,7 +15456,7 @@  void intel_modeset_cleanup(struct drm_device *dev)
 
 	intel_cleanup_overlay(dev_priv);
 
-	intel_cleanup_gt_powersave(dev_priv);
+	intel_gt_pm_fini(dev_priv);
 
 	intel_teardown_gmbus(dev_priv);
 
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index feb3bf060f78..c5d0382c934d 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2383,11 +2383,13 @@  static void intel_init_emon(struct drm_i915_private *dev_priv)
 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
 }
 
-void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv)
 {
 	dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */
+	intel_gt_pm_disable_rps(dev_priv);
+
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
-	intel_disable_gt_powersave(dev_priv);
+	intel_gt_pm_disable_rc6(dev_priv);
 
 	if (INTEL_GEN(dev_priv) < 11)
 		gen6_reset_rps_interrupts(dev_priv);
@@ -2395,7 +2397,7 @@  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 		WARN_ON_ONCE(1);
 }
 
-void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_init(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
@@ -2475,22 +2477,13 @@  void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
 	/* Finally allow us to boost to max by default */
 	rps->boost_freq = rps->max_freq;
 
-	mutex_unlock(&rps->lock);
-}
-
-static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
-{
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (i915->gt_pm.llc_pstate.enabled)
-		return;
-
-	gen6_update_ring_freq(i915);
+	if (HAS_LLC(dev_priv))
+		gen6_update_ring_freq(dev_priv);
 
-	i915->gt_pm.llc_pstate.enabled = true;
+	mutex_unlock(&rps->lock);
 }
 
-static void intel_enable_rc6(struct drm_i915_private *dev_priv)
+static void __enable_rc6(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
 
@@ -2511,7 +2504,7 @@  static void intel_enable_rc6(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = true;
 }
 
-static void intel_enable_rps(struct drm_i915_private *dev_priv)
+static void __enable_rps(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
 
@@ -2546,37 +2539,27 @@  static void intel_enable_rps(struct drm_i915_private *dev_priv)
 	rps->enabled = true;
 }
 
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv)
 {
-	/* Powersaving is controlled by the host when inside a VM */
-	if (intel_vgpu_active(dev_priv))
+	if (!HAS_RC6(dev_priv))
 		return;
 
 	mutex_lock(&dev_priv->gt_pm.rps.lock);
-
-	if (HAS_RC6(dev_priv))
-		intel_enable_rc6(dev_priv);
-	if (HAS_RPS(dev_priv))
-		intel_enable_rps(dev_priv);
-	if (HAS_LLC(dev_priv))
-		intel_enable_llc_pstate(dev_priv);
-
+	__enable_rc6(dev_priv);
 	mutex_unlock(&dev_priv->gt_pm.rps.lock);
 }
 
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv)
 {
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (!i915->gt_pm.llc_pstate.enabled)
+	if (!HAS_RPS(dev_priv))
 		return;
 
-	/* Currently there is no HW configuration to be done to disable. */
-
-	i915->gt_pm.llc_pstate.enabled = false;
+	mutex_lock(&dev_priv->gt_pm.rps.lock);
+	__enable_rps(dev_priv);
+	mutex_unlock(&dev_priv->gt_pm.rps.lock);
 }
 
-static void intel_disable_rc6(struct drm_i915_private *dev_priv)
+static void __disable_rc6(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
 
@@ -2595,7 +2578,14 @@  static void intel_disable_rc6(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = false;
 }
 
-static void intel_disable_rps(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv)
+{
+	mutex_lock(&dev_priv->gt_pm.rps.lock);
+	__disable_rc6(dev_priv);
+	mutex_unlock(&dev_priv->gt_pm.rps.lock);
+}
+
+static void __disable_rps(struct drm_i915_private *dev_priv)
 {
 	lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
 
@@ -2616,19 +2606,14 @@  static void intel_disable_rps(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rps.enabled = false;
 }
 
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv)
 {
 	mutex_lock(&dev_priv->gt_pm.rps.lock);
-
-	intel_disable_rc6(dev_priv);
-	intel_disable_rps(dev_priv);
-	if (HAS_LLC(dev_priv))
-		intel_disable_llc_pstate(dev_priv);
-
+	__disable_rps(dev_priv);
 	mutex_unlock(&dev_priv->gt_pm.rps.lock);
 }
 
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
+void intel_gt_pm_fini(struct drm_i915_private *dev_priv)
 {
 	if (IS_VALLEYVIEW(dev_priv))
 		valleyview_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index 722325bbb6cc..5975c63f46bf 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -31,12 +31,16 @@  struct intel_rps_client;
 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
 void intel_gpu_ips_teardown(void);
 
-void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_gt_pm_sanitize(struct drm_i915_private *dev_priv);
 
-void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
-void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
+void intel_gt_pm_init(struct drm_i915_private *dev_priv);
+void intel_gt_pm_fini(struct drm_i915_private *dev_priv);
+
+void intel_gt_pm_enable_rps(struct drm_i915_private *dev_priv);
+void intel_gt_pm_disable_rps(struct drm_i915_private *dev_priv);
+
+void intel_gt_pm_enable_rc6(struct drm_i915_private *dev_priv);
+void intel_gt_pm_disable_rc6(struct drm_i915_private *dev_priv);
 
 void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);

[27/36] drm/i915: Split control of rps and rc6

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