diff mbox

[1/5] drm/i915: Clean up ADPA pipe select bits

Message ID 20180514172423.9302-1-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä May 14, 2018, 5:24 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Clean up the ADPA pipe select bits. To make the whole situation a bit
less ugly we'll start to share the same code between .get_hw_state()
and the port state asserts.

v2: Order the defines shift,mask,value (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 11 +++++-----
 drivers/gpu/drm/i915/intel_crt.c     | 40 ++++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
 drivers/gpu/drm/i915/intel_drv.h     |  2 ++
 4 files changed, 33 insertions(+), 44 deletions(-)

Comments

Ville Syrjälä May 15, 2018, 2:56 p.m. UTC | #1
On Tue, May 15, 2018 at 02:47:48AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: series starting with [1/5] drm/i915: Clean up ADPA pipe select bits (rev2)
> URL   : https://patchwork.freedesktop.org/series/43151/
> State : failure
> 
> == Summary ==
> 
> = CI Bug Log - changes from CI_DRM_4179_full -> Patchwork_8997_full =
> 
> == Summary - FAILURE ==
> 
>   Serious unknown changes coming with Patchwork_8997_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_8997_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://patchwork.freedesktop.org/api/1.0/series/43151/revisions/2/mbox/
> 
> == Possible new issues ==
> 
>   Here are the unknown changes that may have been introduced in Patchwork_8997_full:
> 
>   === IGT changes ===
> 
>     ==== Possible regressions ====
> 
>     igt@gem_eio@in-flight-contexts-1us:
>       shard-apl:          PASS -> DMESG-WARN +1
> 
>     igt@gem_eio@unwedge-stress:
>       shard-glk:          PASS -> DMESG-WARN +1
>       shard-snb:          PASS -> DMESG-WARN +1

kthread_park() WARNs from -rc5.

> 
>     igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
>       shard-glk:          PASS -> FAIL

(kms_cursor_legacy:4524) CRITICAL: Test assertion failure function two_screens_flip_vs_cursor, file ../tests/kms_cursor_legacy.c:1013:
(kms_cursor_legacy:4524) CRITICAL: Failed assertion: vblank_matches
(kms_cursor_legacy:4524) CRITICAL: Last errno: 25, Inappropriate ioctl for device
(kms_cursor_legacy:4524) CRITICAL: During modeset at least 1 page flip needs to match!

Looks ping-pongy already on glk.

> 
>     
>     ==== Warnings ====
> 
>     igt@gem_mocs_settings@mocs-rc6-blt:
>       shard-kbl:          PASS -> SKIP

Test requirement not met in function rc6_wait, file ../tests/gem_mocs_settings.c:346:
Test requirement: igt_wait(rc6_residency(sysfs) != residency, 10000, 2)

Nothing in these look relevant for these patches.

> 
>     igt@gem_mocs_settings@mocs-rc6-dirty-render:
>       shard-kbl:          SKIP -> PASS +1
> 
>     
> == Known issues ==
> 
>   Here are the changes found in Patchwork_8997_full that come from known issues:
> 
>   === IGT changes ===
> 
>     ==== Issues hit ====
> 
>     igt@gem_ppgtt@blt-vs-render-ctxn:
>       shard-kbl:          PASS -> INCOMPLETE (fdo#106023, fdo#103665)
> 
>     igt@kms_3d:
>       shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558)
> 
>     igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
>       shard-hsw:          PASS -> FAIL (fdo#105707)
> 
>     igt@kms_flip@basic-flip-vs-wf_vblank:
>       shard-hsw:          PASS -> FAIL (fdo#103928)
> 
>     igt@kms_flip@flip-vs-wf_vblank-interruptible:
>       shard-hsw:          PASS -> FAIL (fdo#100368) +1
> 
>     igt@kms_flip@plain-flip-fb-recreate-interruptible:
>       shard-glk:          PASS -> FAIL (fdo#100368) +1
> 
>     igt@kms_flip_tiling@flip-to-y-tiled:
>       shard-glk:          PASS -> FAIL (fdo#104724)
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
>       shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103313, fdo#103558) +7
> 
>     igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
>       shard-kbl:          PASS -> DMESG-WARN (fdo#106247)
> 
>     igt@kms_frontbuffer_tracking@fbc-suspend:
>       shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558, fdo#103841)
> 
>     igt@kms_setmode@basic:
>       shard-kbl:          PASS -> FAIL (fdo#99912)
> 
>     
>     ==== Possible fixes ====
> 
>     igt@drv_suspend@fence-restore-untiled:
>       shard-glk:          DMESG-WARN -> PASS +2
> 
>     igt@gem_eio@in-flight-1us:
>       shard-hsw:          DMESG-WARN -> PASS
> 
>     igt@gem_eio@in-flight-suspend:
>       shard-snb:          DMESG-WARN -> PASS
> 
>     igt@gem_eio@wait-wedge-10ms:
>       shard-apl:          DMESG-WARN -> PASS +1
> 
>     igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
>       shard-glk:          FAIL -> PASS +3
> 
>     igt@kms_cursor_crc@cursor-64x21-sliding:
>       shard-kbl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +4
> 
>     igt@kms_cursor_legacy@flip-vs-cursor-legacy:
>       shard-hsw:          FAIL (fdo#102670) -> PASS
> 
>     igt@kms_flip@2x-flip-vs-expired-vblank:
>       shard-glk:          FAIL (fdo#105363) -> PASS
> 
>     igt@kms_flip_tiling@flip-y-tiled:
>       shard-glk:          FAIL (fdo#103822, fdo#104724) -> PASS
> 
>     igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
>       shard-snb:          FAIL (fdo#103166, fdo#104724) -> PASS
> 
>     igt@perf@polling:
>       shard-hsw:          FAIL (fdo#102252) -> PASS
> 
>     
>   fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
>   fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
>   fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
>   fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
>   fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
>   fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
>   fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
>   fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
>   fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
>   fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
>   fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
>   fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
>   fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
>   fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
>   fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
>   fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
>   fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> 
> 
> == Participating hosts (5 -> 5) ==
> 
>   No changes in participating hosts
> 
> 
> == Build changes ==
> 
>     * Linux: CI_DRM_4179 -> Patchwork_8997
> 
>   CI_DRM_4179: be6d36ea8d6130f54ab5ec816555f1a46bd95f7b @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_4479: 89ae332745e31a075747a63ac5acc5baccf75769 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>   Patchwork_8997: 004ffb58f52776d11f993197577ea98baa95a019 @ git://anongit.freedesktop.org/gfx-ci/linux
>   piglit_4479: 3ba0657bff4216d1ec7179935590261855f1651e @ git://anongit.freedesktop.org/piglit
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8997/shards.html
Jani Nikula May 17, 2018, 9:31 a.m. UTC | #2
On Mon, 14 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Clean up the ADPA pipe select bits. To make the whole situation a bit
> less ugly we'll start to share the same code between .get_hw_state()
> and the port state asserts.
>
> v2: Order the defines shift,mask,value (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Yup, the series looks good.

BR,
Jani.

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 11 +++++-----
>  drivers/gpu/drm/i915/intel_crt.c     | 40 ++++++++++++++++++------------------
>  drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
>  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
>  4 files changed, 33 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f11bb213ec07..ae3c26216996 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4133,11 +4133,12 @@ enum {
>  
>  #define   ADPA_DAC_ENABLE	(1<<31)
>  #define   ADPA_DAC_DISABLE	0
> -#define   ADPA_PIPE_SELECT_MASK	(1<<30)
> -#define   ADPA_PIPE_A_SELECT	0
> -#define   ADPA_PIPE_B_SELECT	(1<<30)
> -#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
> -/* CPT uses bits 29:30 for pch transcoder select */
> +#define   ADPA_PIPE_SEL_SHIFT		30
> +#define   ADPA_PIPE_SEL_MASK		(1<<30)
> +#define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
> +#define   ADPA_PIPE_SEL_SHIFT_CPT	29
> +#define   ADPA_PIPE_SEL_MASK_CPT	(3<<29)
> +#define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
>  #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
>  #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
>  #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index de0e22322c76..211d601cd1b1 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
>  	return intel_encoder_to_crt(intel_attached_encoder(connector));
>  }
>  
> +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> +			    i915_reg_t adpa_reg, enum pipe *pipe)
> +{
> +	u32 val;
> +
> +	val = I915_READ(adpa_reg);
> +
> +	/* asserts want to know the pipe even if the port is disabled */
> +	if (HAS_PCH_CPT(dev_priv))
> +		*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
> +	else
> +		*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
> +
> +	return val & ADPA_DAC_ENABLE;
> +}
> +
>  static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
>  				   enum pipe *pipe)
>  {
> -	struct drm_device *dev = encoder->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crt *crt = intel_encoder_to_crt(encoder);
> -	u32 tmp;
>  	bool ret;
>  
>  	if (!intel_display_power_get_if_enabled(dev_priv,
>  						encoder->power_domain))
>  		return false;
>  
> -	ret = false;
> -
> -	tmp = I915_READ(crt->adpa_reg);
> -
> -	if (!(tmp & ADPA_DAC_ENABLE))
> -		goto out;
> +	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
>  
> -	if (HAS_PCH_CPT(dev_priv))
> -		*pipe = PORT_TO_PIPE_CPT(tmp);
> -	else
> -		*pipe = PORT_TO_PIPE(tmp);
> -
> -	ret = true;
> -out:
>  	intel_display_power_put(dev_priv, encoder->power_domain);
>  
>  	return ret;
> @@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
>  	if (HAS_PCH_LPT(dev_priv))
>  		; /* Those bits don't exist here */
>  	else if (HAS_PCH_CPT(dev_priv))
> -		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> -	else if (crtc->pipe == 0)
> -		adpa |= ADPA_PIPE_A_SELECT;
> +		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
>  	else
> -		adpa |= ADPA_PIPE_B_SELECT;
> +		adpa |= ADPA_PIPE_SEL(crtc->pipe);
>  
>  	if (!HAS_PCH_SPLIT(dev_priv))
>  		I915_WRITE(BCLRPAT(crtc->pipe), 0);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ad588d564198..6daa8d97a0aa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
>  	return true;
>  }
>  
> -static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
> -			      enum pipe pipe, u32 val)
> -{
> -	if ((val & ADPA_DAC_ENABLE) == 0)
> -		return false;
> -	if (HAS_PCH_CPT(dev_priv)) {
> -		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
> -			return false;
> -	} else {
> -		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
> -			return false;
> -	}
> -	return true;
> -}
> -
>  static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
>  				   enum pipe pipe, i915_reg_t reg,
>  				   u32 port_sel)
> @@ -1405,16 +1390,17 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
>  static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  				      enum pipe pipe)
>  {
> +	enum pipe port_pipe;
>  	u32 val;
>  
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
>  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
>  
> -	val = I915_READ(PCH_ADPA);
> -	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
> -	     "PCH VGA enabled on transcoder %c, should be disabled\n",
> -	     pipe_name(pipe));
> +	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> +			port_pipe == pipe,
> +			"PCH VGA enabled on transcoder %c, should be disabled\n",
> +			pipe_name(pipe));
>  
>  	val = I915_READ(PCH_LVDS);
>  	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d7dbca1aabff..423795050970 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1377,6 +1377,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
>  void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
>  
>  /* intel_crt.c */
> +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> +			    i915_reg_t adpa_reg, enum pipe *pipe);
>  void intel_crt_init(struct drm_i915_private *dev_priv);
>  void intel_crt_reset(struct drm_encoder *encoder);
Ville Syrjälä May 17, 2018, 5:03 p.m. UTC | #3
On Thu, May 17, 2018 at 12:31:59PM +0300, Jani Nikula wrote:
> On Mon, 14 May 2018, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Clean up the ADPA pipe select bits. To make the whole situation a bit
> > less ugly we'll start to share the same code between .get_hw_state()
> > and the port state asserts.
> >
> > v2: Order the defines shift,mask,value (Jani)
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> Yup, the series looks good.

Cool. Pushed to dinq.

> 
> BR,
> Jani.
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      | 11 +++++-----
> >  drivers/gpu/drm/i915/intel_crt.c     | 40 ++++++++++++++++++------------------
> >  drivers/gpu/drm/i915/intel_display.c | 24 +++++-----------------
> >  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
> >  4 files changed, 33 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f11bb213ec07..ae3c26216996 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4133,11 +4133,12 @@ enum {
> >  
> >  #define   ADPA_DAC_ENABLE	(1<<31)
> >  #define   ADPA_DAC_DISABLE	0
> > -#define   ADPA_PIPE_SELECT_MASK	(1<<30)
> > -#define   ADPA_PIPE_A_SELECT	0
> > -#define   ADPA_PIPE_B_SELECT	(1<<30)
> > -#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
> > -/* CPT uses bits 29:30 for pch transcoder select */
> > +#define   ADPA_PIPE_SEL_SHIFT		30
> > +#define   ADPA_PIPE_SEL_MASK		(1<<30)
> > +#define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
> > +#define   ADPA_PIPE_SEL_SHIFT_CPT	29
> > +#define   ADPA_PIPE_SEL_MASK_CPT	(3<<29)
> > +#define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
> >  #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
> >  #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
> >  #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
> > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> > index de0e22322c76..211d601cd1b1 100644
> > --- a/drivers/gpu/drm/i915/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/intel_crt.c
> > @@ -63,33 +63,35 @@ static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
> >  	return intel_encoder_to_crt(intel_attached_encoder(connector));
> >  }
> >  
> > +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> > +			    i915_reg_t adpa_reg, enum pipe *pipe)
> > +{
> > +	u32 val;
> > +
> > +	val = I915_READ(adpa_reg);
> > +
> > +	/* asserts want to know the pipe even if the port is disabled */
> > +	if (HAS_PCH_CPT(dev_priv))
> > +		*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
> > +	else
> > +		*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
> > +
> > +	return val & ADPA_DAC_ENABLE;
> > +}
> > +
> >  static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> >  				   enum pipe *pipe)
> >  {
> > -	struct drm_device *dev = encoder->base.dev;
> > -	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	struct intel_crt *crt = intel_encoder_to_crt(encoder);
> > -	u32 tmp;
> >  	bool ret;
> >  
> >  	if (!intel_display_power_get_if_enabled(dev_priv,
> >  						encoder->power_domain))
> >  		return false;
> >  
> > -	ret = false;
> > -
> > -	tmp = I915_READ(crt->adpa_reg);
> > -
> > -	if (!(tmp & ADPA_DAC_ENABLE))
> > -		goto out;
> > +	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
> >  
> > -	if (HAS_PCH_CPT(dev_priv))
> > -		*pipe = PORT_TO_PIPE_CPT(tmp);
> > -	else
> > -		*pipe = PORT_TO_PIPE(tmp);
> > -
> > -	ret = true;
> > -out:
> >  	intel_display_power_put(dev_priv, encoder->power_domain);
> >  
> >  	return ret;
> > @@ -168,11 +170,9 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> >  	if (HAS_PCH_LPT(dev_priv))
> >  		; /* Those bits don't exist here */
> >  	else if (HAS_PCH_CPT(dev_priv))
> > -		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
> > -	else if (crtc->pipe == 0)
> > -		adpa |= ADPA_PIPE_A_SELECT;
> > +		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
> >  	else
> > -		adpa |= ADPA_PIPE_B_SELECT;
> > +		adpa |= ADPA_PIPE_SEL(crtc->pipe);
> >  
> >  	if (!HAS_PCH_SPLIT(dev_priv))
> >  		I915_WRITE(BCLRPAT(crtc->pipe), 0);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ad588d564198..6daa8d97a0aa 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1360,21 +1360,6 @@ static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
> >  	return true;
> >  }
> >  
> > -static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
> > -			      enum pipe pipe, u32 val)
> > -{
> > -	if ((val & ADPA_DAC_ENABLE) == 0)
> > -		return false;
> > -	if (HAS_PCH_CPT(dev_priv)) {
> > -		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
> > -			return false;
> > -	} else {
> > -		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
> > -			return false;
> > -	}
> > -	return true;
> > -}
> > -
> >  static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
> >  				   enum pipe pipe, i915_reg_t reg,
> >  				   u32 port_sel)
> > @@ -1405,16 +1390,17 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> >  static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> >  				      enum pipe pipe)
> >  {
> > +	enum pipe port_pipe;
> >  	u32 val;
> >  
> >  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
> >  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
> >  	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
> >  
> > -	val = I915_READ(PCH_ADPA);
> > -	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
> > -	     "PCH VGA enabled on transcoder %c, should be disabled\n",
> > -	     pipe_name(pipe));
> > +	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
> > +			port_pipe == pipe,
> > +			"PCH VGA enabled on transcoder %c, should be disabled\n",
> > +			pipe_name(pipe));
> >  
> >  	val = I915_READ(PCH_LVDS);
> >  	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index d7dbca1aabff..423795050970 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1377,6 +1377,8 @@ void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
> >  void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
> >  
> >  /* intel_crt.c */
> > +bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> > +			    i915_reg_t adpa_reg, enum pipe *pipe);
> >  void intel_crt_init(struct drm_i915_private *dev_priv);
> >  void intel_crt_reset(struct drm_encoder *encoder);
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f11bb213ec07..ae3c26216996 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4133,11 +4133,12 @@  enum {
 
 #define   ADPA_DAC_ENABLE	(1<<31)
 #define   ADPA_DAC_DISABLE	0
-#define   ADPA_PIPE_SELECT_MASK	(1<<30)
-#define   ADPA_PIPE_A_SELECT	0
-#define   ADPA_PIPE_B_SELECT	(1<<30)
-#define   ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
-/* CPT uses bits 29:30 for pch transcoder select */
+#define   ADPA_PIPE_SEL_SHIFT		30
+#define   ADPA_PIPE_SEL_MASK		(1<<30)
+#define   ADPA_PIPE_SEL(pipe)		((pipe) << 30)
+#define   ADPA_PIPE_SEL_SHIFT_CPT	29
+#define   ADPA_PIPE_SEL_MASK_CPT	(3<<29)
+#define   ADPA_PIPE_SEL_CPT(pipe)	((pipe) << 29)
 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0<<24)
 #define   ADPA_CRT_HOTPLUG_MONITOR_MASK  (3<<24)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index de0e22322c76..211d601cd1b1 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -63,33 +63,35 @@  static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
 	return intel_encoder_to_crt(intel_attached_encoder(connector));
 }
 
+bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+			    i915_reg_t adpa_reg, enum pipe *pipe)
+{
+	u32 val;
+
+	val = I915_READ(adpa_reg);
+
+	/* asserts want to know the pipe even if the port is disabled */
+	if (HAS_PCH_CPT(dev_priv))
+		*pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
+	else
+		*pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
+
+	return val & ADPA_DAC_ENABLE;
+}
+
 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
 				   enum pipe *pipe)
 {
-	struct drm_device *dev = encoder->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crt *crt = intel_encoder_to_crt(encoder);
-	u32 tmp;
 	bool ret;
 
 	if (!intel_display_power_get_if_enabled(dev_priv,
 						encoder->power_domain))
 		return false;
 
-	ret = false;
-
-	tmp = I915_READ(crt->adpa_reg);
-
-	if (!(tmp & ADPA_DAC_ENABLE))
-		goto out;
+	ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 
-	if (HAS_PCH_CPT(dev_priv))
-		*pipe = PORT_TO_PIPE_CPT(tmp);
-	else
-		*pipe = PORT_TO_PIPE(tmp);
-
-	ret = true;
-out:
 	intel_display_power_put(dev_priv, encoder->power_domain);
 
 	return ret;
@@ -168,11 +170,9 @@  static void intel_crt_set_dpms(struct intel_encoder *encoder,
 	if (HAS_PCH_LPT(dev_priv))
 		; /* Those bits don't exist here */
 	else if (HAS_PCH_CPT(dev_priv))
-		adpa |= PORT_TRANS_SEL_CPT(crtc->pipe);
-	else if (crtc->pipe == 0)
-		adpa |= ADPA_PIPE_A_SELECT;
+		adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 	else
-		adpa |= ADPA_PIPE_B_SELECT;
+		adpa |= ADPA_PIPE_SEL(crtc->pipe);
 
 	if (!HAS_PCH_SPLIT(dev_priv))
 		I915_WRITE(BCLRPAT(crtc->pipe), 0);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ad588d564198..6daa8d97a0aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1360,21 +1360,6 @@  static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
 	return true;
 }
 
-static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
-			      enum pipe pipe, u32 val)
-{
-	if ((val & ADPA_DAC_ENABLE) == 0)
-		return false;
-	if (HAS_PCH_CPT(dev_priv)) {
-		if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
-			return false;
-	} else {
-		if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
-			return false;
-	}
-	return true;
-}
-
 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
 				   enum pipe pipe, i915_reg_t reg,
 				   u32 port_sel)
@@ -1405,16 +1390,17 @@  static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
 				      enum pipe pipe)
 {
+	enum pipe port_pipe;
 	u32 val;
 
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
 	assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
 
-	val = I915_READ(PCH_ADPA);
-	I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
-	     "PCH VGA enabled on transcoder %c, should be disabled\n",
-	     pipe_name(pipe));
+	I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&
+			port_pipe == pipe,
+			"PCH VGA enabled on transcoder %c, should be disabled\n",
+			pipe_name(pipe));
 
 	val = I915_READ(PCH_LVDS);
 	I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d7dbca1aabff..423795050970 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1377,6 +1377,8 @@  void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
 
 /* intel_crt.c */
+bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+			    i915_reg_t adpa_reg, enum pipe *pipe);
 void intel_crt_init(struct drm_i915_private *dev_priv);
 void intel_crt_reset(struct drm_encoder *encoder);