| Message ID | 20180709162222.28125-1-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: > Instead of defining all registers twice, define just a PCH_GPIO_BASE > that has the same address as PCH_GPIO_A and use that to calculate all > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing > the same thing. > > This also rewrites the GMBUS[05] registers since they depend on > gpio_mmio_base. > > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() > macro to return a particular gpio address and move the enum out of > i915_reg.h (suggested by Jani) > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- > 4 files changed, 52 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > index e39492aaff6c..e25a74fe753b 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, > gmbus_mmio_write); > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); > > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 0424e45f88db..f8f71d577613 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { > /* > * GPIO regs > */ > -#define GPIOA _MMIO(0x5010) > -#define GPIOB _MMIO(0x5014) > -#define GPIOC _MMIO(0x5018) > -#define GPIOD _MMIO(0x501c) > -#define GPIOE _MMIO(0x5020) > -#define GPIOF _MMIO(0x5024) > -#define GPIOG _MMIO(0x5028) > -#define GPIOH _MMIO(0x502c) > -#define GPIOJ _MMIO(0x5034) > -#define GPIOK _MMIO(0x5038) > -#define GPIOL _MMIO(0x503C) > -#define GPIOM _MMIO(0x5040) > +#define GPIO_OFFSET 0x5010u > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) This is a rather peculiar choice of baseline address. I'd either go with 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). Only needs a slight adjustment to your GPIO macro, but avoids the rather onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda indicates your offset is all confused. Anyway, just a drive-by comment, I was looking for some other gmbus patch. -Daniel > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio)) > + > # define GPIO_CLOCK_DIR_MASK (1 << 0) > # define GPIO_CLOCK_DIR_IN (0 << 1) > # define GPIO_CLOCK_DIR_OUT (1 << 1) > @@ -3115,7 +3108,11 @@ enum i915_power_well_id { > # define GPIO_DATA_VAL_IN (1 << 12) > # define GPIO_DATA_PULLUP_DISABLE (1 << 13) > > -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ > +#define GMBUS_OFFSET 0x5100u > + > +/* clock/port select */ > +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET) > #define GMBUS_AKSV_SELECT (1 << 11) > #define GMBUS_RATE_100KHZ (0 << 8) > #define GMBUS_RATE_50KHZ (1 << 8) > @@ -3141,7 +3138,10 @@ enum i915_power_well_id { > #define GMBUS_PIN_12_TC4_ICP 12 > > #define GMBUS_NUM_PINS 13 /* including 0 */ > -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ > + > +/* command/status */ > +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET + 0x4) > #define GMBUS_SW_CLR_INT (1 << 31) > #define GMBUS_SW_RDY (1 << 30) > #define GMBUS_ENT (1 << 29) /* enable timeout */ > @@ -3155,7 +3155,10 @@ enum i915_power_well_id { > #define GMBUS_SLAVE_ADDR_SHIFT 1 > #define GMBUS_SLAVE_READ (1 << 0) > #define GMBUS_SLAVE_WRITE (0 << 0) > -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ > + > +/* status */ > +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET + 0x8) > #define GMBUS_INUSE (1 << 15) > #define GMBUS_HW_WAIT_PHASE (1 << 14) > #define GMBUS_STALL_TIMEOUT (1 << 13) > @@ -3163,14 +3166,21 @@ enum i915_power_well_id { > #define GMBUS_HW_RDY (1 << 11) > #define GMBUS_SATOER (1 << 10) > #define GMBUS_ACTIVE (1 << 9) > -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ > -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ > + > +/* data buffer bytes 3-0 */ > +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET + 0xc) > +/* interrupt mask (Pineview+) */ > +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET + 0x10) > #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) > #define GMBUS_NAK_EN (1 << 3) > #define GMBUS_IDLE_EN (1 << 2) > #define GMBUS_HW_WAIT_EN (1 << 1) > #define GMBUS_HW_RDY_EN (1 << 0) > -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ > +/* byte index */ > +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > + + GMBUS_OFFSET + 0x20) > #define GMBUS_2BYTE_INDEX_EN (1 << 31) > > /* > @@ -7668,13 +7678,6 @@ enum { > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) > > -#define PCH_GPIOA _MMIO(0xc5010) > -#define PCH_GPIOB _MMIO(0xc5014) > -#define PCH_GPIOC _MMIO(0xc5018) > -#define PCH_GPIOD _MMIO(0xc501c) > -#define PCH_GPIOE _MMIO(0xc5020) > -#define PCH_GPIOF _MMIO(0xc5024) > - > #define PCH_GMBUS0 _MMIO(0xc5100) > #define PCH_GMBUS1 _MMIO(0xc5104) > #define PCH_GMBUS2 _MMIO(0xc5108) > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 61e715ddd0d5..dedf87c58a95 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -152,6 +152,22 @@ > * Display related stuff > */ > > +enum i915_gpio { > + GPIOA = 0, > + GPIOB, > + GPIOC, > + GPIOD, > + GPIOE, > + GPIOF, > + GPIOG, > + GPIOH, > + __GPIOI_UNUSED, > + GPIOJ, > + GPIOK, > + GPIOL, > + GPIOM, > +}; > + > /* store information about an Ixxx DVO */ > /* The i830->i865 use multiple DVOs with multiple i2cs */ > /* the i915, i945 have a single sDVO i2c bus - which is different */ > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index 97606c1be70d..f1c0b974daa6 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -37,7 +37,7 @@ > > struct gmbus_pin { > const char *name; > - i915_reg_t reg; > + enum i915_gpio gpio; > }; > > /* Map gmbus pin pairs to names and registers. */ > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, > else > size = ARRAY_SIZE(gmbus_pins); > > - return pin < size && > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); > + return pin < size && get_gmbus_pin(dev_priv, pin)->name; > } > > /* Intel GPIO access functions */ > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) > > algo = &bus->bit_algo; > > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); > bus->adapter.algo_data = algo; > algo->setsda = set_data; > algo->setscl = set_clock; > @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) > return 0; > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; > + dev_priv->gpio_mmio_base = VLV_GPIO_BASE; > else if (!HAS_GMCH_DISPLAY(dev_priv)) > - dev_priv->gpio_mmio_base = > - i915_mmio_reg_offset(PCH_GPIOA) - > - i915_mmio_reg_offset(GPIOA); > + dev_priv->gpio_mmio_base = PCH_GPIO_BASE; > + else > + dev_priv->gpio_mmio_base = GPIO_OFFSET; > > mutex_init(&dev_priv->gmbus_mutex); > init_waitqueue_head(&dev_priv->gmbus_wait_queue); > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote: > On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: > > Instead of defining all registers twice, define just a PCH_GPIO_BASE > > that has the same address as PCH_GPIO_A and use that to calculate all > > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing > > the same thing. > > > > This also rewrites the GMBUS[05] registers since they depend on > > gpio_mmio_base. > > > > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() > > macro to return a particular gpio address and move the enum out of > > i915_reg.h (suggested by Jani) > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- > > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ > > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- > > 4 files changed, 52 insertions(+), 35 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > > index e39492aaff6c..e25a74fe753b 100644 > > --- a/drivers/gpu/drm/i915/gvt/handlers.c > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > > > > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, > > gmbus_mmio_write); > > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); > > > > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 0424e45f88db..f8f71d577613 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { > > /* > > * GPIO regs > > */ > > -#define GPIOA _MMIO(0x5010) > > -#define GPIOB _MMIO(0x5014) > > -#define GPIOC _MMIO(0x5018) > > -#define GPIOD _MMIO(0x501c) > > -#define GPIOE _MMIO(0x5020) > > -#define GPIOF _MMIO(0x5024) > > -#define GPIOG _MMIO(0x5028) > > -#define GPIOH _MMIO(0x502c) > > -#define GPIOJ _MMIO(0x5034) > > -#define GPIOK _MMIO(0x5038) > > -#define GPIOL _MMIO(0x503C) > > -#define GPIOM _MMIO(0x5040) > > +#define GPIO_OFFSET 0x5010u > > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) > > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) > > This is a rather peculiar choice of baseline address. I'd either go with > 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). I'm all for a round 0x50000 number, however it doesn't match the spec. I don't understand how 0x0 would make sense here. Are you suggesting to embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE? #define GPIO_OFFSET 0x5010u /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */ #define PCH_GPIO_BASE 0xc0000u #define VLV_GPIO_BASE VLV_DISPLAY_BASE #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio)) That would make sense, but I don't think it's a better option due to GPIO_BASE now and mmio_gpio_base matching nothing in the spec (and the extra add on every gpio). > Only needs a slight adjustment to your GPIO macro, but avoids the rather > onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda > indicates your offset is all confused. well.. this is only because there I'm actually interested in the vlv display / pch offset. The subtraction is done so I don't have to store a gmbus_mmio_base and can rather work it out from the gpio one. Lucas De Marchi > > Anyway, just a drive-by comment, I was looking for some other gmbus patch. > -Daniel > > > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio)) > > + > > # define GPIO_CLOCK_DIR_MASK (1 << 0) > > # define GPIO_CLOCK_DIR_IN (0 << 1) > > # define GPIO_CLOCK_DIR_OUT (1 << 1) > > @@ -3115,7 +3108,11 @@ enum i915_power_well_id { > > # define GPIO_DATA_VAL_IN (1 << 12) > > # define GPIO_DATA_PULLUP_DISABLE (1 << 13) > > > > -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ > > +#define GMBUS_OFFSET 0x5100u > > + > > +/* clock/port select */ > > +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET) > > #define GMBUS_AKSV_SELECT (1 << 11) > > #define GMBUS_RATE_100KHZ (0 << 8) > > #define GMBUS_RATE_50KHZ (1 << 8) > > @@ -3141,7 +3138,10 @@ enum i915_power_well_id { > > #define GMBUS_PIN_12_TC4_ICP 12 > > > > #define GMBUS_NUM_PINS 13 /* including 0 */ > > -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ > > + > > +/* command/status */ > > +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET + 0x4) > > #define GMBUS_SW_CLR_INT (1 << 31) > > #define GMBUS_SW_RDY (1 << 30) > > #define GMBUS_ENT (1 << 29) /* enable timeout */ > > @@ -3155,7 +3155,10 @@ enum i915_power_well_id { > > #define GMBUS_SLAVE_ADDR_SHIFT 1 > > #define GMBUS_SLAVE_READ (1 << 0) > > #define GMBUS_SLAVE_WRITE (0 << 0) > > -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ > > + > > +/* status */ > > +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET + 0x8) > > #define GMBUS_INUSE (1 << 15) > > #define GMBUS_HW_WAIT_PHASE (1 << 14) > > #define GMBUS_STALL_TIMEOUT (1 << 13) > > @@ -3163,14 +3166,21 @@ enum i915_power_well_id { > > #define GMBUS_HW_RDY (1 << 11) > > #define GMBUS_SATOER (1 << 10) > > #define GMBUS_ACTIVE (1 << 9) > > -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ > > -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ > > + > > +/* data buffer bytes 3-0 */ > > +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET + 0xc) > > +/* interrupt mask (Pineview+) */ > > +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET + 0x10) > > #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) > > #define GMBUS_NAK_EN (1 << 3) > > #define GMBUS_IDLE_EN (1 << 2) > > #define GMBUS_HW_WAIT_EN (1 << 1) > > #define GMBUS_HW_RDY_EN (1 << 0) > > -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ > > +/* byte index */ > > +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ > > + + GMBUS_OFFSET + 0x20) > > #define GMBUS_2BYTE_INDEX_EN (1 << 31) > > > > /* > > @@ -7668,13 +7678,6 @@ enum { > > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) > > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) > > > > -#define PCH_GPIOA _MMIO(0xc5010) > > -#define PCH_GPIOB _MMIO(0xc5014) > > -#define PCH_GPIOC _MMIO(0xc5018) > > -#define PCH_GPIOD _MMIO(0xc501c) > > -#define PCH_GPIOE _MMIO(0xc5020) > > -#define PCH_GPIOF _MMIO(0xc5024) > > - > > #define PCH_GMBUS0 _MMIO(0xc5100) > > #define PCH_GMBUS1 _MMIO(0xc5104) > > #define PCH_GMBUS2 _MMIO(0xc5108) > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > > index 61e715ddd0d5..dedf87c58a95 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -152,6 +152,22 @@ > > * Display related stuff > > */ > > > > +enum i915_gpio { > > + GPIOA = 0, > > + GPIOB, > > + GPIOC, > > + GPIOD, > > + GPIOE, > > + GPIOF, > > + GPIOG, > > + GPIOH, > > + __GPIOI_UNUSED, > > + GPIOJ, > > + GPIOK, > > + GPIOL, > > + GPIOM, > > +}; > > + > > /* store information about an Ixxx DVO */ > > /* The i830->i865 use multiple DVOs with multiple i2cs */ > > /* the i915, i945 have a single sDVO i2c bus - which is different */ > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > > index 97606c1be70d..f1c0b974daa6 100644 > > --- a/drivers/gpu/drm/i915/intel_i2c.c > > +++ b/drivers/gpu/drm/i915/intel_i2c.c > > @@ -37,7 +37,7 @@ > > > > struct gmbus_pin { > > const char *name; > > - i915_reg_t reg; > > + enum i915_gpio gpio; > > }; > > > > /* Map gmbus pin pairs to names and registers. */ > > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, > > else > > size = ARRAY_SIZE(gmbus_pins); > > > > - return pin < size && > > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); > > + return pin < size && get_gmbus_pin(dev_priv, pin)->name; > > } > > > > /* Intel GPIO access functions */ > > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) > > > > algo = &bus->bit_algo; > > > > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + > > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); > > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); > > bus->adapter.algo_data = algo; > > algo->setsda = set_data; > > algo->setscl = set_clock; > > @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) > > return 0; > > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > > - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; > > + dev_priv->gpio_mmio_base = VLV_GPIO_BASE; > > else if (!HAS_GMCH_DISPLAY(dev_priv)) > > - dev_priv->gpio_mmio_base = > > - i915_mmio_reg_offset(PCH_GPIOA) - > > - i915_mmio_reg_offset(GPIOA); > > + dev_priv->gpio_mmio_base = PCH_GPIO_BASE; > > + else > > + dev_priv->gpio_mmio_base = GPIO_OFFSET; > > > > mutex_init(&dev_priv->gmbus_mutex); > > init_waitqueue_head(&dev_priv->gmbus_wait_queue); > > -- > > 2.17.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi <lucas.de.marchi@gmail.com> wrote: > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote: >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE >> > that has the same address as PCH_GPIO_A and use that to calculate all >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing >> > the same thing. >> > >> > This also rewrites the GMBUS[05] registers since they depend on >> > gpio_mmio_base. >> > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() >> > macro to return a particular gpio address and move the enum out of >> > i915_reg.h (suggested by Jani) >> > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> > --- >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- >> > 4 files changed, 52 insertions(+), 35 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c >> > index e39492aaff6c..e25a74fe753b 100644 >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) >> > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, >> > gmbus_mmio_write); >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); >> > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > index 0424e45f88db..f8f71d577613 100644 >> > --- a/drivers/gpu/drm/i915/i915_reg.h >> > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { >> > /* >> > * GPIO regs >> > */ >> > -#define GPIOA _MMIO(0x5010) >> > -#define GPIOB _MMIO(0x5014) >> > -#define GPIOC _MMIO(0x5018) >> > -#define GPIOD _MMIO(0x501c) >> > -#define GPIOE _MMIO(0x5020) >> > -#define GPIOF _MMIO(0x5024) >> > -#define GPIOG _MMIO(0x5028) >> > -#define GPIOH _MMIO(0x502c) >> > -#define GPIOJ _MMIO(0x5034) >> > -#define GPIOK _MMIO(0x5038) >> > -#define GPIOL _MMIO(0x503C) >> > -#define GPIOM _MMIO(0x5040) >> > +#define GPIO_OFFSET 0x5010u >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) >> >> This is a rather peculiar choice of baseline address. I'd either go with >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). > > I'm all for a round 0x50000 number, however it doesn't match the spec. > I don't understand how 0x0 would make sense here. Are you suggesting to > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE? > > #define GPIO_OFFSET 0x5010u > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */ > #define PCH_GPIO_BASE 0xc0000u > #define VLV_GPIO_BASE VLV_DISPLAY_BASE > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio)) Yeah that's what I had in mind. > That would make sense, but I don't think it's a better option due to > GPIO_BASE now and mmio_gpio_base matching nothing in the spec (and the > extra add on every gpio). > >> Only needs a slight adjustment to your GPIO macro, but avoids the rather >> onerous - GPIO_OFFSET + GMBUS_OFFSET you have below. That one kinda >> indicates your offset is all confused. > > well.. this is only because there I'm actually interested in the vlv > display / pch offset. The subtraction is done so I don't have to store > a gmbus_mmio_base and can rather work it out from the gpio one. If you want to stick with your approach, at least extract the common ->gpio_mmio_base - GPIO_OFFSET + GMBUS_OFFSET computation into a GMBUS_BASE(dev) macro or something like that. I think that would be a good solution too. Either approach has my a-b (I'll be on vacations next 3 weeks to probably no r-b from me). -Daniel > > Lucas De Marchi > >> >> Anyway, just a drive-by comment, I was looking for some other gmbus patch. >> -Daniel >> >> > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio)) >> > + >> > # define GPIO_CLOCK_DIR_MASK (1 << 0) >> > # define GPIO_CLOCK_DIR_IN (0 << 1) >> > # define GPIO_CLOCK_DIR_OUT (1 << 1) >> > @@ -3115,7 +3108,11 @@ enum i915_power_well_id { >> > # define GPIO_DATA_VAL_IN (1 << 12) >> > # define GPIO_DATA_PULLUP_DISABLE (1 << 13) >> > >> > -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ >> > +#define GMBUS_OFFSET 0x5100u >> > + >> > +/* clock/port select */ >> > +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET) >> > #define GMBUS_AKSV_SELECT (1 << 11) >> > #define GMBUS_RATE_100KHZ (0 << 8) >> > #define GMBUS_RATE_50KHZ (1 << 8) >> > @@ -3141,7 +3138,10 @@ enum i915_power_well_id { >> > #define GMBUS_PIN_12_TC4_ICP 12 >> > >> > #define GMBUS_NUM_PINS 13 /* including 0 */ >> > -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ >> > + >> > +/* command/status */ >> > +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET + 0x4) >> > #define GMBUS_SW_CLR_INT (1 << 31) >> > #define GMBUS_SW_RDY (1 << 30) >> > #define GMBUS_ENT (1 << 29) /* enable timeout */ >> > @@ -3155,7 +3155,10 @@ enum i915_power_well_id { >> > #define GMBUS_SLAVE_ADDR_SHIFT 1 >> > #define GMBUS_SLAVE_READ (1 << 0) >> > #define GMBUS_SLAVE_WRITE (0 << 0) >> > -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ >> > + >> > +/* status */ >> > +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET + 0x8) >> > #define GMBUS_INUSE (1 << 15) >> > #define GMBUS_HW_WAIT_PHASE (1 << 14) >> > #define GMBUS_STALL_TIMEOUT (1 << 13) >> > @@ -3163,14 +3166,21 @@ enum i915_power_well_id { >> > #define GMBUS_HW_RDY (1 << 11) >> > #define GMBUS_SATOER (1 << 10) >> > #define GMBUS_ACTIVE (1 << 9) >> > -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ >> > -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ >> > + >> > +/* data buffer bytes 3-0 */ >> > +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET + 0xc) >> > +/* interrupt mask (Pineview+) */ >> > +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET + 0x10) >> > #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) >> > #define GMBUS_NAK_EN (1 << 3) >> > #define GMBUS_IDLE_EN (1 << 2) >> > #define GMBUS_HW_WAIT_EN (1 << 1) >> > #define GMBUS_HW_RDY_EN (1 << 0) >> > -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ >> > +/* byte index */ >> > +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ >> > + + GMBUS_OFFSET + 0x20) >> > #define GMBUS_2BYTE_INDEX_EN (1 << 31) >> > >> > /* >> > @@ -7668,13 +7678,6 @@ enum { >> > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) >> > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) >> > >> > -#define PCH_GPIOA _MMIO(0xc5010) >> > -#define PCH_GPIOB _MMIO(0xc5014) >> > -#define PCH_GPIOC _MMIO(0xc5018) >> > -#define PCH_GPIOD _MMIO(0xc501c) >> > -#define PCH_GPIOE _MMIO(0xc5020) >> > -#define PCH_GPIOF _MMIO(0xc5024) >> > - >> > #define PCH_GMBUS0 _MMIO(0xc5100) >> > #define PCH_GMBUS1 _MMIO(0xc5104) >> > #define PCH_GMBUS2 _MMIO(0xc5108) >> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> > index 61e715ddd0d5..dedf87c58a95 100644 >> > --- a/drivers/gpu/drm/i915/intel_drv.h >> > +++ b/drivers/gpu/drm/i915/intel_drv.h >> > @@ -152,6 +152,22 @@ >> > * Display related stuff >> > */ >> > >> > +enum i915_gpio { >> > + GPIOA = 0, >> > + GPIOB, >> > + GPIOC, >> > + GPIOD, >> > + GPIOE, >> > + GPIOF, >> > + GPIOG, >> > + GPIOH, >> > + __GPIOI_UNUSED, >> > + GPIOJ, >> > + GPIOK, >> > + GPIOL, >> > + GPIOM, >> > +}; >> > + >> > /* store information about an Ixxx DVO */ >> > /* The i830->i865 use multiple DVOs with multiple i2cs */ >> > /* the i915, i945 have a single sDVO i2c bus - which is different */ >> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c >> > index 97606c1be70d..f1c0b974daa6 100644 >> > --- a/drivers/gpu/drm/i915/intel_i2c.c >> > +++ b/drivers/gpu/drm/i915/intel_i2c.c >> > @@ -37,7 +37,7 @@ >> > >> > struct gmbus_pin { >> > const char *name; >> > - i915_reg_t reg; >> > + enum i915_gpio gpio; >> > }; >> > >> > /* Map gmbus pin pairs to names and registers. */ >> > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, >> > else >> > size = ARRAY_SIZE(gmbus_pins); >> > >> > - return pin < size && >> > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); >> > + return pin < size && get_gmbus_pin(dev_priv, pin)->name; >> > } >> > >> > /* Intel GPIO access functions */ >> > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) >> > >> > algo = &bus->bit_algo; >> > >> > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + >> > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); >> > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); >> > bus->adapter.algo_data = algo; >> > algo->setsda = set_data; >> > algo->setscl = set_clock; >> > @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) >> > return 0; >> > >> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) >> > - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; >> > + dev_priv->gpio_mmio_base = VLV_GPIO_BASE; >> > else if (!HAS_GMCH_DISPLAY(dev_priv)) >> > - dev_priv->gpio_mmio_base = >> > - i915_mmio_reg_offset(PCH_GPIOA) - >> > - i915_mmio_reg_offset(GPIOA); >> > + dev_priv->gpio_mmio_base = PCH_GPIO_BASE; >> > + else >> > + dev_priv->gpio_mmio_base = GPIO_OFFSET; >> > >> > mutex_init(&dev_priv->gmbus_mutex); >> > init_waitqueue_head(&dev_priv->gmbus_wait_queue); >> > -- >> > 2.17.1 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >> -- >> Daniel Vetter >> Software Engineer, Intel Corporation >> http://blog.ffwll.ch >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote: > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi > <lucas.de.marchi@gmail.com> wrote: > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote: > >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: > >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE > >> > that has the same address as PCH_GPIO_A and use that to calculate all > >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing > >> > the same thing. > >> > > >> > This also rewrites the GMBUS[05] registers since they depend on > >> > gpio_mmio_base. > >> > > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() > >> > macro to return a particular gpio address and move the enum out of > >> > i915_reg.h (suggested by Jani) > >> > > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > >> > --- > >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- > >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ > >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- > >> > 4 files changed, 52 insertions(+), 35 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > >> > index e39492aaff6c..e25a74fe753b 100644 > >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c > >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > >> > > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, > >> > gmbus_mmio_write); > >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); > >> > > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> > index 0424e45f88db..f8f71d577613 100644 > >> > --- a/drivers/gpu/drm/i915/i915_reg.h > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h > >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { > >> > /* > >> > * GPIO regs > >> > */ > >> > -#define GPIOA _MMIO(0x5010) > >> > -#define GPIOB _MMIO(0x5014) > >> > -#define GPIOC _MMIO(0x5018) > >> > -#define GPIOD _MMIO(0x501c) > >> > -#define GPIOE _MMIO(0x5020) > >> > -#define GPIOF _MMIO(0x5024) > >> > -#define GPIOG _MMIO(0x5028) > >> > -#define GPIOH _MMIO(0x502c) > >> > -#define GPIOJ _MMIO(0x5034) > >> > -#define GPIOK _MMIO(0x5038) > >> > -#define GPIOL _MMIO(0x503C) > >> > -#define GPIOM _MMIO(0x5040) > >> > +#define GPIO_OFFSET 0x5010u > >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) > >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) > >> > >> This is a rather peculiar choice of baseline address. I'd either go with > >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). > > > > I'm all for a round 0x50000 number, however it doesn't match the spec. > > I don't understand how 0x0 would make sense here. Are you suggesting to > > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE? > > > > #define GPIO_OFFSET 0x5010u > > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */ > > #define PCH_GPIO_BASE 0xc0000u > > #define VLV_GPIO_BASE VLV_DISPLAY_BASE > > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio)) > > Yeah that's what I had in mind. I think I like this one the most. Keeps the 0x5010 in the GPIO() macro so less confusion when looking it up in the spec (except on PCH platforms perhaps). Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something like that. I've occasionally pondered about some kind of generic south_display_base thing that could maybe cover all the things that live on the PCH side on those platforms. But I never bothered to look at all the register offsets hard enough to figure out whether it'd be actually useful.
On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote: > On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote: > > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi > > <lucas.de.marchi@gmail.com> wrote: > > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote: > > >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: > > >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE > > >> > that has the same address as PCH_GPIO_A and use that to calculate all > > >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing > > >> > the same thing. > > >> > > > >> > This also rewrites the GMBUS[05] registers since they depend on > > >> > gpio_mmio_base. > > >> > > > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() > > >> > macro to return a particular gpio address and move the enum out of > > >> > i915_reg.h (suggested by Jani) > > >> > > > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > >> > --- > > >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- > > >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ > > >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- > > >> > 4 files changed, 52 insertions(+), 35 deletions(-) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > > >> > index e39492aaff6c..e25a74fe753b 100644 > > >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c > > >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > > >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > > >> > > > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, > > >> > gmbus_mmio_write); > > >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); > > >> > > > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, > > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > >> > index 0424e45f88db..f8f71d577613 100644 > > >> > --- a/drivers/gpu/drm/i915/i915_reg.h > > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h > > >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { > > >> > /* > > >> > * GPIO regs > > >> > */ > > >> > -#define GPIOA _MMIO(0x5010) > > >> > -#define GPIOB _MMIO(0x5014) > > >> > -#define GPIOC _MMIO(0x5018) > > >> > -#define GPIOD _MMIO(0x501c) > > >> > -#define GPIOE _MMIO(0x5020) > > >> > -#define GPIOF _MMIO(0x5024) > > >> > -#define GPIOG _MMIO(0x5028) > > >> > -#define GPIOH _MMIO(0x502c) > > >> > -#define GPIOJ _MMIO(0x5034) > > >> > -#define GPIOK _MMIO(0x5038) > > >> > -#define GPIOL _MMIO(0x503C) > > >> > -#define GPIOM _MMIO(0x5040) > > >> > +#define GPIO_OFFSET 0x5010u > > >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) > > >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) > > >> > > >> This is a rather peculiar choice of baseline address. I'd either go with > > >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). > > > > > > I'm all for a round 0x50000 number, however it doesn't match the spec. > > > I don't understand how 0x0 would make sense here. Are you suggesting to > > > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE? > > > > > > #define GPIO_OFFSET 0x5010u > > > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */ > > > #define PCH_GPIO_BASE 0xc0000u > > > #define VLV_GPIO_BASE VLV_DISPLAY_BASE > > > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio)) > > > > Yeah that's what I had in mind. > > I think I like this one the most. Keeps the 0x5010 in the GPIO() macro > so less confusion when looking it up in the spec (except on PCH platforms > perhaps). > > Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and > just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something > like that. > > I've occasionally pondered about some kind of generic south_display_base > thing that could maybe cover all the things that live on the PCH side on > those platforms. But I never bothered to look at all the register offsets > hard enough to figure out whether it'd be actually useful. Problem with a generic south_display_base is that some things moved between south and north block. So not sure the generic south_display_base would actually be all that useful. -Daniel
n Fri, Jul 13, 2018 at 10:48:02AM +0200, Daniel Vetter wrote: > On Thu, Jul 12, 2018 at 08:23:05PM +0300, Ville Syrjälä wrote: > > On Thu, Jul 12, 2018 at 07:03:58PM +0200, Daniel Vetter wrote: > > > On Thu, Jul 12, 2018 at 6:24 PM, Lucas De Marchi > > > <lucas.de.marchi@gmail.com> wrote: > > > > On Thu, Jul 12, 2018 at 05:04:03PM +0200, Daniel Vetter wrote: > > > >> On Mon, Jul 09, 2018 at 09:22:21AM -0700, Lucas De Marchi wrote: > > > >> > Instead of defining all registers twice, define just a PCH_GPIO_BASE > > > >> > that has the same address as PCH_GPIO_A and use that to calculate all > > > >> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing > > > >> > the same thing. > > > >> > > > > >> > This also rewrites the GMBUS[05] registers since they depend on > > > >> > gpio_mmio_base. > > > >> > > > > >> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO() > > > >> > macro to return a particular gpio address and move the enum out of > > > >> > i915_reg.h (suggested by Jani) > > > >> > > > > >> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > >> > --- > > > >> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > > >> > drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- > > > >> > drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ > > > >> > drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- > > > >> > 4 files changed, 52 insertions(+), 35 deletions(-) > > > >> > > > > >> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c > > > >> > index e39492aaff6c..e25a74fe753b 100644 > > > >> > --- a/drivers/gpu/drm/i915/gvt/handlers.c > > > >> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > > > >> > @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > > > >> > > > > >> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, > > > >> > gmbus_mmio_write); > > > >> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > > >> > + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); > > > >> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); > > > >> > > > > >> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, > > > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > > >> > index 0424e45f88db..f8f71d577613 100644 > > > >> > --- a/drivers/gpu/drm/i915/i915_reg.h > > > >> > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > >> > @@ -3088,18 +3088,11 @@ enum i915_power_well_id { > > > >> > /* > > > >> > * GPIO regs > > > >> > */ > > > >> > -#define GPIOA _MMIO(0x5010) > > > >> > -#define GPIOB _MMIO(0x5014) > > > >> > -#define GPIOC _MMIO(0x5018) > > > >> > -#define GPIOD _MMIO(0x501c) > > > >> > -#define GPIOE _MMIO(0x5020) > > > >> > -#define GPIOF _MMIO(0x5024) > > > >> > -#define GPIOG _MMIO(0x5028) > > > >> > -#define GPIOH _MMIO(0x502c) > > > >> > -#define GPIOJ _MMIO(0x5034) > > > >> > -#define GPIOK _MMIO(0x5038) > > > >> > -#define GPIOL _MMIO(0x503C) > > > >> > -#define GPIOM _MMIO(0x5040) > > > >> > +#define GPIO_OFFSET 0x5010u > > > >> > +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) > > > >> > +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) > > > >> > > > >> This is a rather peculiar choice of baseline address. I'd either go with > > > >> 0x5000u or 0x0000u (which avoids the need to change all the gmbus macros). > > > > > > > > I'm all for a round 0x50000 number, however it doesn't match the spec. > > > > I don't understand how 0x0 would make sense here. Are you suggesting to > > > > embed the GPIO_OFFSET into the GPIO macro and get rid of the GPIO_BASE? > > > > > > > > #define GPIO_OFFSET 0x5010u > > > > /* THESE 2 BELOW COULD USE ANOTHER BETTER NAME */ > > > > #define PCH_GPIO_BASE 0xc0000u > > > > #define VLV_GPIO_BASE VLV_DISPLAY_BASE > > > > #define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + 4 * (gpio)) > > > > > > Yeah that's what I had in mind. > > > > I think I like this one the most. Keeps the 0x5010 in the GPIO() macro > > so less confusion when looking it up in the spec (except on PCH platforms > > perhaps). > > > > Also I would drop the VLV_GPIO_BASE and PCH_GPIO_BASE definitions and > > just do gpio_mmio_Base = VLV_DISPLAY_BASE/PCH_DISPLAY_BASE or something > > like that. > > > > I've occasionally pondered about some kind of generic south_display_base > > thing that could maybe cover all the things that live on the PCH side on > > those platforms. But I never bothered to look at all the register offsets > > hard enough to figure out whether it'd be actually useful. > > Problem with a generic south_display_base is that some things moved > between south and north block. So not sure the generic south_display_base > would actually be all that useful. Yeah. And of course there are things like backlight that lives on both sides of the divide on some platforms.
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index e39492aaff6c..e25a74fe753b 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, gmbus_mmio_write); - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); + MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL); MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0424e45f88db..f8f71d577613 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3088,18 +3088,11 @@ enum i915_power_well_id { /* * GPIO regs */ -#define GPIOA _MMIO(0x5010) -#define GPIOB _MMIO(0x5014) -#define GPIOC _MMIO(0x5018) -#define GPIOD _MMIO(0x501c) -#define GPIOE _MMIO(0x5020) -#define GPIOF _MMIO(0x5024) -#define GPIOG _MMIO(0x5028) -#define GPIOH _MMIO(0x502c) -#define GPIOJ _MMIO(0x5034) -#define GPIOK _MMIO(0x5038) -#define GPIOL _MMIO(0x503C) -#define GPIOM _MMIO(0x5040) +#define GPIO_OFFSET 0x5010u +#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET) +#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET) +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio)) + # define GPIO_CLOCK_DIR_MASK (1 << 0) # define GPIO_CLOCK_DIR_IN (0 << 1) # define GPIO_CLOCK_DIR_OUT (1 << 1) @@ -3115,7 +3108,11 @@ enum i915_power_well_id { # define GPIO_DATA_VAL_IN (1 << 12) # define GPIO_DATA_PULLUP_DISABLE (1 << 13) -#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */ +#define GMBUS_OFFSET 0x5100u + +/* clock/port select */ +#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET) #define GMBUS_AKSV_SELECT (1 << 11) #define GMBUS_RATE_100KHZ (0 << 8) #define GMBUS_RATE_50KHZ (1 << 8) @@ -3141,7 +3138,10 @@ enum i915_power_well_id { #define GMBUS_PIN_12_TC4_ICP 12 #define GMBUS_NUM_PINS 13 /* including 0 */ -#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */ + +/* command/status */ +#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET + 0x4) #define GMBUS_SW_CLR_INT (1 << 31) #define GMBUS_SW_RDY (1 << 30) #define GMBUS_ENT (1 << 29) /* enable timeout */ @@ -3155,7 +3155,10 @@ enum i915_power_well_id { #define GMBUS_SLAVE_ADDR_SHIFT 1 #define GMBUS_SLAVE_READ (1 << 0) #define GMBUS_SLAVE_WRITE (0 << 0) -#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */ + +/* status */ +#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET + 0x8) #define GMBUS_INUSE (1 << 15) #define GMBUS_HW_WAIT_PHASE (1 << 14) #define GMBUS_STALL_TIMEOUT (1 << 13) @@ -3163,14 +3166,21 @@ enum i915_power_well_id { #define GMBUS_HW_RDY (1 << 11) #define GMBUS_SATOER (1 << 10) #define GMBUS_ACTIVE (1 << 9) -#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */ -#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */ + +/* data buffer bytes 3-0 */ +#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET + 0xc) +/* interrupt mask (Pineview+) */ +#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET + 0x10) #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) #define GMBUS_NAK_EN (1 << 3) #define GMBUS_IDLE_EN (1 << 2) #define GMBUS_HW_WAIT_EN (1 << 1) #define GMBUS_HW_RDY_EN (1 << 0) -#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */ +/* byte index */ +#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \ + + GMBUS_OFFSET + 0x20) #define GMBUS_2BYTE_INDEX_EN (1 << 31) /* @@ -7668,13 +7678,6 @@ enum { #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4) #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4) -#define PCH_GPIOA _MMIO(0xc5010) -#define PCH_GPIOB _MMIO(0xc5014) -#define PCH_GPIOC _MMIO(0xc5018) -#define PCH_GPIOD _MMIO(0xc501c) -#define PCH_GPIOE _MMIO(0xc5020) -#define PCH_GPIOF _MMIO(0xc5024) - #define PCH_GMBUS0 _MMIO(0xc5100) #define PCH_GMBUS1 _MMIO(0xc5104) #define PCH_GMBUS2 _MMIO(0xc5108) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 61e715ddd0d5..dedf87c58a95 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -152,6 +152,22 @@ * Display related stuff */ +enum i915_gpio { + GPIOA = 0, + GPIOB, + GPIOC, + GPIOD, + GPIOE, + GPIOF, + GPIOG, + GPIOH, + __GPIOI_UNUSED, + GPIOJ, + GPIOK, + GPIOL, + GPIOM, +}; + /* store information about an Ixxx DVO */ /* The i830->i865 use multiple DVOs with multiple i2cs */ /* the i915, i945 have a single sDVO i2c bus - which is different */ diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 97606c1be70d..f1c0b974daa6 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -37,7 +37,7 @@ struct gmbus_pin { const char *name; - i915_reg_t reg; + enum i915_gpio gpio; }; /* Map gmbus pin pairs to names and registers. */ @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, else size = ARRAY_SIZE(gmbus_pins); - return pin < size && - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); + return pin < size && get_gmbus_pin(dev_priv, pin)->name; } /* Intel GPIO access functions */ @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) algo = &bus->bit_algo; - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); bus->adapter.algo_data = algo; algo->setsda = set_data; algo->setscl = set_clock; @@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv) return 0; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; + dev_priv->gpio_mmio_base = VLV_GPIO_BASE; else if (!HAS_GMCH_DISPLAY(dev_priv)) - dev_priv->gpio_mmio_base = - i915_mmio_reg_offset(PCH_GPIOA) - - i915_mmio_reg_offset(GPIOA); + dev_priv->gpio_mmio_base = PCH_GPIO_BASE; + else + dev_priv->gpio_mmio_base = GPIO_OFFSET; mutex_init(&dev_priv->gmbus_mutex); init_waitqueue_head(&dev_priv->gmbus_wait_queue);
Instead of defining all registers twice, define just a PCH_GPIO_BASE that has the same address as PCH_GPIO_A and use that to calculate all the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing the same thing. This also rewrites the GMBUS[05] registers since they depend on gpio_mmio_base. v2: Fix GMBUS registers to be relative to gpio base; create GPIO() macro to return a particular gpio address and move the enum out of i915_reg.h (suggested by Jani) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++-------------- drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++ drivers/gpu/drm/i915/intel_i2c.c | 16 ++++----- 4 files changed, 52 insertions(+), 35 deletions(-)