| Message ID | 175a491f-a827-4a92-1884-2f1490d38a52@cogentembedded.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | bcee502ceb6c0dcbc7ccd460ed7040c3d6998c3e |
| Delegated to: | Simon Horman |
| Headers | show |
On Fri, Jul 20, 2018 at 10:21:45PM +0300, Sergei Shtylyov wrote: > Describe RWDT in the R8A77980 SoC device tree. > > Enable RWDT on the Condor and V3H Starter Kit boards. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's > 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches > (adding the RWDT clock) in order to work... But it is safe to apply without those patches, right? Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
On 07/23/2018 07:08 PM, Simon Horman wrote: >> Describe RWDT in the R8A77980 SoC device tree. >> >> Enable RWDT on the Condor and V3H Starter Kit boards. >> >> Based on the original (and large) patch by Vladimir Barinov. >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> >> --- >> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's >> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches >> (adding the RWDT clock) in order to work... > > But it is safe to apply without those patches, right? The RWDT driver should just fail to probe with -ENOENT. > Reviewed-by: Simon Horman <horms+renesas@verge.net.au> TY! MBR, Sergei
On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > Describe RWDT in the R8A77980 SoC device tree. > > Enable RWDT on the Condor and V3H Starter Kit boards. > > Based on the original (and large) patch by Vladimir Barinov. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -262,6 +262,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -191,6 +191,11 @@ }; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi =================================================================== --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -118,6 +118,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a77980-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77980", "renesas,rcar-gen3-gpio";