| Message ID | 1542007730-47284-7-git-send-email-chi-hsien.lin@cypress.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Kalle Valo |
| Headers | show |
| Series | brcmfmac: chip related changes | expand |
On 11/12/2018 8:29 AM, Chi-Hsien Lin wrote: > From: Naveen Gupta <naveen.gupta@cypress.com> > > The number of words that the read FIFO has to contain except > the end of frame before sends data back to the host. > Max watermark = (512B - 2* (BurstLength))/4 = > (512 - 128)/4 = 384/4 = 0x60 > so if burst length (i.e. BurstLength = 64) is increased, > watermark has to be reduced. This is the optimal setting for this chip. > > Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com> > Signed-off-by: Naveen Gupta <naveen.gupta@cypress.com> > Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com> > --- > drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c > index 7707b0169c21..e1708e297d07 100644 > --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c > +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c > @@ -52,6 +52,7 @@ > /* watermark expressed in number of words */ > #define DEFAULT_F2_WATERMARK 0x8 > #define CY_4373_F2_WATERMARK 0x40 > +#define CY_43012_F2_WATERMARK 0x60 So basically you increase queuing in firmware rx path. How does this affect TCP latency. The DMA error obviously needs fixing, but why go from a watermark of 32 bytes to the maximum of 384 bytes. Same question for 4373. Regards, Arend
(+Madhan) On 11/12/2018 5:25, Arend van Spriel wrote: > On 11/12/2018 8:29 AM, Chi-Hsien Lin wrote: >> From: Naveen Gupta <naveen.gupta@cypress.com> >> >> The number of words that the read FIFO has to contain except >> the end of frame before sends data back to the host. >> Max watermark = (512B - 2* (BurstLength))/4 = >> (512 - 128)/4 = 384/4 = 0x60 >> so if burst length (i.e. BurstLength = 64) is increased, >> watermark has to be reduced. This is the optimal setting for this chip. >> >> Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com> >> Signed-off-by: Naveen Gupta <naveen.gupta@cypress.com> >> Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com> >> --- >> drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c | 12 >> ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c >> b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c >> index 7707b0169c21..e1708e297d07 100644 >> --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c >> +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c >> @@ -52,6 +52,7 @@ >> /* watermark expressed in number of words */ >> #define DEFAULT_F2_WATERMARK 0x8 >> #define CY_4373_F2_WATERMARK 0x40 >> +#define CY_43012_F2_WATERMARK 0x60 > > So basically you increase queuing in firmware rx path. How does this > affect TCP latency. The DMA error obviously needs fixing, but why go > from a watermark of 32 bytes to the maximum of 384 bytes. Same question > for 4373. This is to answer 2/8 and 6/8 - For current chips like 4373 and 43012, we are configuring F2 block size as 256 and it is recommended to program the F2 watermark (SDIO TX path - SDIO Device to host traffic) to at least equal or greater than the block size to make sure that at least >= 1 Block size of data is in FIFO before sending on the SDIO bus to avoid underflow. We haven't observed excess TCP latency with this setting. Regards, Chi-hsien Lin > > Regards, > Arend
diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c index 7707b0169c21..e1708e297d07 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c @@ -52,6 +52,7 @@ /* watermark expressed in number of words */ #define DEFAULT_F2_WATERMARK 0x8 #define CY_4373_F2_WATERMARK 0x40 +#define CY_43012_F2_WATERMARK 0x60 #ifdef DEBUG @@ -4173,6 +4174,17 @@ static void brcmf_sdio_firmware_callback(struct device *dev, int err, CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB, &err); break; + case SDIO_DEVICE_ID_CYPRESS_43012: + brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", + CY_43012_F2_WATERMARK); + brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, + CY_43012_F2_WATERMARK, &err); + devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, + &err); + devctl |= SBSDIO_DEVCTL_F2WM_ENAB; + brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, + &err); + break; default: brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, DEFAULT_F2_WATERMARK, &err);