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[for-next] iw_cxgb4: Check for send WR also while posting write with completion WR

Message ID 20181221073048.14554-1-bharat@chelsio.com (mailing list archive)
State Superseded
Headers show
Series [for-next] iw_cxgb4: Check for send WR also while posting write with completion WR | expand

Commit Message

Potnuri Bharat Teja Dec. 21, 2018, 7:30 a.m. UTC 
Post a Write with completion for WRITE WR + SEND WR combination as well.

Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
Reviewed-by: Steve Wise <swise@opengridcomputing.com>
---
 drivers/infiniband/hw/cxgb4/qp.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

Comments

Jason Gunthorpe Dec. 21, 2018, 7:07 p.m. UTC | #1 
On Fri, Dec 21, 2018 at 01:00:48PM +0530, Potnuri Bharat Teja wrote:
> Post a Write with completion for WRITE WR + SEND WR combination as well.
> 
> Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
> Reviewed-by: Steve Wise <swise@opengridcomputing.com>
> ---
>  drivers/infiniband/hw/cxgb4/qp.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)

Is this a bug fix? Should there be a fixes line? The commit message is
very uninformative, and the patch looks like it is bug fixing the send
with invalidate support..

Jason
Potnuri Bharat Teja Dec. 24, 2018, 3:16 p.m. UTC | #2 
On Saturday, December 12/22/18, 2018 at 00:37:25 +0530, Jason Gunthorpe wrote:
> On Fri, Dec 21, 2018 at 01:00:48PM +0530, Potnuri Bharat Teja wrote:
> > Post a Write with completion for WRITE WR + SEND WR combination as well.
> > 
> > Signed-off-by: Potnuri Bharat Teja <bharat@chelsio.com>
> > Reviewed-by: Steve Wise <swise@opengridcomputing.com>
> > ---
> >  drivers/infiniband/hw/cxgb4/qp.c | 19 +++++++++++++------
> >  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> Is this a bug fix? Should there be a fixes line? The commit message is
No, this is not a bug fix, this is just an extension to the earlier added 
write with completion WR.
> very uninformative, and the patch looks like it is bug fixing the send
> with invalidate support..
Sorry for the bad description. sending out a v2.
> 
> Jason
diff mbox series

Patch

diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index 5a8030bd4208..c9b42f0bbb64 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -632,7 +632,10 @@  static void build_rdma_write_cmpl(struct t4_sq *sq,
 
 	wcwr->stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
 	wcwr->to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
-	wcwr->stag_inv = cpu_to_be32(wr->next->ex.invalidate_rkey);
+	if (wr->next->opcode == IB_WR_SEND)
+		wcwr->stag_inv = 0;
+	else
+		wcwr->stag_inv = cpu_to_be32(wr->next->ex.invalidate_rkey);
 	wcwr->r2 = 0;
 	wcwr->r3 = 0;
 
@@ -726,7 +729,10 @@  static void post_write_cmpl(struct c4iw_qp *qhp, const struct ib_send_wr *wr)
 
 	/* SEND_WITH_INV swsqe */
 	swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
-	swsqe->opcode = FW_RI_SEND_WITH_INV;
+	if (wr->next->opcode == IB_WR_SEND)
+		swsqe->opcode = FW_RI_SEND;
+	else
+		swsqe->opcode = FW_RI_SEND_WITH_INV;
 	swsqe->idx = qhp->wq.sq.pidx;
 	swsqe->complete = 0;
 	swsqe->signaled = send_signaled;
@@ -1133,9 +1139,9 @@  int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 	/*
 	 * Fastpath for NVMe-oF target WRITE + SEND_WITH_INV wr chain which is
 	 * the response for small NVMEe-oF READ requests.  If the chain is
-	 * exactly a WRITE->SEND_WITH_INV and the sgl depths and lengths
-	 * meet the requirements of the fw_ri_write_cmpl_wr work request,
-	 * then build and post the write_cmpl WR.  If any of the tests
+	 * exactly a WRITE->SEND_WITH_INV or a WRITE->SEND and the sgl depths
+	 * and lengths meet the requirements of the fw_ri_write_cmpl_wr work
+	 * request, then build and post the write_cmpl WR. If any of the tests
 	 * below are not true, then we continue on with the tradtional WRITE
 	 * and SEND WRs.
 	 */
@@ -1145,7 +1151,8 @@  int c4iw_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 	    wr && wr->next && !wr->next->next &&
 	    wr->opcode == IB_WR_RDMA_WRITE &&
 	    wr->sg_list[0].length && wr->num_sge <= T4_WRITE_CMPL_MAX_SGL &&
-	    wr->next->opcode == IB_WR_SEND_WITH_INV &&
+	    (wr->next->opcode == IB_WR_SEND ||
+	    wr->next->opcode == IB_WR_SEND_WITH_INV) &&
 	    wr->next->sg_list[0].length == T4_WRITE_CMPL_MAX_CQE &&
 	    wr->next->num_sge == 1 && num_wrs >= 2) {
 		post_write_cmpl(qhp, wr);