diff mbox series

[PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions

Message ID 1547553668-4359-1-git-send-email-ykaneko0929@gmail.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series [PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add DRIF pins, groups and functions | expand

Commit Message

Yoshihiro Kaneko Jan. 15, 2019, 12:01 p.m. UTC 
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---

This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.

 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 255 +++++++++++++++++++++++++++++++++-
 1 file changed, 253 insertions(+), 2 deletions(-)

Comments

Geert Uytterhoeven Jan. 16, 2019, 4:38 p.m. UTC | #1 
Hi Kaneko-san,

On Tue, Jan 15, 2019 at 1:01 PM Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990
> SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>

Thanks for your patch!

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c

> @@ -3523,7 +3716,7 @@ enum {
>  };
>
>  static const struct {
> -       struct sh_pfc_pin_group common[241];
> +       struct sh_pfc_pin_group common[262];
>         struct sh_pfc_pin_group automotive[2];
>  } pinmux_groups = {
>         .common = {
> @@ -3555,6 +3748,27 @@ enum {
>                 SH_PFC_PIN_GROUP(can0_data),
>                 SH_PFC_PIN_GROUP(can1_data),
>                 SH_PFC_PIN_GROUP(can_clk),
> +               SH_PFC_PIN_GROUP(drif0_ctrl_a),
> +               SH_PFC_PIN_GROUP(drif0_data0_a),
> +               SH_PFC_PIN_GROUP(drif0_data1_a),
> +               SH_PFC_PIN_GROUP(drif0_ctrl_b),
> +               SH_PFC_PIN_GROUP(drif0_data0_b),
> +               SH_PFC_PIN_GROUP(drif0_data1_b),
> +               SH_PFC_PIN_GROUP(drif1_ctrl),
> +               SH_PFC_PIN_GROUP(drif1_data0),
> +               SH_PFC_PIN_GROUP(drif1_data1),
> +               SH_PFC_PIN_GROUP(drif2_ctrl_a),
> +               SH_PFC_PIN_GROUP(drif2_data0_a),
> +               SH_PFC_PIN_GROUP(drif2_data1_a),
> +               SH_PFC_PIN_GROUP(drif2_ctrl_b),
> +               SH_PFC_PIN_GROUP(drif2_data0_b),
> +               SH_PFC_PIN_GROUP(drif2_data1_b),
> +               SH_PFC_PIN_GROUP(drif3_ctrl_a),
> +               SH_PFC_PIN_GROUP(drif3_data0_a),
> +               SH_PFC_PIN_GROUP(drif3_data1_a),
> +               SH_PFC_PIN_GROUP(drif3_ctrl_b),
> +               SH_PFC_PIN_GROUP(drif3_data0_b),
> +               SH_PFC_PIN_GROUP(drif3_data1_b),

As RZ/G2E (r8a774c0) does not have the DRIF modules, the DRIF pin groups
should be added to the automotive section, instead of the common section.

>                 SH_PFC_PIN_GROUP(du_rgb666),
>                 SH_PFC_PIN_GROUP(du_rgb888),
>                 SH_PFC_PIN_GROUP(du_clk_in_0),

> @@ -4157,7 +4404,7 @@ enum {
>  };
>
>  static const struct {
> -       struct sh_pfc_function common[44];
> +       struct sh_pfc_function common[48];
>         struct sh_pfc_function automotive[2];
>  } pinmux_functions = {
>         .common = {
> @@ -4166,6 +4413,10 @@ enum {
>                 SH_PFC_FUNCTION(can0),
>                 SH_PFC_FUNCTION(can1),
>                 SH_PFC_FUNCTION(can_clk),
> +               SH_PFC_FUNCTION(drif0),
> +               SH_PFC_FUNCTION(drif1),
> +               SH_PFC_FUNCTION(drif2),
> +               SH_PFC_FUNCTION(drif3),

Likewise for the DRIF pin functions.

>                 SH_PFC_FUNCTION(du),
>                 SH_PFC_FUNCTION(hscif0),
>                 SH_PFC_FUNCTION(hscif1),

The rest looks good to me, so with the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert
Yoshihiro Kaneko Jan. 24, 2019, 5:26 p.m. UTC | #2 
Hi Geert-san,

Thanks for your review!

2019年1月17日(木) 1:38 Geert Uytterhoeven <geert@linux-m68k.org>:
>
> Hi Kaneko-san,
>
> On Tue, Jan 15, 2019 at 1:01 PM Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > This patch adds DRIF{0,1,2,3} pins, groups and functions to the R8A77990
> > SoC.
> >
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
> > @@ -3523,7 +3716,7 @@ enum {
> >  };
> >
> >  static const struct {
> > -       struct sh_pfc_pin_group common[241];
> > +       struct sh_pfc_pin_group common[262];
> >         struct sh_pfc_pin_group automotive[2];
> >  } pinmux_groups = {
> >         .common = {
> > @@ -3555,6 +3748,27 @@ enum {
> >                 SH_PFC_PIN_GROUP(can0_data),
> >                 SH_PFC_PIN_GROUP(can1_data),
> >                 SH_PFC_PIN_GROUP(can_clk),
> > +               SH_PFC_PIN_GROUP(drif0_ctrl_a),
> > +               SH_PFC_PIN_GROUP(drif0_data0_a),
> > +               SH_PFC_PIN_GROUP(drif0_data1_a),
> > +               SH_PFC_PIN_GROUP(drif0_ctrl_b),
> > +               SH_PFC_PIN_GROUP(drif0_data0_b),
> > +               SH_PFC_PIN_GROUP(drif0_data1_b),
> > +               SH_PFC_PIN_GROUP(drif1_ctrl),
> > +               SH_PFC_PIN_GROUP(drif1_data0),
> > +               SH_PFC_PIN_GROUP(drif1_data1),
> > +               SH_PFC_PIN_GROUP(drif2_ctrl_a),
> > +               SH_PFC_PIN_GROUP(drif2_data0_a),
> > +               SH_PFC_PIN_GROUP(drif2_data1_a),
> > +               SH_PFC_PIN_GROUP(drif2_ctrl_b),
> > +               SH_PFC_PIN_GROUP(drif2_data0_b),
> > +               SH_PFC_PIN_GROUP(drif2_data1_b),
> > +               SH_PFC_PIN_GROUP(drif3_ctrl_a),
> > +               SH_PFC_PIN_GROUP(drif3_data0_a),
> > +               SH_PFC_PIN_GROUP(drif3_data1_a),
> > +               SH_PFC_PIN_GROUP(drif3_ctrl_b),
> > +               SH_PFC_PIN_GROUP(drif3_data0_b),
> > +               SH_PFC_PIN_GROUP(drif3_data1_b),
>
> As RZ/G2E (r8a774c0) does not have the DRIF modules, the DRIF pin groups
> should be added to the automotive section, instead of the common section.

I will do that.

>
> >                 SH_PFC_PIN_GROUP(du_rgb666),
> >                 SH_PFC_PIN_GROUP(du_rgb888),
> >                 SH_PFC_PIN_GROUP(du_clk_in_0),
>
> > @@ -4157,7 +4404,7 @@ enum {
> >  };
> >
> >  static const struct {
> > -       struct sh_pfc_function common[44];
> > +       struct sh_pfc_function common[48];
> >         struct sh_pfc_function automotive[2];
> >  } pinmux_functions = {
> >         .common = {
> > @@ -4166,6 +4413,10 @@ enum {
> >                 SH_PFC_FUNCTION(can0),
> >                 SH_PFC_FUNCTION(can1),
> >                 SH_PFC_FUNCTION(can_clk),
> > +               SH_PFC_FUNCTION(drif0),
> > +               SH_PFC_FUNCTION(drif1),
> > +               SH_PFC_FUNCTION(drif2),
> > +               SH_PFC_FUNCTION(drif3),
>
> Likewise for the DRIF pin functions.

Likewise.

>
> >                 SH_PFC_FUNCTION(du),
> >                 SH_PFC_FUNCTION(hscif0),
> >                 SH_PFC_FUNCTION(hscif1),
>
> The rest looks good to me, so with the above fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

Best regards,
Kaneko
diff mbox series

Patch

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index e40908d..5fc50f4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1586,6 +1586,199 @@  enum {
 	CANFD1_TX_MARK, CANFD1_RX_MARK,
 };
 
+/* - DRIF0 --------------------------------------------------------------- */
+static const unsigned int drif0_ctrl_a_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
+};
+
+static const unsigned int drif0_ctrl_a_mux[] = {
+	RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
+};
+
+static const unsigned int drif0_data0_a_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(5, 17),
+};
+
+static const unsigned int drif0_data0_a_mux[] = {
+	RIF0_D0_A_MARK,
+};
+
+static const unsigned int drif0_data1_a_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(5, 18),
+};
+
+static const unsigned int drif0_data1_a_mux[] = {
+	RIF0_D1_A_MARK,
+};
+
+static const unsigned int drif0_ctrl_b_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
+};
+
+static const unsigned int drif0_ctrl_b_mux[] = {
+	RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
+};
+
+static const unsigned int drif0_data0_b_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(3, 13),
+};
+
+static const unsigned int drif0_data0_b_mux[] = {
+	RIF0_D0_B_MARK,
+};
+
+static const unsigned int drif0_data1_b_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(3, 14),
+};
+
+static const unsigned int drif0_data1_b_mux[] = {
+	RIF0_D1_B_MARK,
+};
+
+/* - DRIF1 --------------------------------------------------------------- */
+static const unsigned int drif1_ctrl_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
+};
+
+static const unsigned int drif1_ctrl_mux[] = {
+	RIF1_CLK_MARK, RIF1_SYNC_MARK,
+};
+
+static const unsigned int drif1_data0_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int drif1_data0_mux[] = {
+	RIF1_D0_MARK,
+};
+
+static const unsigned int drif1_data1_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(5, 3),
+};
+
+static const unsigned int drif1_data1_mux[] = {
+	RIF1_D1_MARK,
+};
+
+/* - DRIF2 --------------------------------------------------------------- */
+static const unsigned int drif2_ctrl_a_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
+};
+
+static const unsigned int drif2_ctrl_a_mux[] = {
+	RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
+};
+
+static const unsigned int drif2_data0_a_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(2, 8),
+};
+
+static const unsigned int drif2_data0_a_mux[] = {
+	RIF2_D0_A_MARK,
+};
+
+static const unsigned int drif2_data1_a_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int drif2_data1_a_mux[] = {
+	RIF2_D1_A_MARK,
+};
+
+static const unsigned int drif2_ctrl_b_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
+};
+
+static const unsigned int drif2_ctrl_b_mux[] = {
+	RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
+};
+
+static const unsigned int drif2_data0_b_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(1, 6),
+};
+
+static const unsigned int drif2_data0_b_mux[] = {
+	RIF2_D0_B_MARK,
+};
+
+static const unsigned int drif2_data1_b_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(1, 7),
+};
+
+static const unsigned int drif2_data1_b_mux[] = {
+	RIF2_D1_B_MARK,
+};
+
+/* - DRIF3 --------------------------------------------------------------- */
+static const unsigned int drif3_ctrl_a_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int drif3_ctrl_a_mux[] = {
+	RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
+};
+
+static const unsigned int drif3_data0_a_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(2, 12),
+};
+
+static const unsigned int drif3_data0_a_mux[] = {
+	RIF3_D0_A_MARK,
+};
+
+static const unsigned int drif3_data1_a_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(2, 13),
+};
+
+static const unsigned int drif3_data1_a_mux[] = {
+	RIF3_D1_A_MARK,
+};
+
+static const unsigned int drif3_ctrl_b_pins[] = {
+	/* CLK, SYNC */
+	RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
+};
+
+static const unsigned int drif3_ctrl_b_mux[] = {
+	RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
+};
+
+static const unsigned int drif3_data0_b_pins[] = {
+	/* D0 */
+	RCAR_GP_PIN(0, 10),
+};
+
+static const unsigned int drif3_data0_b_mux[] = {
+	RIF3_D0_B_MARK,
+};
+
+static const unsigned int drif3_data1_b_pins[] = {
+	/* D1 */
+	RCAR_GP_PIN(0, 11),
+};
+
+static const unsigned int drif3_data1_b_mux[] = {
+	RIF3_D1_B_MARK,
+};
+
 /* - DU --------------------------------------------------------------------- */
 static const unsigned int du_rgb666_pins[] = {
 	/* R[7:2], G[7:2], B[7:2] */
@@ -3523,7 +3716,7 @@  enum {
 };
 
 static const struct {
-	struct sh_pfc_pin_group common[241];
+	struct sh_pfc_pin_group common[262];
 	struct sh_pfc_pin_group automotive[2];
 } pinmux_groups = {
 	.common = {
@@ -3555,6 +3748,27 @@  enum {
 		SH_PFC_PIN_GROUP(can0_data),
 		SH_PFC_PIN_GROUP(can1_data),
 		SH_PFC_PIN_GROUP(can_clk),
+		SH_PFC_PIN_GROUP(drif0_ctrl_a),
+		SH_PFC_PIN_GROUP(drif0_data0_a),
+		SH_PFC_PIN_GROUP(drif0_data1_a),
+		SH_PFC_PIN_GROUP(drif0_ctrl_b),
+		SH_PFC_PIN_GROUP(drif0_data0_b),
+		SH_PFC_PIN_GROUP(drif0_data1_b),
+		SH_PFC_PIN_GROUP(drif1_ctrl),
+		SH_PFC_PIN_GROUP(drif1_data0),
+		SH_PFC_PIN_GROUP(drif1_data1),
+		SH_PFC_PIN_GROUP(drif2_ctrl_a),
+		SH_PFC_PIN_GROUP(drif2_data0_a),
+		SH_PFC_PIN_GROUP(drif2_data1_a),
+		SH_PFC_PIN_GROUP(drif2_ctrl_b),
+		SH_PFC_PIN_GROUP(drif2_data0_b),
+		SH_PFC_PIN_GROUP(drif2_data1_b),
+		SH_PFC_PIN_GROUP(drif3_ctrl_a),
+		SH_PFC_PIN_GROUP(drif3_data0_a),
+		SH_PFC_PIN_GROUP(drif3_data1_a),
+		SH_PFC_PIN_GROUP(drif3_ctrl_b),
+		SH_PFC_PIN_GROUP(drif3_data0_b),
+		SH_PFC_PIN_GROUP(drif3_data1_b),
 		SH_PFC_PIN_GROUP(du_rgb666),
 		SH_PFC_PIN_GROUP(du_rgb888),
 		SH_PFC_PIN_GROUP(du_clk_in_0),
@@ -3826,6 +4040,39 @@  enum {
 	"canfd1_data",
 };
 
+static const char * const drif0_groups[] = {
+	"drif0_ctrl_a",
+	"drif0_data0_a",
+	"drif0_data1_a",
+	"drif0_ctrl_b",
+	"drif0_data0_b",
+	"drif0_data1_b",
+};
+
+static const char * const drif1_groups[] = {
+	"drif1_ctrl",
+	"drif1_data0",
+	"drif1_data1",
+};
+
+static const char * const drif2_groups[] = {
+	"drif2_ctrl_a",
+	"drif2_data0_a",
+	"drif2_data1_a",
+	"drif2_ctrl_b",
+	"drif2_data0_b",
+	"drif2_data1_b",
+};
+
+static const char * const drif3_groups[] = {
+	"drif3_ctrl_a",
+	"drif3_data0_a",
+	"drif3_data1_a",
+	"drif3_ctrl_b",
+	"drif3_data0_b",
+	"drif3_data1_b",
+};
+
 static const char * const du_groups[] = {
 	"du_rgb666",
 	"du_rgb888",
@@ -4157,7 +4404,7 @@  enum {
 };
 
 static const struct {
-	struct sh_pfc_function common[44];
+	struct sh_pfc_function common[48];
 	struct sh_pfc_function automotive[2];
 } pinmux_functions = {
 	.common = {
@@ -4166,6 +4413,10 @@  enum {
 		SH_PFC_FUNCTION(can0),
 		SH_PFC_FUNCTION(can1),
 		SH_PFC_FUNCTION(can_clk),
+		SH_PFC_FUNCTION(drif0),
+		SH_PFC_FUNCTION(drif1),
+		SH_PFC_FUNCTION(drif2),
+		SH_PFC_FUNCTION(drif3),
 		SH_PFC_FUNCTION(du),
 		SH_PFC_FUNCTION(hscif0),
 		SH_PFC_FUNCTION(hscif1),