diff mbox series

[v3,6/8] drm/i915: Bump gen7+ fb size limits to 16kx16k

Message ID 20190118152720.24643-7-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: GTT remapping for display | expand

Commit Message

Ville Syrjälä Jan. 18, 2019, 3:27 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

With gtt remapping in place we can use arbitrarily large
framebuffers. Let's bump the limits to 16kx16k on gen7+.
The limit was chosen to match the maximum 2D surface size
of the 3D engine.

With the remapping we could easily go higher than that for the
display engine. However the modesetting ddx will blindly assume
it can handle whatever is reported via kms. The oversized
buffer dimensions are not caught by glamor nor Mesa until
finally an assert will trip when genxml attempts to pack the
SURFACE_STATE. So we pick a safe limit to avoid the X server
from crashing (or potentially misbehaving if the genxml asserts
are compiled out).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

Comments

Daniel Vetter Jan. 30, 2019, 10:01 a.m. UTC | #1 
On Fri, Jan 18, 2019 at 05:27:18PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> With gtt remapping in place we can use arbitrarily large
> framebuffers. Let's bump the limits to 16kx16k on gen7+.
> The limit was chosen to match the maximum 2D surface size
> of the 3D engine.
> 
> With the remapping we could easily go higher than that for the
> display engine. However the modesetting ddx will blindly assume
> it can handle whatever is reported via kms. The oversized
> buffer dimensions are not caught by glamor nor Mesa until
> finally an assert will trip when genxml attempts to pack the
> SURFACE_STATE. So we pick a safe limit to avoid the X server
> from crashing (or potentially misbehaving if the genxml asserts
> are compiled out).

So -modesetting is still fireworks on gen3, which has 4k x 4k buffer
limit, but 2k x 2k render limit? I thought the tiled rendering stuff
landed ...

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Matches my mesa here.

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f7c4456220cd..4053ed93e73c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15366,16 +15366,22 @@ int intel_modeset_init(struct drm_device *dev)
>  		}
>  	}
>  
> -	/* maximum framebuffer dimensions */
> -	if (IS_GEN(dev_priv, 2)) {
> -		dev->mode_config.max_width = 2048;
> -		dev->mode_config.max_height = 2048;
> +	/*
> +	 * Maximum framebuffer dimensions, chosen to match
> +	 * the maximum render engine surface size on gen4+.
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 7) {
> +		dev->mode_config.max_width = 16384;
> +		dev->mode_config.max_height = 16384;
> +	} else if (INTEL_GEN(dev_priv) >= 4) {
> +		dev->mode_config.max_width = 8192;
> +		dev->mode_config.max_height = 8192;
>  	} else if (IS_GEN(dev_priv, 3)) {
>  		dev->mode_config.max_width = 4096;
>  		dev->mode_config.max_height = 4096;
>  	} else {
> -		dev->mode_config.max_width = 8192;
> -		dev->mode_config.max_height = 8192;
> +		dev->mode_config.max_width = 2048;
> +		dev->mode_config.max_height = 2048;
>  	}
>  
>  	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> -- 
> 2.19.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Ville Syrjälä Jan. 30, 2019, 2:35 p.m. UTC | #2 
On Wed, Jan 30, 2019 at 11:01:50AM +0100, Daniel Vetter wrote:
> On Fri, Jan 18, 2019 at 05:27:18PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > With gtt remapping in place we can use arbitrarily large
> > framebuffers. Let's bump the limits to 16kx16k on gen7+.
> > The limit was chosen to match the maximum 2D surface size
> > of the 3D engine.
> > 
> > With the remapping we could easily go higher than that for the
> > display engine. However the modesetting ddx will blindly assume
> > it can handle whatever is reported via kms. The oversized
> > buffer dimensions are not caught by glamor nor Mesa until
> > finally an assert will trip when genxml attempts to pack the
> > SURFACE_STATE. So we pick a safe limit to avoid the X server
> > from crashing (or potentially misbehaving if the genxml asserts
> > are compiled out).
> 
> So -modesetting is still fireworks on gen3, which has 4k x 4k buffer
> limit, but 2k x 2k render limit?

Not sure. Does anyone seriously expect -modesetting to work with
gen3? I've never even tried it myself.

> I thought the tiled rendering stuff
> landed ...
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Matches my mesa here.
> 
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++------
> >  1 file changed, 12 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index f7c4456220cd..4053ed93e73c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15366,16 +15366,22 @@ int intel_modeset_init(struct drm_device *dev)
> >  		}
> >  	}
> >  
> > -	/* maximum framebuffer dimensions */
> > -	if (IS_GEN(dev_priv, 2)) {
> > -		dev->mode_config.max_width = 2048;
> > -		dev->mode_config.max_height = 2048;
> > +	/*
> > +	 * Maximum framebuffer dimensions, chosen to match
> > +	 * the maximum render engine surface size on gen4+.
> > +	 */
> > +	if (INTEL_GEN(dev_priv) >= 7) {
> > +		dev->mode_config.max_width = 16384;
> > +		dev->mode_config.max_height = 16384;
> > +	} else if (INTEL_GEN(dev_priv) >= 4) {
> > +		dev->mode_config.max_width = 8192;
> > +		dev->mode_config.max_height = 8192;
> >  	} else if (IS_GEN(dev_priv, 3)) {
> >  		dev->mode_config.max_width = 4096;
> >  		dev->mode_config.max_height = 4096;
> >  	} else {
> > -		dev->mode_config.max_width = 8192;
> > -		dev->mode_config.max_height = 8192;
> > +		dev->mode_config.max_width = 2048;
> > +		dev->mode_config.max_height = 2048;
> >  	}
> >  
> >  	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> > -- 
> > 2.19.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f7c4456220cd..4053ed93e73c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15366,16 +15366,22 @@  int intel_modeset_init(struct drm_device *dev)
 		}
 	}
 
-	/* maximum framebuffer dimensions */
-	if (IS_GEN(dev_priv, 2)) {
-		dev->mode_config.max_width = 2048;
-		dev->mode_config.max_height = 2048;
+	/*
+	 * Maximum framebuffer dimensions, chosen to match
+	 * the maximum render engine surface size on gen4+.
+	 */
+	if (INTEL_GEN(dev_priv) >= 7) {
+		dev->mode_config.max_width = 16384;
+		dev->mode_config.max_height = 16384;
+	} else if (INTEL_GEN(dev_priv) >= 4) {
+		dev->mode_config.max_width = 8192;
+		dev->mode_config.max_height = 8192;
 	} else if (IS_GEN(dev_priv, 3)) {
 		dev->mode_config.max_width = 4096;
 		dev->mode_config.max_height = 4096;
 	} else {
-		dev->mode_config.max_width = 8192;
-		dev->mode_config.max_height = 8192;
+		dev->mode_config.max_width = 2048;
+		dev->mode_config.max_height = 2048;
 	}
 
 	if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {