| Message ID | 20190228013259.30026-5-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3,1/6] drm/i915/psr: Remove PSR2 FIXME | expand |
On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza wrote: > When PSR2 is active aka after the number of frames programmed in > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > interruptions causing IGT tests to fail due timeout. > > Oddly that don't happen when PSR1 active, so here it switches from > PSR2 to PSR1 while user is requesting pipe CRC. > > Force setting mode_changed as true is necessary to atomic checks > functions compute new PSR state, that is why it was added to > intel_crtc_crc_prepare(). > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > v2: Changed commit description to describe that PSR2 inhibit CRC > calculations. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index f6d0b2aaffe2..e7ac24c33650 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private *dev_priv, struct drm_crtc *crtc, > goto put_state; > } > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != enable; Do we really want to set that unconditionally? > pipe_config->crc_enabled = enable; > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 6175b1d2e0c8..f7730b8b2ec0 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > + if (crtc_state->crc_enabled) > + return false; > + > return true; > } > > -- > 2.21.0
On Thu, 2019-02-28 at 18:58 +0200, Ville Syrjälä wrote: > On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza > wrote: > > When PSR2 is active aka after the number of frames programmed in > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > interruptions causing IGT tests to fail due timeout. > > > > Oddly that don't happen when PSR1 active, so here it switches from > > PSR2 to PSR1 while user is requesting pipe CRC. > > > > Force setting mode_changed as true is necessary to atomic checks > > functions compute new PSR state, that is why it was added to > > intel_crtc_crc_prepare(). > > > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > > > v2: Changed commit description to describe that PSR2 inhibit CRC > > calculations. > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index f6d0b2aaffe2..e7ac24c33650 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > > *dev_priv, struct drm_crtc *crtc, > > goto put_state; > > } > > > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != > > enable; > > Do we really want to set that unconditionally? Without it atomic helpers will return ealier as there is no state changes, I was wondering if the IPS was being applied in the bellow connectors_changed is not set. Anyways to triggers the code paths to disable PSR2 it is needed, and with fastboot enable by default in gen9+ it will do a fastset so not much drawbacks. > > > pipe_config->crc_enabled = enable; > > > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > > > + if (crtc_state->crc_enabled) > > + return false; > > + > > return true; > > } > > > > -- > > 2.21.0
On Thu, 2019-02-28 at 15:07 -0800, Souza, Jose wrote: > On Thu, 2019-02-28 at 18:58 +0200, Ville Syrjälä wrote: > > On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza > > wrote: > > > When PSR2 is active aka after the number of frames programmed in > > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > > interruptions causing IGT tests to fail due timeout. > > > > > > Oddly that don't happen when PSR1 active, so here it switches > > > from > > > PSR2 to PSR1 while user is requesting pipe CRC. > > > > > > Force setting mode_changed as true is necessary to atomic checks > > > functions compute new PSR state, that is why it was added to > > > intel_crtc_crc_prepare(). > > > > > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > > > > > v2: Changed commit description to describe that PSR2 inhibit CRC > > > calculations. > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > --- > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > index f6d0b2aaffe2..e7ac24c33650 100644 > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct > > > drm_i915_private > > > *dev_priv, struct drm_crtc *crtc, > > > goto put_state; > > > } > > > > > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != > > > enable; > > > > Do we really want to set that unconditionally? > > Without it atomic helpers will return ealier as there is no state > changes, I was wondering if the IPS was being applied in the bellow > connectors_changed is not set. > Anyways to triggers the code paths to disable PSR2 it is needed, and > with fastboot enable by default in gen9+ it will do a fastset so not > much drawbacks. What about pre gen9 platforms that do not have PSR? Running through state checks and acquiring several locks on platforms that will never need it is wasteful. Why not make it conditional upon? if (HAS_PSR()) or even CAN_PSR() for that matter. > > > > > > pipe_config->crc_enabled = enable; > > > > > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > > b/drivers/gpu/drm/i915/intel_psr.c > > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > > intel_dp *intel_dp, > > > return false; > > > } > > > > > > + if (crtc_state->crc_enabled) > > > + return false; > > > + > > > return true; > > > } > > > > > > -- > > > 2.21.0
On Thu, 2019-02-28 at 17:57 -0800, Dhinakaran Pandiyan wrote: > On Thu, 2019-02-28 at 15:07 -0800, Souza, Jose wrote: > > On Thu, 2019-02-28 at 18:58 +0200, Ville Syrjälä wrote: > > > On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza > > > wrote: > > > > When PSR2 is active aka after the number of frames programmed > > > > in > > > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate > > > > CRC > > > > interruptions causing IGT tests to fail due timeout. > > > > > > > > Oddly that don't happen when PSR1 active, so here it switches > > > > from > > > > PSR2 to PSR1 while user is requesting pipe CRC. > > > > > > > > Force setting mode_changed as true is necessary to atomic > > > > checks > > > > functions compute new PSR state, that is why it was added to > > > > intel_crtc_crc_prepare(). > > > > > > > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > > > > > > > v2: Changed commit description to describe that PSR2 inhibit > > > > CRC > > > > calculations. > > > > > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > > > 2 files changed, 4 insertions(+) > > > > > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > index f6d0b2aaffe2..e7ac24c33650 100644 > > > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct > > > > drm_i915_private > > > > *dev_priv, struct drm_crtc *crtc, > > > > goto put_state; > > > > } > > > > > > > > + pipe_config->base.mode_changed = pipe_config- > > > > >crc_enabled != > > > > enable; > > > > > > Do we really want to set that unconditionally? > > > > Without it atomic helpers will return ealier as there is no state > > changes, I was wondering if the IPS was being applied in the bellow > > connectors_changed is not set. > > Anyways to triggers the code paths to disable PSR2 it is needed, > > and > > with fastboot enable by default in gen9+ it will do a fastset so > > not > > much drawbacks. > What about pre gen9 platforms that do not have PSR? Running through > state checks and acquiring several locks on platforms that will never > need it is wasteful. > > Why not make it conditional upon? > if (HAS_PSR()) or even CAN_PSR() for that matter. Okay, done. > > > > > > > pipe_config->crc_enabled = enable; > > > > > > > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) > > > > { > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > > > b/drivers/gpu/drm/i915/intel_psr.c > > > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > > > --- a/drivers/gpu/drm/i915/intel_psr.c > > > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > > > intel_dp *intel_dp, > > > > return false; > > > > } > > > > > > > > + if (crtc_state->crc_enabled) > > > > + return false; > > > > + > > > > return true; > > > > } > > > > > > > > -- > > > > 2.21.0
On Wed, 2019-02-27 at 17:32 -0800, José Roberto de Souza wrote: > When PSR2 is active aka after the number of frames programmed in > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > interruptions causing IGT tests to fail due timeout. Just to make sure we are documenting the issue correctly in the commit message - is it the SU state when CRC generation stops or deep sleep? -DK > > Oddly that don't happen when PSR1 active, so here it switches from > PSR2 to PSR1 while user is requesting pipe CRC. > > Force setting mode_changed as true is necessary to atomic checks > functions compute new PSR state, that is why it was added to > intel_crtc_crc_prepare(). > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > v2: Changed commit description to describe that PSR2 inhibit CRC > calculations. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > b/drivers/gpu/drm/i915/intel_pipe_crc.c > index f6d0b2aaffe2..e7ac24c33650 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > *dev_priv, struct drm_crtc *crtc, > goto put_state; > } > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != > enable; > pipe_config->crc_enabled = enable; > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 6175b1d2e0c8..f7730b8b2ec0 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > intel_dp *intel_dp, > return false; > } > > + if (crtc_state->crc_enabled) > + return false; > + > return true; > } >
On Fri, 2019-03-01 at 12:12 -0800, Dhinakaran Pandiyan wrote: > On Wed, 2019-02-27 at 17:32 -0800, José Roberto de Souza wrote: > > When PSR2 is active aka after the number of frames programmed in > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > interruptions causing IGT tests to fail due timeout. > > Just to make sure we are documenting the issue correctly in the > commit > message - is it the SU state when CRC generation stops or deep sleep? 'Frames Before SU Entry' is the number of frames to activate PSR2, so it stops as soons as PSR2 is active. > > -DK > > Oddly that don't happen when PSR1 active, so here it switches from > > PSR2 to PSR1 while user is requesting pipe CRC. > > > > Force setting mode_changed as true is necessary to atomic checks > > functions compute new PSR state, that is why it was added to > > intel_crtc_crc_prepare(). > > > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > > > v2: Changed commit description to describe that PSR2 inhibit CRC > > calculations. > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index f6d0b2aaffe2..e7ac24c33650 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > > *dev_priv, struct drm_crtc *crtc, > > goto put_state; > > } > > > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != > > enable; > > pipe_config->crc_enabled = enable; > > > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > > > + if (crtc_state->crc_enabled) > > + return false; > > + > > return true; > > } > >
On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza wrote: > When PSR2 is active aka after the number of frames programmed in > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > interruptions causing IGT tests to fail due timeout. I'm more concerned about the all ones (or was it all zeroes?) crc we get when coming back from PSR. But I don't remmber right now if that was limited PSR2 or if it happens with PSR1 as well. Have you looked at that issue as well? > > Oddly that don't happen when PSR1 active, so here it switches from > PSR2 to PSR1 while user is requesting pipe CRC. > > Force setting mode_changed as true is necessary to atomic checks > functions compute new PSR state, that is why it was added to > intel_crtc_crc_prepare(). > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > v2: Changed commit description to describe that PSR2 inhibit CRC > calculations. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index f6d0b2aaffe2..e7ac24c33650 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private *dev_priv, struct drm_crtc *crtc, > goto put_state; > } > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != enable; > pipe_config->crc_enabled = enable; > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 6175b1d2e0c8..f7730b8b2ec0 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > return false; > } > > + if (crtc_state->crc_enabled) > + return false; > + > return true; > } > > -- > 2.21.0
On Fri, 2019-03-01 at 22:45 +0200, Ville Syrjälä wrote: > On Wed, Feb 27, 2019 at 05:32:58PM -0800, José Roberto de Souza > wrote: > > When PSR2 is active aka after the number of frames programmed in > > PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC > > interruptions causing IGT tests to fail due timeout. > > I'm more concerned about the all ones (or was it all zeroes?) crc we > get when coming back from PSR. But I don't remmber right now if that > was limited PSR2 or if it happens with PSR1 as well. Have you looked > at that issue as well? Just wrote a test that gets 500 CRCs and the real difference between PSR1 and PSR2 is that PSR1 activation is blocked after the pipe CRC is enabled while on PSR2 that don't happen. After exit PSR2 I got more 4 CRC interruptions, 1 invalid value and 3 valid ones. Got the results above in a WHL and ICL. > > > Oddly that don't happen when PSR1 active, so here it switches from > > PSR2 to PSR1 while user is requesting pipe CRC. > > > > Force setting mode_changed as true is necessary to atomic checks > > functions compute new PSR state, that is why it was added to > > intel_crtc_crc_prepare(). > > > > v3: Reusing intel_crtc_crc_prepare() and crc_enabled > > > > v2: Changed commit description to describe that PSR2 inhibit CRC > > calculations. > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > > --- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + > > drivers/gpu/drm/i915/intel_psr.c | 3 +++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c > > b/drivers/gpu/drm/i915/intel_pipe_crc.c > > index f6d0b2aaffe2..e7ac24c33650 100644 > > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > > @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private > > *dev_priv, struct drm_crtc *crtc, > > goto put_state; > > } > > > > + pipe_config->base.mode_changed = pipe_config->crc_enabled != > > enable; > > pipe_config->crc_enabled = enable; > > > > if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 6175b1d2e0c8..f7730b8b2ec0 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct > > intel_dp *intel_dp, > > return false; > > } > > > > + if (crtc_state->crc_enabled) > > + return false; > > + > > return true; > > } > > > > -- > > 2.21.0
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index f6d0b2aaffe2..e7ac24c33650 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -308,6 +308,7 @@ intel_crtc_crc_prepare(struct drm_i915_private *dev_priv, struct drm_crtc *crtc, goto put_state; } + pipe_config->base.mode_changed = pipe_config->crc_enabled != enable; pipe_config->crc_enabled = enable; if (IS_HASWELL(dev_priv) && intel_crtc->pipe == PIPE_A) { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 6175b1d2e0c8..f7730b8b2ec0 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -572,6 +572,9 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (crtc_state->crc_enabled) + return false; + return true; }
When PSR2 is active aka after the number of frames programmed in PSR2_CTL 'Frames Before SU Entry' hardware stops to generate CRC interruptions causing IGT tests to fail due timeout. Oddly that don't happen when PSR1 active, so here it switches from PSR2 to PSR1 while user is requesting pipe CRC. Force setting mode_changed as true is necessary to atomic checks functions compute new PSR state, that is why it was added to intel_crtc_crc_prepare(). v3: Reusing intel_crtc_crc_prepare() and crc_enabled v2: Changed commit description to describe that PSR2 inhibit CRC calculations. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + drivers/gpu/drm/i915/intel_psr.c | 3 +++ 2 files changed, 4 insertions(+)