diff mbox series

[v3,RESEND,01/24] arm64: dts: exynos: configure GSCALER related clocks

Message ID 20190325071349.22600-2-a.hajda@samsung.com (mailing list archive)
State Accepted
Headers show
Series drm/exynos: add support for GSCALER planes on Exynos5433 | expand

Commit Message

Andrzej Hajda March 25, 2019, 7:13 a.m. UTC
GSCALER should be feed with clock at certain rates.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
---
Already merged !!!
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 6 ++++++
 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts         | 6 ++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

Comments

Krzysztof Kozlowski March 25, 2019, 7:50 a.m. UTC | #1
On Mon, 25 Mar 2019 at 08:13, Andrzej Hajda <a.hajda@samsung.com> wrote:
>
> GSCALER should be feed with clock at certain rates.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> ---
> Already merged !!!

Then you should skip it because someone might not notice it and apply
second time.

Best regards,
Krzysztof
Andrzej Hajda March 25, 2019, 8:31 a.m. UTC | #2
On 25.03.2019 08:50, Krzysztof Kozlowski wrote:
> On Mon, 25 Mar 2019 at 08:13, Andrzej Hajda <a.hajda@samsung.com> wrote:
>> GSCALER should be feed with clock at certain rates.
>>
>> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
>> ---
>> Already merged !!!
> Then you should skip it because someone might not notice it and apply
> second time.


I was asked to rebase the patchset on exynos-drm-next, but it does not
contains yet these patches,

so without adding it here "someone might not notice it and" can complain
that patchset is broken :)

Maybe better solution would be point to point out samsung-soc tree tag
which should exynos-drm-next be based on? Next time I will try this way.


Regards

Andrzej


>
> Best regards,
> Krzysztof
>
>
Krzysztof Kozlowski March 25, 2019, 8:44 a.m. UTC | #3
On Mon, 25 Mar 2019 at 09:32, Andrzej Hajda <a.hajda@samsung.com> wrote:
>
> On 25.03.2019 08:50, Krzysztof Kozlowski wrote:
> > On Mon, 25 Mar 2019 at 08:13, Andrzej Hajda <a.hajda@samsung.com> wrote:
> >> GSCALER should be feed with clock at certain rates.
> >>
> >> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> >> ---
> >> Already merged !!!
> > Then you should skip it because someone might not notice it and apply
> > second time.
>
>
> I was asked to rebase the patchset on exynos-drm-next, but it does not
> contains yet these patches,
>
> so without adding it here "someone might not notice it and" can complain
> that patchset is broken :)
>
> Maybe better solution would be point to point out samsung-soc tree tag
> which should exynos-drm-next be based on? Next time I will try this way.

Yes, I see. If needed, I can provide stable tag with DTS patches
however in general this is discouraged because it means that you break
the ABI. Updated driver does not work with old DTBs... so the best way
is to split the patchset and bring in the second part of driver
changes later. :)

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index d88e2f0e179a..d2de16645e10 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -289,6 +289,12 @@ 
 	assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
 };
 
+&cmu_mif {
+	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
+	assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
+	assigned-clock-rates = <0>, <333000000>;
+};
+
 &cmu_mscl {
 	assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
 			  <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 3d7e0a782243..dda5d2746a74 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -33,7 +33,8 @@ 
 			  <&cmu_disp CLK_MOUT_DISP_PLL>,
 			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
 			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
-			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
+			  <&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
 	assigned-clock-parents = <0>, <0>,
 				 <&cmu_mif CLK_ACLK_DISP_333>,
 				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
@@ -45,7 +46,8 @@ 
 				 <&cmu_disp CLK_FOUT_DISP_PLL>,
 				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
 				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
-				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+				 <&cmu_mif CLK_SCLK_DSD_DISP>;
 	assigned-clock-rates = <250000000>, <400000000>;
 };