Message ID | 20190411214835.19947-3-digetx@gmail.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | clk: Tegra124 PLLM fixes | expand |
Quoting Dmitry Osipenko (2019-04-11 14:48:35) > According to the Tegra124 TRM documentation, PLLM_MISC2 register doesn't > have the lock-enable bit as well as any other PLLM-related register. Hence > PLLM re-locking can't be initiated by software. The incorrect bit setting > should have been harmless since that bit is undefined according to TRM. > > Tested-by: Steev Klimaszewski <steev@kali.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- Applied to clk-next
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index df0018f7bf7e..940592375583 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -413,7 +413,6 @@ static struct tegra_clk_pll_params pll_m_params = { .base_reg = PLLM_BASE, .misc_reg = PLLM_MISC, .lock_mask = PLL_BASE_LOCK, - .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE, .lock_delay = 300, .max_p = 5, .pdiv_tohw = pllm_p, @@ -421,7 +420,7 @@ static struct tegra_clk_pll_params pll_m_params = { .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, .freq_table = pll_m_freq_table, - .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .flags = TEGRA_PLL_USE_LOCK, }; static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {