| Message ID | 20190607091230.1489-4-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for new DMC headers | expand |
>-----Original Message----- >From: De Marchi, Lucas >Sent: Friday, June 7, 2019 2:12 AM >To: intel-gfx@lists.freedesktop.org >Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>; Srivatsa, Anusha ><anusha.srivatsa@intel.com>; De Marchi, Lucas <lucas.demarchi@intel.com> >Subject: [PATCH 3/9] drm/i915/dmc: add support for package_header with >version 2 > >The only meaninful change is that it supports up to 32 fw_info entries rather than >the previous max=20. > >Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> >--- > drivers/gpu/drm/i915/intel_csr.c | 38 ++++++++++++++++++++++---------- > 1 file changed, 26 insertions(+), 12 deletions(-) > >diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c >index 99fa4db95e46..ba72c29acbcc 100644 >--- a/drivers/gpu/drm/i915/intel_csr.c >+++ b/drivers/gpu/drm/i915/intel_csr.c >@@ -71,6 +71,7 @@ MODULE_FIRMWARE(BXT_CSR_PATH); > > #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF > #define PACKAGE_MAX_FW_INFO_ENTRIES 20 >+#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 > > struct intel_css_header { > /* 0x09 for DMC */ >@@ -133,7 +134,7 @@ struct intel_package_header { > /* DMC container header length in dwords */ > u8 header_len; > >- /* always value would be 0x01 */ >+ /* 0x01, 0x02 */ > u8 header_ver; > > u8 reserved[10]; >@@ -339,7 +340,7 @@ static u32 *parse_csr_fw(struct drm_i915_private >*dev_priv, > struct intel_dmc_header *dmc_header; > struct intel_csr *csr = &dev_priv->csr; > const struct stepping_info *si = intel_get_stepping_info(dev_priv); >- u32 dmc_offset, num_entries, readcount = 0, nbytes; >+ u32 dmc_offset, num_entries, max_entries, readcount = 0, nbytes; > u32 i; > u32 *dmc_payload; > size_t fsize; >@@ -381,20 +382,32 @@ static u32 *parse_csr_fw(struct drm_i915_private >*dev_priv, > /* Extract Package Header information*/ > package_header = (struct intel_package_header *) > &fw->data[readcount]; >- if (sizeof(struct intel_package_header) != >- (package_header->header_len * 4)) { >+ >+ readcount += sizeof(struct intel_package_header); >+ >+ if (package_header->header_ver == 1) { >+ max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; >+ } else if (package_header->header_ver == 2) { >+ max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; >+ } else { >+ DRM_ERROR("DMC firmware has unknown header version >%u\n", >+ package_header->header_ver); >+ return NULL; >+ } >+ >+ if (package_header->header_len * 4 != >+ sizeof(struct intel_package_header) + >+ max_entries * sizeof(struct intel_fw_info)) { > DRM_ERROR("DMC firmware has wrong package header length " >- "(%u bytes)\n", >- (package_header->header_len * 4)); >+ "(%u bytes)\n", package_header->header_len * 4); > return NULL; > } > >- readcount += sizeof(struct intel_package_header); > num_entries = package_header->num_entries; >- if (WARN_ON(package_header->num_entries > >PACKAGE_MAX_FW_INFO_ENTRIES)) >- num_entries = PACKAGE_MAX_FW_INFO_ENTRIES; >+ if (WARN_ON(package_header->num_entries > max_entries)) >+ num_entries = max_entries; > >- fsize += PACKAGE_MAX_FW_INFO_ENTRIES * sizeof(struct >intel_fw_info); >+ fsize += max_entries * sizeof(struct intel_fw_info); > if (fsize > fw->size) > goto error_truncated; > >@@ -405,8 +418,9 @@ static u32 *parse_csr_fw(struct drm_i915_private >*dev_priv, > si->stepping); > return NULL; > } >- /* we always have space for PACKAGE_MAX_FW_INFO_ENTRIES */ >- readcount += PACKAGE_MAX_FW_INFO_ENTRIES * sizeof(struct >intel_fw_info); >+ >+ /* we always have space for max_entries, even if not all are used */ >+ readcount += max_entries * sizeof(struct intel_fw_info); > > /* Convert dmc_offset into number of bytes. By default it is in dwords*/ > dmc_offset *= 4; >-- >2.21.0
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index 99fa4db95e46..ba72c29acbcc 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -71,6 +71,7 @@ MODULE_FIRMWARE(BXT_CSR_PATH); #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF #define PACKAGE_MAX_FW_INFO_ENTRIES 20 +#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 struct intel_css_header { /* 0x09 for DMC */ @@ -133,7 +134,7 @@ struct intel_package_header { /* DMC container header length in dwords */ u8 header_len; - /* always value would be 0x01 */ + /* 0x01, 0x02 */ u8 header_ver; u8 reserved[10]; @@ -339,7 +340,7 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv, struct intel_dmc_header *dmc_header; struct intel_csr *csr = &dev_priv->csr; const struct stepping_info *si = intel_get_stepping_info(dev_priv); - u32 dmc_offset, num_entries, readcount = 0, nbytes; + u32 dmc_offset, num_entries, max_entries, readcount = 0, nbytes; u32 i; u32 *dmc_payload; size_t fsize; @@ -381,20 +382,32 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv, /* Extract Package Header information*/ package_header = (struct intel_package_header *) &fw->data[readcount]; - if (sizeof(struct intel_package_header) != - (package_header->header_len * 4)) { + + readcount += sizeof(struct intel_package_header); + + if (package_header->header_ver == 1) { + max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; + } else if (package_header->header_ver == 2) { + max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; + } else { + DRM_ERROR("DMC firmware has unknown header version %u\n", + package_header->header_ver); + return NULL; + } + + if (package_header->header_len * 4 != + sizeof(struct intel_package_header) + + max_entries * sizeof(struct intel_fw_info)) { DRM_ERROR("DMC firmware has wrong package header length " - "(%u bytes)\n", - (package_header->header_len * 4)); + "(%u bytes)\n", package_header->header_len * 4); return NULL; } - readcount += sizeof(struct intel_package_header); num_entries = package_header->num_entries; - if (WARN_ON(package_header->num_entries > PACKAGE_MAX_FW_INFO_ENTRIES)) - num_entries = PACKAGE_MAX_FW_INFO_ENTRIES; + if (WARN_ON(package_header->num_entries > max_entries)) + num_entries = max_entries; - fsize += PACKAGE_MAX_FW_INFO_ENTRIES * sizeof(struct intel_fw_info); + fsize += max_entries * sizeof(struct intel_fw_info); if (fsize > fw->size) goto error_truncated; @@ -405,8 +418,9 @@ static u32 *parse_csr_fw(struct drm_i915_private *dev_priv, si->stepping); return NULL; } - /* we always have space for PACKAGE_MAX_FW_INFO_ENTRIES */ - readcount += PACKAGE_MAX_FW_INFO_ENTRIES * sizeof(struct intel_fw_info); + + /* we always have space for max_entries, even if not all are used */ + readcount += max_entries * sizeof(struct intel_fw_info); /* Convert dmc_offset into number of bytes. By default it is in dwords*/ dmc_offset *= 4;
The only meaninful change is that it supports up to 32 fw_info entries rather than the previous max=20. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/intel_csr.c | 38 ++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 12 deletions(-)