| Message ID | 20190617143255.10462-2-indou.takao@jp.fujitsu.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Introduce boot parameter to disable TLB flush instruction within the same inner shareable domain | expand |
Hi, I know Will is on the case but just expressing some thoughts of my own. On Mon, Jun 17, 2019 at 11:32:54PM +0900, Takao Indoh wrote: > From: Takao Indoh <indou.takao@fujitsu.com> > > mm_cpumask was deleted by the commit 38d96287504a ("arm64: mm: kill > mm_cpumask usage") because it was not used at that time. Now this is needed > to find appropriate CPUs for TLB flush, so this patch reverts this commit. > > Signed-off-by: QI Fuli <qi.fuli@fujitsu.com> > Signed-off-by: Takao Indoh <indou.takao@fujitsu.com> > --- > arch/arm64/include/asm/mmu_context.h | 7 ++++++- > arch/arm64/kernel/smp.c | 6 ++++++ > arch/arm64/mm/context.c | 2 ++ > 3 files changed, 14 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h > index 2da3e478fd8f..21ef11590bcb 100644 > --- a/arch/arm64/include/asm/mmu_context.h > +++ b/arch/arm64/include/asm/mmu_context.h > @@ -241,8 +241,13 @@ static inline void > switch_mm(struct mm_struct *prev, struct mm_struct *next, > struct task_struct *tsk) > { > - if (prev != next) > + unsigned int cpu = smp_processor_id(); > + > + if (prev != next) { > __switch_mm(next); > + cpumask_clear_cpu(cpu, mm_cpumask(prev)); > + local_flush_tlb_mm(prev); > + } That's not actually a revert as we've never flushed the TLBs on the switch_mm() path. Also, this flush is not sufficient on a CnP capable CPU since another thread of the same CPU could have the prev TTBR0_EL1 value set and loading the TLB back.
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 2da3e478fd8f..21ef11590bcb 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -241,8 +241,13 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { - if (prev != next) + unsigned int cpu = smp_processor_id(); + + if (prev != next) { __switch_mm(next); + cpumask_clear_cpu(cpu, mm_cpumask(prev)); + local_flush_tlb_mm(prev); + } /* * Update the saved TTBR0_EL1 of the scheduled-in task as the previous diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index bb4b3f07761a..12a922d1cdd7 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -218,6 +218,7 @@ asmlinkage notrace void secondary_start_kernel(void) */ mmgrab(mm); current->active_mm = mm; + cpumask_set_cpu(cpu, mm_cpumask(mm)); /* * TTBR0 is only used for the identity mapping at this stage. Make it @@ -320,6 +321,11 @@ int __cpu_disable(void) */ irq_migrate_all_off_this_cpu(); + /* + * Remove this CPU from the vm mask set of all processes. + */ + clear_tasks_mm_cpumask(cpu); + return 0; } diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 1f0ea2facf24..ff3ab2924074 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -188,6 +188,7 @@ static u64 new_context(struct mm_struct *mm) set_asid: __set_bit(asid, asid_map); cur_idx = asid; + cpumask_clear(mm_cpumask(mm)); return idx2asid(asid) | generation; } @@ -239,6 +240,7 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) switch_mm_fastpath: arm64_apply_bp_hardening(); + cpumask_set_cpu(cpu, mm_cpumask(mm)); /* * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when