[v4,05/28] riscv: roms: Remove executable attribute of opensbi images

From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
 Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org,
 qemu-riscv@nongnu.org
Date: Sun, 18 Aug 2019 22:11:38 -0700
Message-Id: <1566191521-7820-6-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com>
References: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com>
Subject: [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable
 attribute of opensbi images
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 qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org
Sender: "Qemu-devel"
 <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>

Message ID	1566191521-7820-6-git-send-email-bmeng.cn@gmail.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org> From: Bin Meng <bmeng.cn@gmail.com> To: Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Sun, 18 Aug 2019 22:11:38 -0700 Message-Id: <1566191521-7820-6-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com> References: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com> Subject: [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Precedence: list Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	riscv: sifive_u: Improve the emulation fidelity of sifive_u machine \| expand [v4,00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine [v4,01/28] riscv: hw: Remove superfluous "linux, phandle" property [v4,02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell [v4,03/28] riscv: hw: Remove not needed PLIC properties in device tree [v4,04/28] riscv: hw: Change create_fdt() to return void [v4,05/28] riscv: roms: Remove executable attribute of opensbi images [v4,06/28] riscv: sifive_u: Remove the unnecessary include of prci header [v4,07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} [v4,08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming [v4,09/28] riscv: sifive_e: prci: Update the PRCI register block size [v4,11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines [v4,12/28] riscv: hart: Extract hart realize to a separate routine [v4,13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array [v4,14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC [v4,15/28] riscv: sifive_u: Set the minimum number of cpus to 2 [v4,16/28] riscv: sifive_u: Update PLIC hart topology configuration string [v4,17/28] riscv: sifive: Implement PRCI model for FU540 [v4,18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes [v4,19/28] riscv: sifive_u: Add PRCI block to the SoC [v4,20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes [v4,21/28] riscv: sifive_u: Update UART base addresses and IRQs [v4,22/28] riscv: sifive_u: Change UART node name in device tree [v4,23/28] riscv: roms: Update default bios for sifive_u machine [v4,24/28] riscv: sifive: Implement a model for SiFive FU540 OTP [v4,25/28] riscv: sifive_u: Instantiate OTP memory with a serial number [v4,26/28] riscv: sifive_u: Fix broken GEM support [v4,27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet [v4,28/28] riscv: sifive_u: Update model and compatible strings in device tree

[v4,05/28] riscv: roms: Remove executable attribute of opensbi images

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