Show patches with: Submitter = Bin Meng       |    State = Action Required       |    Archived = No       |   340 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,6/6] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-08-03 Bin Meng New
[v6,5/6] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-08-03 Bin Meng New
[v6,4/6] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-08-03 Bin Meng New
[v6,3/6] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-08-03 Bin Meng New
[v6,2/6] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-08-03 Bin Meng New
[v6,1/6] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 1 - 0 0 0 2020-08-03 Bin Meng New
hw/riscv: sifive_u: Add a dummy L2 cache controller device hw/riscv: sifive_u: Add a dummy L2 cache controller device - 1 - 0 0 0 2020-07-20 Bin Meng New
hw/riscv: sifive_e: Correct debug block size hw/riscv: sifive_e: Correct debug block size - 1 - 0 0 0 2020-07-16 Bin Meng New
[v5,7/7] Makefile: Ship the generic platform bios ELF images for RISC-V riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - - 0 0 0 2020-07-16 Bin Meng New
[v5,6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-16 Bin Meng New
[v5,5/7] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-16 Bin Meng New
[v5,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-16 Bin Meng New
[v5,3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-16 Bin Meng New
[v5,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-16 Bin Meng New
[v5,1/7] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 1 - 0 0 0 2020-07-16 Bin Meng New
[v4,7/7] Makefile: Ship the generic platform bios images for RISC-V riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 1 - 0 0 0 2020-07-10 Bin Meng New
[v4,6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-10 Bin Meng New
[v4,5/7] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-10 Bin Meng New
[v4,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-10 Bin Meng New
[v4,3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-10 Bin Meng New
[v4,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-10 Bin Meng New
[v4,1/7] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 1 - 0 0 0 2020-07-10 Bin Meng New
[v2,2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is runnin... [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - - - 0 0 0 2020-07-09 Bin Meng New
[v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 [v2,1/2] hw/riscv: Modify MROM size to end at 0x10000 - 1 - 0 0 0 2020-07-09 Bin Meng New
[2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running i... [1/2] hw/riscv: Modify MROM size to end at 0x10000 - - - 0 0 0 2020-07-09 Bin Meng New
[1/2] hw/riscv: Modify MROM size to end at 0x10000 [1/2] hw/riscv: Modify MROM size to end at 0x10000 - 1 - 0 0 0 2020-07-09 Bin Meng New
hw/riscv: virt: Sort the SoC memmap table entries hw/riscv: virt: Sort the SoC memmap table entries - 1 - 0 0 0 2020-07-03 Bin Meng New
[v3,7/7] Makefile: Ship the generic platform bios images for RISC-V riscv: Switch to use generic platform fw_dynamic type opensbi bios images - - - 0 0 0 2020-07-03 Bin Meng New
[v3,6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-03 Bin Meng New
[v3,5/7] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-03 Bin Meng New
[v3,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-03 Bin Meng New
[v3,3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-03 Bin Meng New
[v3,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 2 - 0 0 0 2020-07-03 Bin Meng New
[v3,1/7] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform fw_dynamic type opensbi bios images - 1 - 0 0 0 2020-07-03 Bin Meng New
MAINTAINERS: Add an entry for OpenSBI firmware MAINTAINERS: Add an entry for OpenSBI firmware - 1 - 0 0 0 2020-06-26 Bin Meng New
[v2,7/7] Makefile: Ship the generic platform bios images for RISC-V riscv: Switch to use generic platform of opensbi bios images - - - 0 0 0 2020-06-22 Bin Meng New
[v2,6/7] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-06-22 Bin Meng New
[v2,5/7] hw/riscv: spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - 2 - 0 0 0 2020-06-22 Bin Meng New
[v2,4/7] hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - 2 - 0 0 0 2020-06-22 Bin Meng New
[v2,3/7] roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-06-22 Bin Meng New
[v2,2/7] roms/opensbi: Upgrade from v0.7 to v0.8 riscv: Switch to use generic platform of opensbi bios images - 2 - 0 0 0 2020-06-22 Bin Meng New
[v2,1/7] configure: Create symbolic links for pc-bios/*.elf files riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-06-22 Bin Meng New
[v2,5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-16 Bin Meng New
[v2,4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-16 Bin Meng New
[v2,3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-16 Bin Meng New
[v2,2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-16 Bin Meng New
[v2,1/5] target/riscv: Rename IBEX CPU init routine hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-16 Bin Meng New
[v2,4/4] riscv: Keep the CPU init routine names consistent [v2,1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-11 Bin Meng New
[v2,3/4] riscv: Generalize CPU init routine for the imacu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-11 Bin Meng New
[v2,2/4] riscv: Generalize CPU init routine for the gcsu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-11 Bin Meng New
[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - - 0 0 0 2020-06-08 Bin Meng New
[11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[05/15] hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - 1 - 0 0 0 2020-06-08 Bin Meng New
[4/4] riscv: Keep the CPU init routine names consistent [1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-05 Bin Meng New
[3/4] riscv: Generalize CPU init routine for the imacu CPU [1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-05 Bin Meng New
[2/4] riscv: Generalize CPU init routine for the gcsu CPU [1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-05 Bin Meng New
[1/4] riscv: Generalize CPU init routine for the base CPU [1/4] riscv: Generalize CPU init routine for the base CPU - 1 - 0 0 0 2020-06-05 Bin Meng New
[2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - 2 - 0 0 0 2020-05-21 Bin Meng New
[1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - 2 - 0 0 0 2020-05-21 Bin Meng New
[5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-05-01 Bin Meng New
[4/5] riscv/spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - 2 - 0 0 0 2020-05-01 Bin Meng New
[3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - 2 - 0 0 0 2020-05-01 Bin Meng New
[2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-05-01 Bin Meng New
[1/5] roms/opensbi: Update to support building bios images for generic platform riscv: Switch to use generic platform of opensbi bios images - 1 - 0 0 0 2020-05-01 Bin Meng New
riscv/spike: Change the default bios to use plain binary image riscv/spike: Change the default bios to use plain binary image - - - 0 0 0 2020-05-01 Bin Meng New
riscv: Change the default behavior if no -bios option is specified riscv: Change the default behavior if no -bios option is specified - 1 - 0 0 0 2020-05-01 Bin Meng New
roms: opensbi: Upgrade from v0.6 to v0.7 roms: opensbi: Upgrade from v0.6 to v0.7 - 1 - 0 0 0 2020-04-20 Bin Meng New
hw/riscv: Generate correct "mmu-type" for 32-bit machines hw/riscv: Generate correct "mmu-type" for 32-bit machines - 1 - 0 0 0 2020-03-07 Bin Meng New
[v2,4/4] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image 1 - - 0 0 0 2020-02-24 Bin Meng New
[v2,3/4] riscv: sifive_u: Update BIOS_FILENAME for 32-bit riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - 1 - 0 0 0 2020-02-24 Bin Meng New
[v2,2/4] roms: opensbi: Add 32-bit firmware image for sifive_u machine riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - 1 - 0 0 0 2020-02-24 Bin Meng New
[v2,1/4] roms: opensbi: Upgrade from v0.5 to v0.6 riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - 1 - 0 0 0 2020-02-24 Bin Meng New
[2/2] riscv: sifive_u: Update BIOS_FILENAME for 32-bit [1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u - 1 - 0 0 0 2020-02-20 Bin Meng New
[1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u [1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u - - - 0 0 0 2020-02-20 Bin Meng New
[v2] riscv: sifive_u: Add a "serial" property for board serial number [v2] riscv: sifive_u: Add a "serial" property for board serial number - 1 - 0 0 0 2020-02-16 Bin Meng New
riscv: virt: Allow PCI address 0 riscv: virt: Allow PCI address 0 - 1 - 0 0 0 2019-11-22 Bin Meng New
riscv: sifive_u: Add a "serial" property for board serial number riscv: sifive_u: Add a "serial" property for board serial number - 2 - 0 0 0 2019-11-16 Bin Meng New
[v2,2/2] riscv: sifive_u: Add ethernet0 to the aliases node [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - 2 - 0 0 0 2019-09-21 Bin Meng New
[v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - 1 - 0 0 0 2019-09-21 Bin Meng New
riscv: Skip checking CSR privilege level in debugger mode riscv: Skip checking CSR privilege level in debugger mode - 1 - 0 0 0 2019-09-20 Bin Meng New
[2/2] riscv: sifive_u: Add ethernet0 to the aliases node [1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes - 1 - 0 0 0 2019-09-20 Bin Meng New
[1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes [1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes - 1 - 0 0 0 2019-09-20 Bin Meng New
[v8,32/32] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,30/32] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,29/32] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - 0 0 0 2019-09-06 Bin Meng New
[v8,28/32] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - 1 - 0 0 0 2019-09-06 Bin Meng New
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