| Message ID | 1566191521-7820-19-git-send-email-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand |
On Sun, Aug 18, 2019 at 10:29 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > To keep in sync with Linux kernel device tree, generate hfclk and > rtcclk nodes in the device tree, to be referenced by PRCI node. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++ > include/hw/riscv/sifive_u.h | 2 ++ > 2 files changed, 25 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 284f7a5..08db741 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -80,6 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > char ethclk_names[] = "pclk\0hclk\0tx_clk"; > uint32_t plic_phandle, ethclk_phandle, phandle = 1; > uint32_t uartclk_phandle; > + uint32_t hfclk_phandle, rtcclk_phandle; > > fdt = s->fdt = create_device_tree(&s->fdt_size); > if (!fdt) { > @@ -98,6 +99,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); > qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); > > + hfclk_phandle = phandle++; > + nodename = g_strdup_printf("/hfclk"); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); > + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); > + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > + SIFIVE_U_HFCLK_FREQ); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); > + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > + g_free(nodename); > + > + rtcclk_phandle = phandle++; > + nodename = g_strdup_printf("/rtcclk"); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); > + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); > + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > + SIFIVE_U_RTCCLK_FREQ); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); > + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); > + g_free(nodename); > + > nodename = g_strdup_printf("/memory@%lx", > (long)memmap[SIFIVE_U_DRAM].base); > qemu_fdt_add_subnode(fdt, nodename); > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 7a1a4f3..debbf28 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -68,6 +68,8 @@ enum { > > enum { > SIFIVE_U_CLOCK_FREQ = 1000000000, > + SIFIVE_U_HFCLK_FREQ = 33333333, > + SIFIVE_U_RTCCLK_FREQ = 1000000, > SIFIVE_U_GEM_CLOCK_FREQ = 125000000 > }; > > -- > 2.7.4 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 284f7a5..08db741 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -80,6 +80,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char ethclk_names[] = "pclk\0hclk\0tx_clk"; uint32_t plic_phandle, ethclk_phandle, phandle = 1; uint32_t uartclk_phandle; + uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -98,6 +99,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 7a1a4f3..debbf28 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -68,6 +68,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 };
To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v4: None Changes in v3: None Changes in v2: None hw/riscv/sifive_u.c | 23 +++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 25 insertions(+)