| Message ID | 20190813154747.24256-11-hch@lst.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [01/15] irqchip/sifive-plic: set max threshold for ignored handlers | expand |
On Tue, 2019-08-13 at 17:47 +0200, Christoph Hellwig wrote: > There is no SBI when we run in M-mode, so fail the compile for any > code > trying to use SBI calls. > > Signed-off-by: Christoph Hellwig <hch@lst.de> > --- > arch/riscv/include/asm/sbi.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/sbi.h > b/arch/riscv/include/asm/sbi.h > index 21134b3ef404..1e17f07eadaf 100644 > --- a/arch/riscv/include/asm/sbi.h > +++ b/arch/riscv/include/asm/sbi.h > @@ -8,6 +8,7 @@ > > #include <linux/types.h> > > +#ifndef CONFIG_M_MODE > #define SBI_SET_TIMER 0 > #define SBI_CONSOLE_PUTCHAR 1 > #define SBI_CONSOLE_GETCHAR 2 > @@ -94,4 +95,5 @@ static inline void sbi_remote_sfence_vma_asid(const > unsigned long *hart_mask, > SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, > asid); > } > > -#endif > +#endif /* CONFIG_M_MODE */ > +#endif /* _ASM_RISCV_SBI_H */ Reviewed-by: Atish Patra <atish.patra@wdc.com>
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 21134b3ef404..1e17f07eadaf 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -8,6 +8,7 @@ #include <linux/types.h> +#ifndef CONFIG_M_MODE #define SBI_SET_TIMER 0 #define SBI_CONSOLE_PUTCHAR 1 #define SBI_CONSOLE_GETCHAR 2 @@ -94,4 +95,5 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid); } -#endif +#endif /* CONFIG_M_MODE */ +#endif /* _ASM_RISCV_SBI_H */
There is no SBI when we run in M-mode, so fail the compile for any code trying to use SBI calls. Signed-off-by: Christoph Hellwig <hch@lst.de> --- arch/riscv/include/asm/sbi.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)