| Message ID | 20190822111445.29350-6-ramalingam.c@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ | expand |
On Thu, 22 Aug 2019, Ramalingam C <ramalingam.c@intel.com> wrote: > On gen12+ platforms, HDCP HW is associated to the transcoder. > Hence on every modeset associated transcoder is updated into the > intel_hdcp. > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 7 +++ > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++ > drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++++++++++++++++- > drivers/gpu/drm/i915/display/intel_hdcp.h | 2 + > drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++ > 5 files changed, 63 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 449abaea619f..c6b9f7198ee3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -388,6 +388,13 @@ struct intel_hdcp { > wait_queue_head_t cp_irq_queue; > atomic_t cp_irq_count; > int cp_irq_count_cached; > + > + /* > + * HDCP register access for gen12+ need the transcoder associated. > + * Transcoder attached to the connector could be changed at modeset. > + * Hence caching the transcoder here. > + */ > + enum transcoder trans; $ git grep "enum transcoder" -- drivers/gpu/drm/i915/ Please call this cpu_transcoder. > }; > > struct intel_connector { > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 921ad0a2f7ba..ba5317d56da7 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2244,6 +2244,9 @@ intel_dp_compute_config(struct intel_encoder *encoder, > > intel_psr_compute_config(intel_dp, pipe_config); > > + intel_hdcp_transcoder_config(intel_connector, > + pipe_config->cpu_transcoder); > + > return 0; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c > index 534832f435dc..264bda5d484c 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c > @@ -1762,13 +1762,60 @@ enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port) > } > } > > +static inline > +enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder tc) enum transcoder trancoder or enum transcoder cpu_transcoder. > +{ > + switch (tc) { > + case TRANSCODER_A ... TRANSCODER_D: > + return (enum mei_fw_tc)(tc | 0x10); > + case TRANSCODER_EDP: > + return MEI_TC_EDP; > + case TRANSCODER_DSI_0: > + return MEI_TC_DSI0; > + case TRANSCODER_DSI_1: > + return MEI_TC_DSI1; > + default: > + return MEI_INVALID_TRANSCODER; > + } > +} > + > +void intel_hdcp_transcoder_config(struct intel_connector *connector, > + enum transcoder trans) enum transcoder trancoder or enum transcoder cpu_transcoder. > +{ > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > + struct intel_hdcp *hdcp = &connector->hdcp; > + > + if (!hdcp->shim) > + return; > + > + if (INTEL_GEN(dev_priv) >= 12) { > + mutex_lock(&hdcp->mutex); > + hdcp->trans = trans; > + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(trans); > + mutex_unlock(&hdcp->mutex); > + } > +} > + > static inline int initialize_hdcp_port_data(struct intel_connector *connector, > const struct intel_hdcp_shim *shim) > { > + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); > struct intel_hdcp *hdcp = &connector->hdcp; > struct hdcp_port_data *data = &hdcp->port_data; > + struct intel_crtc *crtc; > + > + if (INTEL_GEN(dev_priv) < 12) { > + data->fw_ddi = > + intel_get_mei_fw_ddi_index(connector->encoder->port); > + } else { > + crtc = to_intel_crtc(connector->base.state->crtc); > + if (crtc) { > + hdcp->trans = crtc->config->cpu_transcoder; > + data->fw_tc = intel_get_mei_fw_tc(hdcp->trans); > + } > + data->fw_ddi = intel_get_mei_fw_ddi_index(PORT_NONE); > + } > > - data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port); > data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; > data->protocol = (u8)shim->protocol; > > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h > index 13555b054930..1041b2c11fe9 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdcp.h > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h > @@ -19,6 +19,8 @@ struct intel_hdcp_shim; > void intel_hdcp_atomic_check(struct drm_connector *connector, > struct drm_connector_state *old_state, > struct drm_connector_state *new_state); > +void intel_hdcp_transcoder_config(struct intel_connector *connector, > + enum transcoder trans); enum transcoder trancoder or enum transcoder cpu_transcoder. > int intel_hdcp_init(struct intel_connector *connector, > const struct intel_hdcp_shim *hdcp_shim); > int intel_hdcp_enable(struct intel_connector *connector, u8 content_type); > diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c > index e02f0faecf02..6e9bb6bd1ee2 100644 > --- a/drivers/gpu/drm/i915/display/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c > @@ -2431,6 +2431,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, > return -EINVAL; > } > > + intel_hdcp_transcoder_config(intel_hdmi->attached_connector, > + pipe_config->cpu_transcoder); > + > return 0; > }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 449abaea619f..c6b9f7198ee3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -388,6 +388,13 @@ struct intel_hdcp { wait_queue_head_t cp_irq_queue; atomic_t cp_irq_count; int cp_irq_count_cached; + + /* + * HDCP register access for gen12+ need the transcoder associated. + * Transcoder attached to the connector could be changed at modeset. + * Hence caching the transcoder here. + */ + enum transcoder trans; }; struct intel_connector { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 921ad0a2f7ba..ba5317d56da7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2244,6 +2244,9 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_psr_compute_config(intel_dp, pipe_config); + intel_hdcp_transcoder_config(intel_connector, + pipe_config->cpu_transcoder); + return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 534832f435dc..264bda5d484c 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1762,13 +1762,60 @@ enum mei_fw_ddi intel_get_mei_fw_ddi_index(enum port port) } } +static inline +enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder tc) +{ + switch (tc) { + case TRANSCODER_A ... TRANSCODER_D: + return (enum mei_fw_tc)(tc | 0x10); + case TRANSCODER_EDP: + return MEI_TC_EDP; + case TRANSCODER_DSI_0: + return MEI_TC_DSI0; + case TRANSCODER_DSI_1: + return MEI_TC_DSI1; + default: + return MEI_INVALID_TRANSCODER; + } +} + +void intel_hdcp_transcoder_config(struct intel_connector *connector, + enum transcoder trans) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_hdcp *hdcp = &connector->hdcp; + + if (!hdcp->shim) + return; + + if (INTEL_GEN(dev_priv) >= 12) { + mutex_lock(&hdcp->mutex); + hdcp->trans = trans; + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(trans); + mutex_unlock(&hdcp->mutex); + } +} + static inline int initialize_hdcp_port_data(struct intel_connector *connector, const struct intel_hdcp_shim *shim) { + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; struct hdcp_port_data *data = &hdcp->port_data; + struct intel_crtc *crtc; + + if (INTEL_GEN(dev_priv) < 12) { + data->fw_ddi = + intel_get_mei_fw_ddi_index(connector->encoder->port); + } else { + crtc = to_intel_crtc(connector->base.state->crtc); + if (crtc) { + hdcp->trans = crtc->config->cpu_transcoder; + data->fw_tc = intel_get_mei_fw_tc(hdcp->trans); + } + data->fw_ddi = intel_get_mei_fw_ddi_index(PORT_NONE); + } - data->fw_ddi = intel_get_mei_fw_ddi_index(connector->encoder->port); data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; data->protocol = (u8)shim->protocol; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h index 13555b054930..1041b2c11fe9 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h @@ -19,6 +19,8 @@ struct intel_hdcp_shim; void intel_hdcp_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); +void intel_hdcp_transcoder_config(struct intel_connector *connector, + enum transcoder trans); int intel_hdcp_init(struct intel_connector *connector, const struct intel_hdcp_shim *hdcp_shim); int intel_hdcp_enable(struct intel_connector *connector, u8 content_type); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index e02f0faecf02..6e9bb6bd1ee2 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -2431,6 +2431,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, return -EINVAL; } + intel_hdcp_transcoder_config(intel_hdmi->attached_connector, + pipe_config->cpu_transcoder); + return 0; }
On gen12+ platforms, HDCP HW is associated to the transcoder. Hence on every modeset associated transcoder is updated into the intel_hdcp. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- .../drm/i915/display/intel_display_types.h | 7 +++ drivers/gpu/drm/i915/display/intel_dp.c | 3 ++ drivers/gpu/drm/i915/display/intel_hdcp.c | 49 ++++++++++++++++++- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 + drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++ 5 files changed, 63 insertions(+), 1 deletion(-)