diff mbox series

[v5,06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h

Message ID 1566537069-22741-7-git-send-email-bmeng.cn@gmail.com (mailing list archive)
State New, archived
Headers show
Series riscv: sifive_u: Improve the emulation fidelity of sifive_u machine | expand

Commit Message

Bin Meng Aug. 23, 2019, 5:10 a.m. UTC
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

Changes in v5:
- new patch to remove the unnecessary include of target/riscv/cpu.h

Changes in v4: None
Changes in v3: None
Changes in v2: None

 hw/riscv/sifive_prci.c | 1 -
 hw/riscv/sifive_test.c | 1 -
 hw/riscv/sifive_uart.c | 1 -
 3 files changed, 3 deletions(-)

Comments

Alistair Francis Aug. 23, 2019, 5:38 p.m. UTC | #1
On Thu, Aug 22, 2019 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> The inclusion of "target/riscv/cpu.h" is unnecessary in various
> sifive model drivers.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> Changes in v5:
> - new patch to remove the unnecessary include of target/riscv/cpu.h
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/sifive_prci.c | 1 -
>  hw/riscv/sifive_test.c | 1 -
>  hw/riscv/sifive_uart.c | 1 -
>  3 files changed, 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
> index 1ab98d4..1957dcd 100644
> --- a/hw/riscv/sifive_prci.c
> +++ b/hw/riscv/sifive_prci.c
> @@ -22,7 +22,6 @@
>  #include "hw/sysbus.h"
>  #include "qemu/log.h"
>  #include "qemu/module.h"
> -#include "target/riscv/cpu.h"
>  #include "hw/riscv/sifive_prci.h"
>
>  static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
> diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> index 655a3d7..31cad9f 100644
> --- a/hw/riscv/sifive_test.c
> +++ b/hw/riscv/sifive_test.c
> @@ -23,7 +23,6 @@
>  #include "qemu/log.h"
>  #include "qemu/module.h"
>  #include "sysemu/sysemu.h"
> -#include "target/riscv/cpu.h"
>  #include "hw/riscv/sifive_test.h"
>
>  static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
> diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
> index cd74043..1601bd9 100644
> --- a/hw/riscv/sifive_uart.c
> +++ b/hw/riscv/sifive_uart.c
> @@ -22,7 +22,6 @@
>  #include "hw/sysbus.h"
>  #include "chardev/char.h"
>  #include "chardev/char-fe.h"
> -#include "target/riscv/cpu.h"
>  #include "hw/riscv/sifive_uart.h"
>
>  /*
> --
> 2.7.4
>
>
diff mbox series

Patch

diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 1ab98d4..1957dcd 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -22,7 +22,6 @@ 
 #include "hw/sysbus.h"
 #include "qemu/log.h"
 #include "qemu/module.h"
-#include "target/riscv/cpu.h"
 #include "hw/riscv/sifive_prci.h"
 
 static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size)
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 655a3d7..31cad9f 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -23,7 +23,6 @@ 
 #include "qemu/log.h"
 #include "qemu/module.h"
 #include "sysemu/sysemu.h"
-#include "target/riscv/cpu.h"
 #include "hw/riscv/sifive_test.h"
 
 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index cd74043..1601bd9 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -22,7 +22,6 @@ 
 #include "hw/sysbus.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
-#include "target/riscv/cpu.h"
 #include "hw/riscv/sifive_uart.h"
 
 /*