diff mbox series

[4/6] PCI: mobiveil: Add workaround for unsupported request error

Message ID 20190916021742.22844-5-xiaowei.bao@nxp.com (mailing list archive)
State Superseded, archived
Headers show
Series Add the Mobiveil EP and Layerscape Gen4 EP driver support | expand

Commit Message

Xiaowei Bao Sept. 16, 2019, 2:17 a.m. UTC 
Errata: unsupported request error on inbound posted write
transaction, PCIe controller reports advisory error instead
of uncorrectable error message to RC.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
---
 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
 drivers/pci/controller/mobiveil/pcie-mobiveil.h           |  4 ++++
 2 files changed, 17 insertions(+)

Comments

Russell King (Oracle) Sept. 24, 2019, 4:49 p.m. UTC | #1 
On Mon, Sep 16, 2019 at 10:17:40AM +0800, Xiaowei Bao wrote:
> Errata: unsupported request error on inbound posted write
> transaction, PCIe controller reports advisory error instead
> of uncorrectable error message to RC.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> ---
>  drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13 +++++++++++++
>  drivers/pci/controller/mobiveil/pcie-mobiveil.h           |  4 ++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> index 7bfec51..5bc9ed7 100644
> --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> @@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
>  	struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
>  	int win_idx;
>  	u8 bar;
> +	u32 val;
> +
> +	/*
> +	 * Errata: unsupported request error on inbound posted write
> +	 * transaction, PCIe controller reports advisory error instead
> +	 * of uncorrectable error message to RC.
> +	 * workaround: set the bit20(unsupported_request_Error_severity) with
> +	 * value 1 in uncorrectable_Error_Severity_Register, make the
> +	 * unsupported request error generate the fatal error.
> +	 */
> +	val =  csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
> +	val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;

	       BIT(UNSUPPORTED_REQUEST_ERROR_SHIFT) ?

> +	csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
>  
>  	ep->bar_num = PCIE_LX2_BAR_NUM;
>  
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> index 7308fa4..a40707e 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> @@ -123,6 +123,10 @@
>  #define GPEX_BAR_SIZE_UDW		0x4DC
>  #define GPEX_BAR_SELECT			0x4E0
>  
> +#define CFG_UNCORRECTABLE_ERROR_SEVERITY	0x10c
> +#define UNSUPPORTED_REQUEST_ERROR_SHIFT		20
> +#define CFG_UNCORRECTABLE_ERROR_MASK		0x108
> +
>  /* starting offset of INTX bits in status register */
>  #define PAB_INTX_START			5
>  
> -- 
> 2.9.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
Xiaowei Bao Oct. 15, 2019, 7:46 a.m. UTC | #2 
> -----Original Message-----
> From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
> Sent: 2019年9月25日 0:50
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Z.q. Hou <zhiqiang.hou@nxp.com>; bhelgaas@google.com;
> robh+dt@kernel.org; mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com; M.h. Lian
> <minghuan.lian@nxp.com>; andrew.murray@arm.com; Mingkai Hu
> <mingkai.hu@nxp.com>; linux-pci@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 4/6] PCI: mobiveil: Add workaround for unsupported
> request error
> 
> On Mon, Sep 16, 2019 at 10:17:40AM +0800, Xiaowei Bao wrote:
> > Errata: unsupported request error on inbound posted write transaction,
> > PCIe controller reports advisory error instead of uncorrectable error
> > message to RC.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > ---
> >  drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c | 13
> +++++++++++++
> >  drivers/pci/controller/mobiveil/pcie-mobiveil.h           |  4 ++++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> > b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> > index 7bfec51..5bc9ed7 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> > +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
> > @@ -49,6 +49,19 @@ static void ls_pcie_g4_ep_init(struct
> mobiveil_pcie_ep *ep)
> >  	struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
> >  	int win_idx;
> >  	u8 bar;
> > +	u32 val;
> > +
> > +	/*
> > +	 * Errata: unsupported request error on inbound posted write
> > +	 * transaction, PCIe controller reports advisory error instead
> > +	 * of uncorrectable error message to RC.
> > +	 * workaround: set the bit20(unsupported_request_Error_severity) with
> > +	 * value 1 in uncorrectable_Error_Severity_Register, make the
> > +	 * unsupported request error generate the fatal error.
> > +	 */
> > +	val =  csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
> > +	val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
> 
> 	       BIT(UNSUPPORTED_REQUEST_ERROR_SHIFT) ?

OK, thanks

Thanks 
Xiaowei

> 
> > +	csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
> >
> >  	ep->bar_num = PCIE_LX2_BAR_NUM;
> >
> > diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > index 7308fa4..a40707e 100644
> > --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
> > @@ -123,6 +123,10 @@
> >  #define GPEX_BAR_SIZE_UDW		0x4DC
> >  #define GPEX_BAR_SELECT			0x4E0
> >
> > +#define CFG_UNCORRECTABLE_ERROR_SEVERITY	0x10c
> > +#define UNSUPPORTED_REQUEST_ERROR_SHIFT		20
> > +#define CFG_UNCORRECTABLE_ERROR_MASK		0x108
> > +
> >  /* starting offset of INTX bits in status register */
> >  #define PAB_INTX_START			5
> >
> > --
> > 2.9.5
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists
> > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=02%
> 7C0
> >
> 1%7Cxiaowei.bao%40nxp.com%7C7dcebcdf565143413a7708d7410f34f5%7C
> 686ea1d
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> >
> 
> --
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diff mbox series

Patch

diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
index 7bfec51..5bc9ed7 100644
--- a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
+++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
@@ -49,6 +49,19 @@  static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
 	struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
 	int win_idx;
 	u8 bar;
+	u32 val;
+
+	/*
+	 * Errata: unsupported request error on inbound posted write
+	 * transaction, PCIe controller reports advisory error instead
+	 * of uncorrectable error message to RC.
+	 * workaround: set the bit20(unsupported_request_Error_severity) with
+	 * value 1 in uncorrectable_Error_Severity_Register, make the
+	 * unsupported request error generate the fatal error.
+	 */
+	val =  csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
+	val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
+	csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
 
 	ep->bar_num = PCIE_LX2_BAR_NUM;
 
diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
index 7308fa4..a40707e 100644
--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
@@ -123,6 +123,10 @@ 
 #define GPEX_BAR_SIZE_UDW		0x4DC
 #define GPEX_BAR_SELECT			0x4E0
 
+#define CFG_UNCORRECTABLE_ERROR_SEVERITY	0x10c
+#define UNSUPPORTED_REQUEST_ERROR_SHIFT		20
+#define CFG_UNCORRECTABLE_ERROR_MASK		0x108
+
 /* starting offset of INTX bits in status register */
 #define PAB_INTX_START			5