| Message ID | 20191003081738.22101-2-anshuman.gupta@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DC3CO Support for TGL test with DC3CO IGT | expand |
On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote: > Adding following definition to i915_reg.h > 1. DC_STATE_EN register DC3CO bit fields and masks. > DC3CO enable bit will be used by driver to make DC3CO > ready for DMC f/w and status bit will be used as DC3CO > entry status. > 2. Transcoder EXITLINE register and its bit fields and mask. > Transcoder EXITLINE enable bit represents PSR2 idle frame > reset should be applied at exit line and exitlines mask > represent required number of scanlines at which DC3CO > exit happens. > > B.Specs:49196 > > v1: Use of REG_BIT and using extra space for EXITLINE_ macro > definition. [Animesh] > > Cc: Jani Nikula <jani.nikula@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Animesh Manna <animesh.manna@intel.com> > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > Reviewed-by: Imre Deak <imre.deak@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index eefd789b9a28..8fd93008214b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4144,6 +4144,7 @@ enum { > #define _VTOTAL_A 0x6000c > #define _VBLANK_A 0x60010 > #define _VSYNC_A 0x60014 > +#define _EXITLINE_A 0x60018 > #define _PIPEASRC 0x6001c > #define _BCLRPAT_A 0x60020 > #define _VSYNCSHIFT_A 0x60028 > @@ -4190,11 +4191,16 @@ enum { > #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) > #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) > #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) > +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) > #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) > #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) > #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) > #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) > > +#define EXITLINE_ENABLE REG_BIT(31) > +#define EXITLINE_MASK REG_GENMASK(12, 0) > +#define EXITLINE_SHIFT 0 Why are these defines hanging mid-air? > + > /* > * HSW+ eDP PSR registers > * > @@ -10288,6 +10294,8 @@ enum skl_power_gate { > /* GEN9 DC */ > #define DC_STATE_EN _MMIO(0x45504) > #define DC_STATE_DISABLE 0 > +#define DC_STATE_EN_DC3CO REG_BIT(30) > +#define DC_STATE_DC3CO_STATUS REG_BIT(29) > #define DC_STATE_EN_UPTO_DC5 (1 << 0) > #define DC_STATE_EN_DC9 (1 << 3) > #define DC_STATE_EN_UPTO_DC6 (2 << 0) > -- > 2.21.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On 2019-10-04 at 18:48:08 +0300, Ville Syrjälä wrote: > On Thu, Oct 03, 2019 at 01:47:33PM +0530, Anshuman Gupta wrote: > > Adding following definition to i915_reg.h > > 1. DC_STATE_EN register DC3CO bit fields and masks. > > DC3CO enable bit will be used by driver to make DC3CO > > ready for DMC f/w and status bit will be used as DC3CO > > entry status. > > 2. Transcoder EXITLINE register and its bit fields and mask. > > Transcoder EXITLINE enable bit represents PSR2 idle frame > > reset should be applied at exit line and exitlines mask > > represent required number of scanlines at which DC3CO > > exit happens. > > > > B.Specs:49196 > > > > v1: Use of REG_BIT and using extra space for EXITLINE_ macro > > definition. [Animesh] > > > > Cc: Jani Nikula <jani.nikula@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Animesh Manna <animesh.manna@intel.com> > > Reviewed-by: Animesh Manna <animesh.manna@intel.com> > > Reviewed-by: Imre Deak <imre.deak@intel.com> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index eefd789b9a28..8fd93008214b 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -4144,6 +4144,7 @@ enum { > > #define _VTOTAL_A 0x6000c > > #define _VBLANK_A 0x60010 > > #define _VSYNC_A 0x60014 > > +#define _EXITLINE_A 0x60018 > > #define _PIPEASRC 0x6001c > > #define _BCLRPAT_A 0x60020 > > #define _VSYNCSHIFT_A 0x60028 > > @@ -4190,11 +4191,16 @@ enum { > > #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) > > #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) > > #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) > > +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) > > #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) > > #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) > > #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) > > #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) > > > > +#define EXITLINE_ENABLE REG_BIT(31) > > +#define EXITLINE_MASK REG_GENMASK(12, 0) > > +#define EXITLINE_SHIFT 0 > > Why are these defines hanging mid-air? If i understand your comment correctly, the place these EXITLINE bit defines is not correct, and it should be moved after EXITLINE(trans) define, am i correct ? > > > + > > /* > > * HSW+ eDP PSR registers > > * > > @@ -10288,6 +10294,8 @@ enum skl_power_gate { > > /* GEN9 DC */ > > #define DC_STATE_EN _MMIO(0x45504) > > #define DC_STATE_DISABLE 0 > > +#define DC_STATE_EN_DC3CO REG_BIT(30) > > +#define DC_STATE_DC3CO_STATUS REG_BIT(29) > > #define DC_STATE_EN_UPTO_DC5 (1 << 0) > > #define DC_STATE_EN_DC9 (1 << 3) > > #define DC_STATE_EN_UPTO_DC6 (2 << 0) > > -- > > 2.21.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eefd789b9a28..8fd93008214b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4144,6 +4144,7 @@ enum { #define _VTOTAL_A 0x6000c #define _VBLANK_A 0x60010 #define _VSYNC_A 0x60014 +#define _EXITLINE_A 0x60018 #define _PIPEASRC 0x6001c #define _BCLRPAT_A 0x60020 #define _VSYNCSHIFT_A 0x60028 @@ -4190,11 +4191,16 @@ enum { #define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A) #define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A) #define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A) +#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A) #define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A) #define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A) #define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC) #define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A) +#define EXITLINE_ENABLE REG_BIT(31) +#define EXITLINE_MASK REG_GENMASK(12, 0) +#define EXITLINE_SHIFT 0 + /* * HSW+ eDP PSR registers * @@ -10288,6 +10294,8 @@ enum skl_power_gate { /* GEN9 DC */ #define DC_STATE_EN _MMIO(0x45504) #define DC_STATE_DISABLE 0 +#define DC_STATE_EN_DC3CO REG_BIT(30) +#define DC_STATE_DC3CO_STATUS REG_BIT(29) #define DC_STATE_EN_UPTO_DC5 (1 << 0) #define DC_STATE_EN_DC9 (1 << 3) #define DC_STATE_EN_UPTO_DC6 (2 << 0)
Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. DC3CO enable bit will be used by driver to make DC3CO ready for DMC f/w and status bit will be used as DC3CO entry status. 2. Transcoder EXITLINE register and its bit fields and mask. Transcoder EXITLINE enable bit represents PSR2 idle frame reset should be applied at exit line and exitlines mask represent required number of scanlines at which DC3CO exit happens. B.Specs:49196 v1: Use of REG_BIT and using extra space for EXITLINE_ macro definition. [Animesh] Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+)