[2/2] drm/i915/tgl: simplify the lrc register list for !RCS

Commit Message

Daniele Ceraolo Spurio Oct. 9, 2019, 11:04 p.m. UTC

There are small differences between the blitter and the video engines in
the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
blitter). Since we never explicitly set a value for those register and
given that we don't need to update the offsets in the lrc image when we
change engine within the class for virtual engine because the HW can
handle that, instead of having a separate define for the BCS we can
just restrict the programming to the part we're interested in, which is
common across the engines.

Bspec: 45584
Signed-off-by: Daniele Ceraolo Spurio <[e-mail]>
Cc: Chris Wilson <[e-mail]>
Cc: Mika Kuoppala <[e-mail]>
Cc: Stuart Summers <[e-mail]>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c | 66 ++++-------------------------
 1 file changed, 8 insertions(+), 58 deletions(-)

Comments

Chris Wilson Oct. 10, 2019, 9:03 a.m. UTC | #1

Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:24)
> There are small differences between the blitter and the video engines in
> the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
> blitter). Since we never explicitly set a value for those register and
> given that we don't need to update the offsets in the lrc image when we
> change engine within the class for virtual engine because the HW can
> handle that, instead of having a separate define for the BCS we can
> just restrict the programming to the part we're interested in, which is
> common across the engines.

Yeah, my thinking was to be as complete as possible so that if we needed
to apply register updates, we could. It was also a fascinating insight
into what was stored, I was planning on using it for doing
isolation testing (albeit that's a bit chicken-and-egg).

> Bspec: 45584
> Signed-off-by: Daniele Ceraolo Spurio <[e-mail]>
> Cc: Chris Wilson <[e-mail]>
> Cc: Mika Kuoppala <[e-mail]>
> Cc: Stuart Summers <[e-mail]>

No qualms about restricting ourselves to the bare essentials on the
basis that the context image is meant to be relative-addressed. It did
not improve stability of tgl-gem however.
Reviewed-by: Chris Wilson <[e-mail]>
-Chris

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 78a136c12385..488a19ab908d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -669,64 +669,6 @@  static const u8 gen12_xcs_offsets[] = {
 	REG16(0x274),
 	REG16(0x270),
 
-	NOP(13),
-	LRI(2, POSTED),
-	REG16(0x200),
-	REG16(0x204),
-
-	NOP(11),
-	LRI(50, POSTED),
-	REG16(0x588),
-	REG16(0x588),
-	REG16(0x588),
-	REG16(0x588),
-	REG16(0x588),
-	REG16(0x588),
-	REG(0x028),
-	REG(0x09c),
-	REG(0x0c0),
-	REG(0x178),
-	REG(0x17c),
-	REG16(0x358),
-	REG(0x170),
-	REG(0x150),
-	REG(0x154),
-	REG(0x158),
-	REG16(0x41c),
-	REG16(0x600),
-	REG16(0x604),
-	REG16(0x608),
-	REG16(0x60c),
-	REG16(0x610),
-	REG16(0x614),
-	REG16(0x618),
-	REG16(0x61c),
-	REG16(0x620),
-	REG16(0x624),
-	REG16(0x628),
-	REG16(0x62c),
-	REG16(0x630),
-	REG16(0x634),
-	REG16(0x638),
-	REG16(0x63c),
-	REG16(0x640),
-	REG16(0x644),
-	REG16(0x648),
-	REG16(0x64c),
-	REG16(0x650),
-	REG16(0x654),
-	REG16(0x658),
-	REG16(0x65c),
-	REG16(0x660),
-	REG16(0x664),
-	REG16(0x668),
-	REG16(0x66c),
-	REG16(0x670),
-	REG16(0x674),
-	REG16(0x678),
-	REG16(0x67c),
-	REG(0x068),
-
 	END(),
 };
 
@@ -857,6 +799,14 @@  static const u8 gen12_rcs_offsets[] = {
 
 static const u8 *reg_offsets(const struct intel_engine_cs *engine)
 {
+	/*
+	 * the gen12+ lists only have the register we program in the default
+	 * state because we don't need to update the offsets when using a
+	 * virtual engine.
+	 */
+	GEM_BUG_ON(INTEL_GEN(engine->i915) >= 12 &&
+		   !intel_engine_has_relative_mmio(engine));
+
 	if (engine->class == RENDER_CLASS) {
 		if (INTEL_GEN(engine->i915) >= 12)
 			return gen12_rcs_offsets;