| Message ID | 20191019004124.371929-5-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] drm/i915/display: Handle fused off display correctly | expand |
On Fri, Oct 18, 2019 at 05:41:24PM -0700, José Roberto de Souza wrote: > DSC could be fused off, so not all GEN10+ platforms will support it. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Martin Peres <martin.peres@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_device_info.c | 4 ++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 5 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 3792d143bea9..e01690701fdd 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + if (!INTEL_INFO(dev_priv)->display.has_dsc) > + return false; > + > /* On TGL, DSC is supported on all Pipes */ > if (INTEL_GEN(dev_priv) >= 12) > return true; > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index f2280709c8c9..09dbfea7c81f 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = { > GEN9_FEATURES, \ > GEN(10), \ > .ddb_size = 1024, \ > + .display.has_dsc = 1, \ > .has_coherent_ggtt = false, \ > GLK_COLORS > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 84fca4f3af5a..bfa301759b6c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7665,6 +7665,7 @@ enum { > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) > #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) > +#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) > > #define SKL_DSSM _MMIO(0x51004) > #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 97d962944e48..6a24e85c6d10 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > > if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > info->display.has_csr = 0; > + > + if (INTEL_GEN(dev_priv) >= 10 && > + (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) > + info->display.has_dsc = 0; > } > > /* Initialize slice/subslice/EU info */ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 118d922261e2..ba31d68bb7ba 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -136,6 +136,7 @@ enum intel_ppgtt_type { > func(has_ddi); \ > func(has_dp_mst); \ > func(has_dsb); \ > + func(has_dsc); \ > func(has_fbc); \ > func(has_gmch); \ > func(has_hdcp); \ > -- > 2.23.0 >
On 2019-10-18 at 17:41:24 -0700, José Roberto de Souza wrote: > DSC could be fused off, so not all GEN10+ platforms will support it. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Martin Peres <martin.peres@linux.intel.com> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Looks good to me. Reviewed-by: Ramalingam C <ramalingam.c@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ > drivers/gpu/drm/i915/i915_pci.c | 1 + > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_device_info.c | 4 ++++ > drivers/gpu/drm/i915/intel_device_info.h | 1 + > 5 files changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 3792d143bea9..e01690701fdd 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > + if (!INTEL_INFO(dev_priv)->display.has_dsc) > + return false; > + > /* On TGL, DSC is supported on all Pipes */ > if (INTEL_GEN(dev_priv) >= 12) > return true; > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index f2280709c8c9..09dbfea7c81f 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/drivers/gpu/drm/i915/i915_pci.c > @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = { > GEN9_FEATURES, \ > GEN(10), \ > .ddb_size = 1024, \ > + .display.has_dsc = 1, \ > .has_coherent_ggtt = false, \ > GLK_COLORS > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 84fca4f3af5a..bfa301759b6c 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7665,6 +7665,7 @@ enum { > #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) > #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) > #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) > +#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) > > #define SKL_DSSM _MMIO(0x51004) > #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 97d962944e48..6a24e85c6d10 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) > > if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) > info->display.has_csr = 0; > + > + if (INTEL_GEN(dev_priv) >= 10 && > + (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) > + info->display.has_dsc = 0; > } > > /* Initialize slice/subslice/EU info */ > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index 118d922261e2..ba31d68bb7ba 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -136,6 +136,7 @@ enum intel_ppgtt_type { > func(has_ddi); \ > func(has_dp_mst); \ > func(has_dsb); \ > + func(has_dsc); \ > func(has_fbc); \ > func(has_gmch); \ > func(has_hdcp); \ > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 3792d143bea9..e01690701fdd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1888,6 +1888,9 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + if (!INTEL_INFO(dev_priv)->display.has_dsc) + return false; + /* On TGL, DSC is supported on all Pipes */ if (INTEL_GEN(dev_priv) >= 12) return true; diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index f2280709c8c9..09dbfea7c81f 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -737,6 +737,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = { GEN9_FEATURES, \ GEN(10), \ .ddb_size = 1024, \ + .display.has_dsc = 1, \ .has_coherent_ggtt = false, \ GLK_COLORS diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 84fca4f3af5a..bfa301759b6c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7665,6 +7665,7 @@ enum { #define SKL_DFSM_PIPE_B_DISABLE (1 << 21) #define SKL_DFSM_PIPE_C_DISABLE (1 << 28) #define TGL_DFSM_PIPE_D_DISABLE (1 << 22) +#define CNL_DFSM_DISPLAY_DSC_DISABLE (1 << 7) #define SKL_DSSM _MMIO(0x51004) #define CNL_DSSM_CDCLK_PLL_REFCLK_24MHz (1 << 31) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 97d962944e48..6a24e85c6d10 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -996,6 +996,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE)) info->display.has_csr = 0; + + if (INTEL_GEN(dev_priv) >= 10 && + (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE)) + info->display.has_dsc = 0; } /* Initialize slice/subslice/EU info */ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 118d922261e2..ba31d68bb7ba 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -136,6 +136,7 @@ enum intel_ppgtt_type { func(has_ddi); \ func(has_dp_mst); \ func(has_dsb); \ + func(has_dsc); \ func(has_fbc); \ func(has_gmch); \ func(has_hdcp); \
DSC could be fused off, so not all GEN10+ platforms will support it. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Martin Peres <martin.peres@linux.intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_device_info.c | 4 ++++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 5 files changed, 10 insertions(+)